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+/*
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+ * $Id$
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+ *
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+ * Copyright (C) 2006 iptelorg GmbH
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+ *
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+ * This file is part of ser, a free SIP server.
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+ *
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+ * ser is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version
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+ *
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+ * For a license to use the ser software under conditions
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+ * other than those described here, or to purchase support for this
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+ * software, please contact iptel.org by e-mail at the following addresses:
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+ * [email protected]
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+ *
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+ * ser is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ */
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+/*
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+ * atomic ops and memory barriers for arm (>= v3)
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+ * see atomic_ops.h for more details
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+ *
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+ * Config defines: - NOSMP
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+ * - __CPU_arm
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+ * - __CPU_arm6 - armv6 support (supports atomic ops
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+ * via ldrex/strex)
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+ */
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+/*
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+ * History:
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+ * --------
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+ * 2006-03-31 created by andrei
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+ */
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+
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+
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+#ifndef _atomic_arm_h
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+#define _atomic_arm_h
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+
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+
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+
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+#warning "arm atomic operations support not tested"
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+
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+#ifdef NOSMP
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+#define HAVE_ASM_INLINE_MEMBAR
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+#define membar() asm volatile ("" : : : "memory") /* gcc do not cache barrier*/
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+#define membar_read() membar()
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+#define membar_write() membar()
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+#else /* SMP */
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+#warning SMP not supported for arm atomic ops, try compiling with -DNOSMP
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+/* fall back to default lock based barriers (don't define HAVE_ASM...) */
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+#endif /* NOSMP */
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+
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+
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+#ifdef __CPU_arm6
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+
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+
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+#define HAVE_ASM_INLINE_ATOMIC_OPS
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+
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+/* hack to get some membars */
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+#ifndef NOSMP
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+#include "atomic_unknown.h"
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+#endif
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+
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+/* main asm block
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+ * use %0 as input and write the output in %1*/
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+#define ATOMIC_ASM_OP(op) \
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+ "1: ldrex %0, [%3] \n\t" \
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+ " " op "\n\t" \
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+ " strex %0, %1, [%3] \n\t" \
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+ " cmp %0, #0 \n\t" \
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+ " bne 1b \n\t"
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+
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+/* same as above but writes %4 instead of %1, and %0 will contain
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+ * the prev. val*/
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+#define ATOMIC_ASM_OP2(op) \
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+ "1: ldrex %0, [%3] \n\t" \
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+ " " op "\n\t" \
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+ " strex %1, %4, [%3] \n\t" \
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+ " cmp %1, #0 \n\t" \
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+ " bne 1b \n\t"
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+
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+/* no extra param, %0 contains *var, %1 should contain the result */
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+#define ATOMIC_FUNC_DECL(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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+ inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var) \
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+ { \
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+ P_TYPE ret, tmp; \
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+ asm volatile( \
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+ ATOMIC_ASM_OP(OP) \
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+ : "=&r"(tmp), "=&r"(ret), "=m"(*var) : "r"(var) : "cc" \
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+ ); \
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+ return RET_EXPR; \
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+ }
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+
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+/* one extra param in %4 */
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+#define ATOMIC_FUNC_DECL1(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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+ inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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+ P_TYPE v) \
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+ { \
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+ P_TYPE ret, tmp; \
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+ asm volatile( \
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+ ATOMIC_ASM_OP(OP) \
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+ : "=&r"(tmp), "=&r"(ret), "=m"(*var) : "r"(var), "r"(v) : "cc" \
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+ ); \
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+ return RET_EXPR; \
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+ }
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+
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+
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+/* as above, but %4 should contain the result, and %0 is returned*/
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+#define ATOMIC_FUNC_DECL2(NAME, OP, P_TYPE, RET_TYPE, RET_EXPR) \
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+ inline static RET_TYPE atomic_##NAME##_##P_TYPE (volatile P_TYPE *var, \
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+ P_TYPE v) \
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+ { \
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+ P_TYPE ret, tmp; \
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+ asm volatile( \
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+ ATOMIC_ASM_OP2(OP) \
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+ : "=&r"(ret), "=&r"(tmp), "=m"(*var) : "r"(var), "r"(v) : "cc" \
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+ ); \
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+ return RET_EXPR; \
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+ }
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+
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+
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+
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+ATOMIC_FUNC_DECL(inc, "add %1, %0, #1", int, void, /* no return */ )
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+ATOMIC_FUNC_DECL(dec, "sub %1, %0, #1", int, void, /* no return */ )
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+ATOMIC_FUNC_DECL1(and, "and %1, %0, %4", int, void, /* no return */ )
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+ATOMIC_FUNC_DECL1(or, "orr %1, %0, %4", int, void, /* no return */ )
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+ATOMIC_FUNC_DECL(inc_and_test, "add %1, %0, #1", int, int, ret )
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+ATOMIC_FUNC_DECL(dec_and_test, "sub %1, %0, #1", int, int, ret )
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+ATOMIC_FUNC_DECL2(get_and_set, /* no extra op needed */ , int, int, ret)
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+
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+ATOMIC_FUNC_DECL(inc, "add %1, %0, #1", long, void, /* no return */ )
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+ATOMIC_FUNC_DECL(dec, "sub %1, %0, #1", long, void, /* no return */ )
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+ATOMIC_FUNC_DECL1(and, "and %1, %0, %4", long, void, /* no return */ )
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+ATOMIC_FUNC_DECL1(or, "orr %1, %0, %4", long, void, /* no return */ )
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+ATOMIC_FUNC_DECL(inc_and_test, "add %1, %0, #1", long, long, ret )
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+ATOMIC_FUNC_DECL(dec_and_test, "sub %1, %0, #1", long, long, ret )
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+ATOMIC_FUNC_DECL2(get_and_set, /* no extra op needed */ , long, long, ret)
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+
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+#define atomic_inc(var) atomic_inc_int(&(var)->val)
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+#define atomic_dec(var) atomic_dec_int(&(var)->val)
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+#define atomic_and(var, mask) atomic_and_int(&(var)->val, (mask))
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+#define atomic_or(var, mask) atomic_or_int(&(var)->val, (mask))
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+#define atomic_dec_and_test(var) atomic_dec_and_test_int(&(var)->val)
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+#define atomic_inc_and_test(var) atomic_inc_and_test_int(&(var)->val)
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+#define atomic_get_and_set(var, i) atomic_get_and_set_int(&(var)->val, i)
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+
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+
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+/* with integrated membar */
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+
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+#define mb_atomic_set_int(v, i) \
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+ do{ \
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+ membar(); \
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+ atomic_set_int(v, i); \
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+ }while(0)
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+
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+
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+
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+inline static int mb_atomic_get_int(volatile int* v)
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+{
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+ membar();
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+ return atomic_get_int(v);
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+}
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+
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+
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+#define mb_atomic_inc_int(v) \
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+ do{ \
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+ membar(); \
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+ atomic_inc_int(v); \
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+ }while(0)
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+
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+#define mb_atomic_dec_int(v) \
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+ do{ \
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+ membar(); \
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+ atomic_dec_int(v); \
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+ }while(0)
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+
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+#define mb_atomic_or_int(v, m) \
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+ do{ \
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+ membar(); \
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+ atomic_or_int(v, m); \
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+ }while(0)
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+
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+#define mb_atomic_and_int(v, m) \
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+ do{ \
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+ membar(); \
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+ atomic_and_int(v, m); \
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+ }while(0)
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+
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+inline static int mb_atomic_inc_and_test_int(volatile int* v)
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+{
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+ membar();
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+ return atomic_inc_and_test_int(v);
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+}
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+
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+inline static int mb_atomic_dec_and_test_int(volatile int* v)
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+{
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+ membar();
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+ return atomic_dec_and_test_int(v);
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+}
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+
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+
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+inline static int mb_atomic_get_and_set_int(volatile int* v, int i)
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+{
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+ membar();
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+ return atomic_get_and_set_int(v, i);
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+}
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+
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+
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+
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+#define mb_atomic_set_long(v, i) \
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+ do{ \
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+ membar(); \
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+ atomic_set_long(v, i); \
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+ }while(0)
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+
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+
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+
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+inline static long mb_atomic_get_long(volatile long* v)
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+{
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+ membar();
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+ return atomic_get_long(v);
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+}
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+
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+
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+#define mb_atomic_inc_long(v) \
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+ do{ \
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+ membar(); \
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+ atomic_inc_long(v); \
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+ }while(0)
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+
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+
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+#define mb_atomic_dec_long(v) \
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+ do{ \
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+ membar(); \
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+ atomic_dec_long(v); \
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+ }while(0)
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+
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+#define mb_atomic_or_long(v, m) \
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+ do{ \
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+ membar(); \
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+ atomic_or_long(v, m); \
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+ }while(0)
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+
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+#define mb_atomic_and_long(v, m) \
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+ do{ \
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+ membar(); \
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+ atomic_and_long(v, m); \
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+ }while(0)
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+
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+inline static long mb_atomic_inc_and_test_long(volatile long* v)
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+{
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+ membar();
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+ return atomic_inc_and_test_long(v);
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+}
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+
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+inline static long mb_atomic_dec_and_test_long(volatile long* v)
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+{
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+ membar();
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+ return atomic_dec_and_test_long(v);
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+}
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+
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+
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+inline static long mb_atomic_get_and_set_long(volatile long* v, long l)
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+{
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+ membar();
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+ return atomic_get_and_set_long(v, l);
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+}
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+
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+
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+#define mb_atomic_inc(var) mb_atomic_inc_int(&(var)->val)
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+#define mb_atomic_dec(var) mb_atomic_dec_int(&(var)->val)
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+#define mb_atomic_and(var, mask) mb_atomic_and_int(&(var)->val, (mask))
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+#define mb_atomic_or(var, mask) mb_atomic_or_int(&(var)->val, (mask))
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+#define mb_atomic_dec_and_test(var) mb_atomic_dec_and_test_int(&(var)->val)
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+#define mb_atomic_inc_and_test(var) mb_atomic_inc_and_test_int(&(var)->val)
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+#define mb_atomic_get(var) mb_atomic_get_int(&(var)->val)
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+#define mb_atomic_set(var, i) mb_atomic_set_int(&(var)->val, i)
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+#define mb_atomic_get_and_set(var, i) mb_atomic_get_and_set_int(&(var)->val, i)
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+
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+
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+#else /* ! __CPU_arm6 => __CPU_arm */
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+
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+/* no atomic ops for v <6 , only SWP supported
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+ * Atomic ops could be implemented if one bit is sacrificed and used like
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+ * a spinlock, e.g:
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+ * mov %r0, #0x1
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+ * 1: swp %r1, %r0, [&atomic_val]
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+ * if (%r1 & 0x1) goto 1 # wait if first bit is 1
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+ * %r1>>=1 # restore the value (only 31 bits can be used )
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+ * %r1=op (%r1, ...)
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+ * %r1<<=1 # shift back the value, such that the first bit is 0
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+ * str %r1, [&atomic_val] # write the value
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+ *
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+ * However only 31 bits could be used (=> atomic_*_int and atomic_*_long
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+ * would still have to be lock based, since in these cases we guarantee all
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+ * the bits) and I'm not sure there would be a significant performance
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+ * benefit when compared with the fallback lock based version:
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+ * lock(atomic_lock);
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+ * atomic_val=op(*atomic_val, ...)
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+ * unlock(atomic_lock);
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+ *
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+ * -- andrei
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+ */
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+
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+#endif /* __CPU_arm6 */
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+
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+
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+#endif
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Andrei Pelinescu-Onciul