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@@ -51,6 +51,8 @@
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* fix (andrei)
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* 2006-04-04 sparc* optimizations, sparc32 smp support, armv6 no smp support,
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* ppc, mips*, alpha optimizations (andrei)
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+ * 2006-04-05 ppc fixes (s/stw/stwx/, s/lwz/lwzx), early clobber added
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+ * where needed (andrei)
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*
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*/
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@@ -170,7 +172,7 @@ inline static int tsl(fl_lock_t* lock)
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" xor %0, %0 \n\t"
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" btsl $0, %2 \n\t"
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" setc %b0 \n\t"
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- : "=q" (val), "=m" (*lock) : "m"(*lock) : "memory", "cc"
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+ : "=&q" (val), "=m" (*lock) : "m"(*lock) : "memory", "cc"
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);
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#else
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asm volatile(
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@@ -183,7 +185,7 @@ inline static int tsl(fl_lock_t* lock)
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#endif
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" xchgb %2, %b0 \n\t"
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"1: \n\t"
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- : "=q" (val), "=m" (*lock) : "m"(*lock) : "memory"
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+ : "=&q" (val), "=m" (*lock) : "m"(*lock) : "memory"
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#ifdef SPIN_OPTIMIZE
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, "cc"
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#endif
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@@ -199,7 +201,7 @@ inline static int tsl(fl_lock_t* lock)
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" ldstub [%2], %0 \n\t"
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"1: \n\t"
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/* membar_getlock must be called outside this function */
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- : "=r"(val), "=m"(*lock) : "r"(lock): "memory"
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+ : "=&r"(val), "=m"(*lock) : "r"(lock): "memory"
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);
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#elif defined(__CPU_sparc)
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asm volatile(
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@@ -212,7 +214,7 @@ inline static int tsl(fl_lock_t* lock)
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" ldstub [%2], %0 \n\t"
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"1: \n\t"
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/* membar_getlock must be called outside this function */
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- : "=r"(val), "=m"(*lock) : "r"(lock): "memory"
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+ : "=&r"(val), "=m"(*lock) : "r"(lock): "memory"
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#ifdef SPIN_OPTIMIZE
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, "cc"
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#endif
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@@ -230,13 +232,13 @@ inline static int tsl(fl_lock_t* lock)
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/* if %0!=0 => either it was 1 initially or was 0
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* and somebody changed it just before the strexeq (so the
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* lock is taken) => it's safe to return %0 */
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- : "=r"(val), "=m"(*lock) : "r"(lock), "r"(1) : "cc"
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+ : "=&r"(val), "=m"(*lock) : "r"(lock), "r"(1) : "cc"
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);
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#elif defined(__CPU_ppc) || defined(__CPU_ppc64)
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asm volatile(
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"1: \n\t"
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#ifdef SPIN_OPTIMIZE
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- " lwz %0, 0, (%2) \n\t"
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+ " lwzx %0, 0, %2 \n\t"
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" cmpwi %0, 0 \n\t"
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" bne- 2f \n\t" /* predict: not taken */
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#endif
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@@ -247,7 +249,7 @@ inline static int tsl(fl_lock_t* lock)
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" bne- 1b\n\t"
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/* membar_getlock must be called outside this function */
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"2:\n\t"
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- : "=r" (val), "=m"(*lock) : "r" (lock), "r"(1) : "memory", "cc"
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+ : "=&r" (val), "=m"(*lock) : "r"(lock), "r"(1) : "memory", "cc"
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);
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#elif defined __CPU_mips2 || ( defined __CPU_mips && defined MIPS_HAS_LLSC ) \
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|| defined __CPU_mips64
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@@ -293,7 +295,7 @@ inline static int tsl(fl_lock_t* lock)
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".subsection 2 \n\t"
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"3: br 1b \n\t"
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".previous \n\t"
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- :"=&r" (val), "=m"(*lock), "=r"(tmp)
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+ :"=&r" (val), "=m"(*lock), "=&r"(tmp)
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:"m"(*lock)
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: "memory"
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);
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@@ -388,8 +390,8 @@ inline static void release_lock(fl_lock_t* lock)
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* [IBM Prgramming Environments Manual, D.4.2.2]
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*/
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"lwsync\n\t"
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- "stw %1, 0(%2)\n\t"
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- : "=m"(*lock) : "r"(0), "r" (lock) : "memory"
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+ "stwx %1, 0, %2\n\t"
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+ : "=m"(*lock) : "r"(0), "r"(lock) : "memory"
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);
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#elif defined __CPU_mips2 || ( defined __CPU_mips && defined MIPS_HAS_LLSC ) \
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|| defined __CPU_mips64
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Andrei Pelinescu-Onciul