[spirv] Update sm6 tests (use uint for scope).

tools/clang/include/clang/SPIRV/EmitVisitor.h

@@ -206,7 +206,7 @@ public:
   /// \brief The struct representing a SPIR-V module header.
   struct Header {
     /// \brief Default constructs a SPIR-V module header with id bound 0.
-    Header(uint32_t bound);
+    Header(uint32_t bound, uint32_t version);
 
     /// \brief Feeds the consumer with all the SPIR-V words for this header.
     std::vector<uint32_t> takeBinary();

tools/clang/lib/SPIRV/EmitVisitor.cpp

@@ -113,10 +113,10 @@ uint32_t signExtendTo32Bits(int16_t value) {
 namespace clang {
 namespace spirv {
 
-EmitVisitor::Header::Header(uint32_t bound_)
+EmitVisitor::Header::Header(uint32_t bound_, uint32_t version_)
     // We are using the unfied header, which shows spv::Version as the newest
     // version. But we need to stick to 1.0 for Vulkan consumption by default.
-    : magicNumber(spv::MagicNumber), version(0x00010000),
+    : magicNumber(spv::MagicNumber), version(version_),
       generator((kGeneratorNumber << 16) | kToolVersion), bound(bound_),
       reserved(0) {}
 
@@ -210,7 +210,8 @@ void EmitVisitor::finalizeInstruction() {
 
 std::vector<uint32_t> EmitVisitor::takeBinary() {
   std::vector<uint32_t> result;
-  Header header(takeNextId());
+  Header header(takeNextId(),
+                spvOptions.targetEnv == "vulkan1.1" ? 0x00010300u : 0x00010000);
   auto headerBinary = header.takeBinary();
   result.insert(result.end(), headerBinary.begin(), headerBinary.end());
   result.insert(result.end(), preambleBinary.begin(), preambleBinary.end());
@@ -537,10 +538,13 @@ bool EmitVisitor::visit(SpirvAtomic *inst) {
     curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst));
   }
   curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst->getPointer()));
-  curInst.push_back(static_cast<uint32_t>(inst->getScope()));
-  curInst.push_back(static_cast<uint32_t>(inst->getMemorySemantics()));
+  curInst.push_back(typeHandler.getOrCreateConstantUint32(
+      static_cast<uint32_t>(inst->getScope())));
+  curInst.push_back(typeHandler.getOrCreateConstantUint32(
+      static_cast<uint32_t>(inst->getMemorySemantics())));
   if (inst->hasComparator())
-    curInst.push_back(static_cast<uint32_t>(inst->getMemorySemanticsUnequal()));
+    curInst.push_back(typeHandler.getOrCreateConstantUint32(
+        static_cast<uint32_t>(inst->getMemorySemanticsUnequal())));
   if (inst->hasValue())
     curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst->getValue()));
   if (inst->hasComparator())
@@ -811,7 +815,8 @@ bool EmitVisitor::visit(SpirvNonUniformBinaryOp *inst) {
   initInstruction(inst);
   curInst.push_back(inst->getResultTypeId());
   curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst));
-  curInst.push_back(static_cast<uint32_t>(inst->getExecutionScope()));
+  curInst.push_back(typeHandler.getOrCreateConstantUint32(
+      static_cast<uint32_t>(inst->getExecutionScope())));
   curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst->getArg1()));
   curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst->getArg2()));
   finalizeInstruction();
@@ -824,7 +829,8 @@ bool EmitVisitor::visit(SpirvNonUniformElect *inst) {
   initInstruction(inst);
   curInst.push_back(inst->getResultTypeId());
   curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst));
-  curInst.push_back(static_cast<uint32_t>(inst->getExecutionScope()));
+  curInst.push_back(typeHandler.getOrCreateConstantUint32(
+      static_cast<uint32_t>(inst->getExecutionScope())));
   finalizeInstruction();
   emitDebugNameForInstruction(getOrAssignResultId<SpirvInstruction>(inst),
                               inst->getDebugName());
@@ -835,7 +841,8 @@ bool EmitVisitor::visit(SpirvNonUniformUnaryOp *inst) {
   initInstruction(inst);
   curInst.push_back(inst->getResultTypeId());
   curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst));
-  curInst.push_back(static_cast<uint32_t>(inst->getExecutionScope()));
+  curInst.push_back(typeHandler.getOrCreateConstantUint32(
+      static_cast<uint32_t>(inst->getExecutionScope())));
   if (inst->hasGroupOp())
     curInst.push_back(static_cast<uint32_t>(inst->getGroupOp()));
   curInst.push_back(getOrAssignResultId<SpirvInstruction>(inst->getArg()));

tools/clang/test/CodeGenSPIRV/sm6.quad-read-across-diagonal.hlsl

@@ -21,12 +21,12 @@ void main(uint3 id: SV_DispatchThreadID) {
     float val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4int %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v4int %int_3 [[val1]] %uint_2
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v4int %uint_3 [[val1]] %uint_2
     values[x].val1 = QuadReadAcrossDiagonal(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v3uint %int_3 [[val2]] %uint_2
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v3uint %uint_3 [[val2]] %uint_2
     values[x].val2 = QuadReadAcrossDiagonal(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %float %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %float %int_3 [[val3]] %uint_2
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %float %uint_3 [[val3]] %uint_2
     values[x].val3 = QuadReadAcrossDiagonal(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.quad-read-across-x.hlsl

@@ -21,12 +21,12 @@ void main(uint3 id: SV_DispatchThreadID) {
     float val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4int %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v4int %int_3 [[val1]] %uint_0
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v4int %uint_3 [[val1]] %uint_0
     values[x].val1 = QuadReadAcrossX(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v3uint %int_3 [[val2]] %uint_0
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v3uint %uint_3 [[val2]] %uint_0
     values[x].val2 = QuadReadAcrossX(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %float %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %float %int_3 [[val3]] %uint_0
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %float %uint_3 [[val3]] %uint_0
     values[x].val3 = QuadReadAcrossX(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.quad-read-across-y.hlsl

@@ -21,12 +21,12 @@ void main(uint3 id: SV_DispatchThreadID) {
     float val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4int %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v4int %int_3 [[val1]] %uint_1
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v4int %uint_3 [[val1]] %uint_1
     values[x].val1 = QuadReadAcrossY(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v3uint %int_3 [[val2]] %uint_1
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %v3uint %uint_3 [[val2]] %uint_1
     values[x].val2 = QuadReadAcrossY(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %float %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %float %int_3 [[val3]] %uint_1
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadSwap %float %uint_3 [[val3]] %uint_1
     values[x].val3 = QuadReadAcrossY(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.quad-read-lane-at.hlsl

@@ -21,13 +21,13 @@ void main(uint3 id: SV_DispatchThreadID) {
        int val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4float %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadBroadcast %v4float %int_3 [[val1]] %uint_0
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadBroadcast %v4float %uint_3 [[val1]] %uint_0
     values[x].val1 = QuadReadLaneAt(val1, 0);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadBroadcast %v3uint %int_3 [[val2]] %uint_1
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadBroadcast %v3uint %uint_3 [[val2]] %uint_1
     values[x].val2 = QuadReadLaneAt(val2, 1);
 // CHECK:      [[val3:%\d+]] = OpLoad %int %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadBroadcast %int %int_3 [[val3]] %uint_2
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformQuadBroadcast %int %uint_3 [[val3]] %uint_2
     values[x].val3 = QuadReadLaneAt(val3, 2);
 }
 

tools/clang/test/CodeGenSPIRV/sm6.wave-active-all-equal.hlsl

@@ -18,10 +18,10 @@ void main(uint3 id: SV_DispatchThreadID) {
 // CHECK:         [[ptr:%\d+]] = OpAccessChain %_ptr_Uniform_v4float %values %int_0 {{%\d+}} %int_0
 // CHECK-NEXT: [[f32val:%\d+]] = OpLoad %v4float [[ptr]]
 // TODO: The front end will return bool4 for the first call, which acutally should be bool.
-// XXXXX-NEXT:        {{%\d+}} = OpGroupNonUniformAllEqual %bool %int_3 [[f32val]]
+// XXXXX-NEXT:        {{%\d+}} = OpGroupNonUniformAllEqual %bool %uint_3 [[f32val]]
 
 // CHECK:         [[ptr:%\d+]] = OpAccessChain %_ptr_Uniform_uint %values %int_0 {{%\d+}} %int_1
 // CHECK-NEXT: [[u32val:%\d+]] = OpLoad %uint [[ptr]]
-// CHECK-NEXT:        {{%\d+}} = OpGroupNonUniformAllEqual %bool %int_3 [[u32val]]
+// CHECK-NEXT:        {{%\d+}} = OpGroupNonUniformAllEqual %bool %uint_3 [[u32val]]
     values[x].res = WaveActiveAllEqual(values[x].val1) && WaveActiveAllEqual(values[x].val2);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-all-true.hlsl

@@ -15,6 +15,6 @@ RWStructuredBuffer<S> values;
 void main(uint3 id: SV_DispatchThreadID) {
     uint x = id.x;
 // CHECK:      [[cmp:%\d+]] = OpIEqual %bool {{%\d+}} %uint_1
-// CHECK-NEXT:     {{%\d+}} = OpGroupNonUniformAll %bool %int_3 [[cmp]]
+// CHECK-NEXT:     {{%\d+}} = OpGroupNonUniformAll %bool %uint_3 [[cmp]]
     values[x].res = WaveActiveAllTrue(values[x].val == 1);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-any-true.hlsl

@@ -15,6 +15,6 @@ RWStructuredBuffer<S> values;
 void main(uint3 id: SV_DispatchThreadID) {
     uint x = id.x;
 // CHECK:      [[cmp:%\d+]] = OpIEqual %bool {{%\d+}} %uint_0
-// CHECK-NEXT:     {{%\d+}} = OpGroupNonUniformAny %bool %int_3 [[cmp]]
+// CHECK-NEXT:     {{%\d+}} = OpGroupNonUniformAny %bool %uint_3 [[cmp]]
     values[x].res = WaveActiveAnyTrue(values[x].val == 0);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-ballot.hlsl

@@ -15,6 +15,6 @@ RWStructuredBuffer<S> values;
 void main(uint3 id: SV_DispatchThreadID) {
     uint x = id.x;
 // CHECK:      [[cmp:%\d+]] = OpIEqual %bool {{%\d+}} %uint_2
-// CHECK-NEXT:     {{%\d+}} = OpGroupNonUniformBallot %v4uint %int_3 [[cmp]]
+// CHECK-NEXT:     {{%\d+}} = OpGroupNonUniformBallot %v4uint %uint_3 [[cmp]]
     values[x].res = WaveActiveBallot(values[x].val == 2);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-bit-and.hlsl

@@ -24,15 +24,15 @@ void main(uint3 id: SV_DispatchThreadID) {
      uint val4 = values[x].val4;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4uint %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %v4uint %int_3 Reduce [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %v4uint %uint_3 Reduce [[val1]]
     values[x].val1 = WaveActiveBitAnd(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %v3uint %int_3 Reduce [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %v3uint %uint_3 Reduce [[val2]]
     values[x].val2 = WaveActiveBitAnd(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %v2uint %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %v2uint %int_3 Reduce [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %v2uint %uint_3 Reduce [[val3]]
     values[x].val3 = WaveActiveBitAnd(val3);
 // CHECK:      [[val4:%\d+]] = OpLoad %uint %val4
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %uint %int_3 Reduce [[val4]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseAnd %uint %uint_3 Reduce [[val4]]
     values[x].val4 = WaveActiveBitAnd(val4);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-bit-or.hlsl

@@ -24,15 +24,15 @@ void main(uint3 id: SV_DispatchThreadID) {
      uint val4 = values[x].val4;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4uint %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %v4uint %int_3 Reduce [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %v4uint %uint_3 Reduce [[val1]]
     values[x].val1 = WaveActiveBitOr(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %v3uint %int_3 Reduce [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %v3uint %uint_3 Reduce [[val2]]
     values[x].val2 = WaveActiveBitOr(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %v2uint %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %v2uint %int_3 Reduce [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %v2uint %uint_3 Reduce [[val3]]
     values[x].val3 = WaveActiveBitOr(val3);
 // CHECK:      [[val4:%\d+]] = OpLoad %uint %val4
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %uint %int_3 Reduce [[val4]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseOr %uint %uint_3 Reduce [[val4]]
     values[x].val4 = WaveActiveBitOr(val4);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-bit-xor.hlsl

@@ -24,15 +24,15 @@ void main(uint3 id: SV_DispatchThreadID) {
      uint val4 = values[x].val4;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4uint %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %v4uint %int_3 Reduce [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %v4uint %uint_3 Reduce [[val1]]
     values[x].val1 = WaveActiveBitXor(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %v3uint %int_3 Reduce [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %v3uint %uint_3 Reduce [[val2]]
     values[x].val2 = WaveActiveBitXor(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %v2uint %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %v2uint %int_3 Reduce [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %v2uint %uint_3 Reduce [[val3]]
     values[x].val3 = WaveActiveBitXor(val3);
 // CHECK:      [[val4:%\d+]] = OpLoad %uint %val4
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %uint %int_3 Reduce [[val4]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBitwiseXor %uint %uint_3 Reduce [[val4]]
     values[x].val4 = WaveActiveBitXor(val4);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-count-bits.hlsl

@@ -16,8 +16,8 @@ void main(uint3 id: SV_DispatchThreadID) {
     uint x = id.x;
 
 // CHECK:         [[cmp:%\d+]] = OpIEqual %bool {{%\d+}} %uint_0
-// CHECK-NEXT: [[ballot:%\d+]] = OpGroupNonUniformBallot %v4uint %int_3 [[cmp]]
-// CHECK:             {{%\d+}} = OpGroupNonUniformBallotBitCount %uint %int_3 Reduce [[ballot]]
+// CHECK-NEXT: [[ballot:%\d+]] = OpGroupNonUniformBallot %v4uint %uint_3 [[cmp]]
+// CHECK:             {{%\d+}} = OpGroupNonUniformBallotBitCount %uint %uint_3 Reduce [[ballot]]
     results[x].val = WaveActiveCountBits(values[x].val == 0);
 }
 

tools/clang/test/CodeGenSPIRV/sm6.wave-active-max.hlsl

@@ -20,12 +20,12 @@ void main(uint3 id: SV_DispatchThreadID) {
        int val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4uint %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformUMax %v4uint %int_3 Reduce [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformUMax %v4uint %uint_3 Reduce [[val1]]
     values[x].val1 = WaveActiveMax(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v2float %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMax %v2float %int_3 Reduce [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMax %v2float %uint_3 Reduce [[val2]]
     values[x].val2 = WaveActiveMax(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %int %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformSMax %int %int_3 Reduce [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformSMax %int %uint_3 Reduce [[val3]]
     values[x].val3 = WaveActiveMax(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-min.hlsl

@@ -20,12 +20,12 @@ void main(uint3 id: SV_DispatchThreadID) {
        int val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4uint %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformUMin %v4uint %int_3 Reduce [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformUMin %v4uint %uint_3 Reduce [[val1]]
     values[x].val1 = WaveActiveMin(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v2float %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMin %v2float %int_3 Reduce [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMin %v2float %uint_3 Reduce [[val2]]
     values[x].val2 = WaveActiveMin(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %int %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformSMin %int %int_3 Reduce [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformSMin %int %uint_3 Reduce [[val3]]
     values[x].val3 = WaveActiveMin(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-product.hlsl

@@ -20,12 +20,12 @@ void main(uint3 id: SV_DispatchThreadID) {
        int val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4float %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMul %v4float %int_3 Reduce [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMul %v4float %uint_3 Reduce [[val1]]
     values[x].val1 = WaveActiveProduct(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v2uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %v2uint %int_3 Reduce [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %v2uint %uint_3 Reduce [[val2]]
     values[x].val2 = WaveActiveProduct(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %int %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %int %int_3 Reduce [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %int %uint_3 Reduce [[val3]]
     values[x].val3 = WaveActiveProduct(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-active-sum.hlsl

@@ -20,12 +20,12 @@ void main(uint3 id: SV_DispatchThreadID) {
     float val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4int %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v4int %int_3 Reduce [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v4int %uint_3 Reduce [[val1]]
     values[x].val1 = WaveActiveSum(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v2uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v2uint %int_3 Reduce [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v2uint %uint_3 Reduce [[val2]]
     values[x].val2 = WaveActiveSum(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %float %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFAdd %float %int_3 Reduce [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFAdd %float %uint_3 Reduce [[val3]]
     values[x].val3 = WaveActiveSum(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-is-first-lane.hlsl

@@ -8,6 +8,6 @@ RWStructuredBuffer<uint> values;
 
 [numthreads(32, 1, 1)]
 void main(uint3 id: SV_DispatchThreadID) {
-// CHECK: {{%\d+}} = OpGroupNonUniformElect %bool %int_3
+// CHECK: {{%\d+}} = OpGroupNonUniformElect %bool %uint_3
     values[id.x] = WaveIsFirstLane();
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-prefix-count-bits.hlsl

@@ -15,7 +15,7 @@ void main(uint3 id: SV_DispatchThreadID) {
     uint x = id.x;
 
 // CHECK:         [[cmp:%\d+]] = OpIEqual %bool {{%\d+}} %uint_0
-// CHECK-NEXT: [[ballot:%\d+]] = OpGroupNonUniformBallot %v4uint %int_3 [[cmp]]
-// CHECK:             {{%\d+}} = OpGroupNonUniformBallotBitCount %uint %int_3 ExclusiveScan [[ballot]]
+// CHECK-NEXT: [[ballot:%\d+]] = OpGroupNonUniformBallot %v4uint %uint_3 [[cmp]]
+// CHECK:             {{%\d+}} = OpGroupNonUniformBallotBitCount %uint %uint_3 ExclusiveScan [[ballot]]
     values[x].val = WavePrefixCountBits(values[x].val == 0);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-prefix-product.hlsl

@@ -20,12 +20,12 @@ void main(uint3 id: SV_DispatchThreadID) {
        int val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4float %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMul %v4float %int_3 ExclusiveScan [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFMul %v4float %uint_3 ExclusiveScan [[val1]]
     values[x].val1 = WavePrefixProduct(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v2uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %v2uint %int_3 ExclusiveScan [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %v2uint %uint_3 ExclusiveScan [[val2]]
     values[x].val2 = WavePrefixProduct(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %int %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %int %int_3 ExclusiveScan [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIMul %int %uint_3 ExclusiveScan [[val3]]
     values[x].val3 = WavePrefixProduct(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-prefix-sum.hlsl

@@ -20,12 +20,12 @@ void main(uint3 id: SV_DispatchThreadID) {
     float val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4int %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v4int %int_3 ExclusiveScan [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v4int %uint_3 ExclusiveScan [[val1]]
     values[x].val1 = WavePrefixSum(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v2uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v2uint %int_3 ExclusiveScan [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformIAdd %v2uint %uint_3 ExclusiveScan [[val2]]
     values[x].val2 = WavePrefixSum(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %float %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFAdd %float %int_3 ExclusiveScan [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformFAdd %float %uint_3 ExclusiveScan [[val3]]
     values[x].val3 = WavePrefixSum(val3);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-read-lane-at.hlsl

@@ -21,12 +21,12 @@ void main(uint3 id: SV_DispatchThreadID) {
        int val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4float %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcast %v4float %int_3 [[val1]] %uint_15
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcast %v4float %uint_3 [[val1]] %uint_15
     values[x].val1 = WaveReadLaneAt(val1, 15);
 // CHECK:      [[val2:%\d+]] = OpLoad %v3uint %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcast %v3uint %int_3 [[val2]] %uint_42
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcast %v3uint %uint_3 [[val2]] %uint_42
     values[x].val2 = WaveReadLaneAt(val2, 42);
 // CHECK:      [[val3:%\d+]] = OpLoad %int %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcast %int %int_3 [[val3]] %uint_15
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcast %int %uint_3 [[val3]] %uint_15
     values[x].val3 = WaveReadLaneAt(val3, 15);
 }

tools/clang/test/CodeGenSPIRV/sm6.wave-read-lane-first.hlsl

@@ -21,12 +21,12 @@ void main(uint3 id: SV_DispatchThreadID) {
     float val3 = values[x].val3;
 
 // CHECK:      [[val1:%\d+]] = OpLoad %v4uint %val1
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcastFirst %v4uint %int_3 [[val1]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcastFirst %v4uint %uint_3 [[val1]]
     values[x].val1 = WaveReadLaneFirst(val1);
 // CHECK:      [[val2:%\d+]] = OpLoad %v2int %val2
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcastFirst %v2int %int_3 [[val2]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcastFirst %v2int %uint_3 [[val2]]
     values[x].val2 = WaveReadLaneFirst(val2);
 // CHECK:      [[val3:%\d+]] = OpLoad %float %val3
-// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcastFirst %float %int_3 [[val3]]
+// CHECK-NEXT:      {{%\d+}} = OpGroupNonUniformBroadcastFirst %float %uint_3 [[val3]]
     values[x].val3 = WaveReadLaneFirst(val3);
 }