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@@ -75,7 +75,7 @@ const hlsl::ConstantPacking *getPackOffset(const NamedDecl *decl) {
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} // anonymous namespace
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bool TypeTranslator::isRelaxedPrecisionType(QualType type,
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- const EmitSPIRVOptions &opts) {
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+ const SpirvCodeGenOptions &opts) {
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// Primitive types
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{
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QualType ty = {};
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@@ -489,7 +489,7 @@ uint32_t TypeTranslator::getElementSpirvBitwidth(QualType type) {
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llvm_unreachable("invalid type passed to getElementSpirvBitwidth");
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}
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-uint32_t TypeTranslator::translateType(QualType type, LayoutRule rule) {
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+uint32_t TypeTranslator::translateType(QualType type, SpirvLayoutRule rule) {
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const auto desugaredType = desugarType(type);
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if (desugaredType != type) {
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const auto id = translateType(desugaredType, rule);
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@@ -510,7 +510,7 @@ uint32_t TypeTranslator::translateType(QualType type, LayoutRule rule) {
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// According to the SPIR-V Spec: There is no physical size or bit
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// pattern defined for boolean type. Therefore an unsigned integer is
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// used to represent booleans when layout is required.
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- if (rule == LayoutRule::Void)
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+ if (rule == SpirvLayoutRule::Void)
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return theBuilder.getBoolType();
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else
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return theBuilder.getUint32Type();
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@@ -594,7 +594,7 @@ uint32_t TypeTranslator::translateType(QualType type, LayoutRule rule) {
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// If the matrix element type is not float, it is represented as an array
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// of vectors, and should therefore have the ArrayStride decoration.
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llvm::SmallVector<const Decoration *, 4> decorations;
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- if (!elemType->isFloatingType() && rule != LayoutRule::Void) {
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+ if (!elemType->isFloatingType() && rule != SpirvLayoutRule::Void) {
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uint32_t stride = 0;
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(void)getAlignmentAndSize(type, rule, &stride);
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decorations.push_back(
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@@ -635,7 +635,7 @@ uint32_t TypeTranslator::translateType(QualType type, LayoutRule rule) {
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}
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llvm::SmallVector<const Decoration *, 4> decorations;
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- if (rule != LayoutRule::Void) {
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+ if (rule != SpirvLayoutRule::Void) {
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decorations = getLayoutDecorations(collectDeclsInDeclContext(decl), rule);
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}
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@@ -649,7 +649,7 @@ uint32_t TypeTranslator::translateType(QualType type, LayoutRule rule) {
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const uint32_t elemTypeId = translateType(elemType, rule);
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llvm::SmallVector<const Decoration *, 4> decorations;
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- if (rule != LayoutRule::Void &&
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+ if (rule != SpirvLayoutRule::Void &&
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// We won't have stride information for structured/byte buffers since
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// they contain runtime arrays.
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!isAKindOfStructuredOrByteBuffer(elemType)) {
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@@ -1304,7 +1304,7 @@ bool TypeTranslator::shouldSkipInStructLayout(const Decl *decl) {
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}
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llvm::SmallVector<const Decoration *, 4> TypeTranslator::getLayoutDecorations(
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- const llvm::SmallVector<const Decl *, 4> &decls, LayoutRule rule) {
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+ const llvm::SmallVector<const Decl *, 4> &decls, SpirvLayoutRule rule) {
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const auto spirvContext = theBuilder.getSPIRVContext();
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llvm::SmallVector<const Decoration *, 4> decorations;
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uint32_t offset = 0, index = 0;
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@@ -1321,9 +1321,9 @@ llvm::SmallVector<const Decoration *, 4> TypeTranslator::getLayoutDecorations(
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// The next avaiable location after layouting the previos members
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const uint32_t nextLoc = offset;
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- if (rule == LayoutRule::RelaxedGLSLStd140 ||
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- rule == LayoutRule::RelaxedGLSLStd430 ||
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- rule == LayoutRule::FxcCTBuffer) {
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+ if (rule == SpirvLayoutRule::RelaxedGLSLStd140 ||
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+ rule == SpirvLayoutRule::RelaxedGLSLStd430 ||
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+ rule == SpirvLayoutRule::FxcCTBuffer) {
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alignUsingHLSLRelaxedLayout(fieldType, memberSize, memberAlignment,
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&offset);
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} else {
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@@ -1426,7 +1426,8 @@ TypeTranslator::collectDeclsInDeclContext(const DeclContext *declContext) {
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return decls;
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}
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-uint32_t TypeTranslator::translateResourceType(QualType type, LayoutRule rule) {
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+uint32_t TypeTranslator::translateResourceType(QualType type,
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+ SpirvLayoutRule rule) {
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// Resource types are either represented like C struct or C++ class in the
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// AST. Samplers are represented like C struct, so isStructureType() will
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// return true for it; textures are represented like C++ class, so
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@@ -1488,7 +1489,7 @@ uint32_t TypeTranslator::translateResourceType(QualType type, LayoutRule rule) {
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// The aliased-to variable should surely be in the Uniform storage class,
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// which has layout decorations.
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bool asAlias = false;
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- if (rule == LayoutRule::Void) {
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+ if (rule == SpirvLayoutRule::Void) {
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asAlias = true;
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rule = spirvOptions.sBufferLayoutRule;
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}
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@@ -1539,7 +1540,7 @@ uint32_t TypeTranslator::translateResourceType(QualType type, LayoutRule rule) {
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// ByteAddressBuffer types.
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if (name == "ByteAddressBuffer") {
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const auto bufferType = theBuilder.getByteAddressBufferType(/*isRW*/ false);
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- if (rule == LayoutRule::Void) {
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+ if (rule == SpirvLayoutRule::Void) {
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// All byte address buffers are in the Uniform storage class.
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return theBuilder.getPointerType(bufferType, spv::StorageClass::Uniform);
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} else {
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@@ -1549,7 +1550,7 @@ uint32_t TypeTranslator::translateResourceType(QualType type, LayoutRule rule) {
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// RWByteAddressBuffer types.
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if (name == "RWByteAddressBuffer") {
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const auto bufferType = theBuilder.getByteAddressBufferType(/*isRW*/ true);
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- if (rule == LayoutRule::Void) {
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+ if (rule == SpirvLayoutRule::Void) {
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// All byte address buffers are in the Uniform storage class.
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return theBuilder.getPointerType(bufferType, spv::StorageClass::Uniform);
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} else {
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@@ -1707,7 +1708,7 @@ void TypeTranslator::alignUsingHLSLRelaxedLayout(QualType fieldType,
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if (fieldIsVecType) {
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uint32_t scalarAlignment = 0;
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std::tie(scalarAlignment, std::ignore) =
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- getAlignmentAndSize(vecElemType, LayoutRule::Void, nullptr);
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+ getAlignmentAndSize(vecElemType, SpirvLayoutRule::Void, nullptr);
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if (scalarAlignment <= 4)
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fieldAlignment = scalarAlignment;
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}
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@@ -1724,7 +1725,7 @@ void TypeTranslator::alignUsingHLSLRelaxedLayout(QualType fieldType,
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}
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std::pair<uint32_t, uint32_t>
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-TypeTranslator::getAlignmentAndSize(QualType type, LayoutRule rule,
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+TypeTranslator::getAlignmentAndSize(QualType type, SpirvLayoutRule rule,
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uint32_t *stride) {
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// std140 layout rules:
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@@ -1853,7 +1854,8 @@ TypeTranslator::getAlignmentAndSize(QualType type, LayoutRule rule,
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uint32_t alignment = 0, size = 0;
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std::tie(alignment, size) = getAlignmentAndSize(elemType, rule, stride);
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// Use element alignment for fxc rules
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- if (rule != LayoutRule::FxcCTBuffer && rule != LayoutRule::FxcSBuffer)
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+ if (rule != SpirvLayoutRule::FxcCTBuffer &&
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+ rule != SpirvLayoutRule::FxcSBuffer)
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alignment = (elemCount == 3 ? 4 : elemCount) * size;
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return {alignment, elemCount * size};
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@@ -1875,16 +1877,16 @@ TypeTranslator::getAlignmentAndSize(QualType type, LayoutRule rule,
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const uint32_t vecStorageSize = isRowMajor ? colCount : rowCount;
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- if (rule == LayoutRule::FxcSBuffer) {
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+ if (rule == SpirvLayoutRule::FxcSBuffer) {
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*stride = vecStorageSize * size;
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// Use element alignment for fxc structured buffers
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return {alignment, rowCount * colCount * size};
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}
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alignment *= (vecStorageSize == 3 ? 4 : vecStorageSize);
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- if (rule == LayoutRule::GLSLStd140 ||
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- rule == LayoutRule::RelaxedGLSLStd140 ||
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- rule == LayoutRule::FxcCTBuffer) {
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+ if (rule == SpirvLayoutRule::GLSLStd140 ||
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+ rule == SpirvLayoutRule::RelaxedGLSLStd140 ||
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+ rule == SpirvLayoutRule::FxcCTBuffer) {
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alignment = roundToPow2(alignment, kStd140Vec4Alignment);
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}
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*stride = alignment;
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@@ -1909,9 +1911,9 @@ TypeTranslator::getAlignmentAndSize(QualType type, LayoutRule rule,
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std::tie(memberAlignment, memberSize) =
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getAlignmentAndSize(field->getType(), rule, stride);
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- if (rule == LayoutRule::RelaxedGLSLStd140 ||
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- rule == LayoutRule::RelaxedGLSLStd430 ||
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- rule == LayoutRule::FxcCTBuffer) {
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+ if (rule == SpirvLayoutRule::RelaxedGLSLStd140 ||
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+ rule == SpirvLayoutRule::RelaxedGLSLStd430 ||
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+ rule == SpirvLayoutRule::FxcCTBuffer) {
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alignUsingHLSLRelaxedLayout(field->getType(), memberSize,
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memberAlignment, &structSize);
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} else {
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@@ -1932,13 +1934,14 @@ TypeTranslator::getAlignmentAndSize(QualType type, LayoutRule rule,
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structSize += memberSize;
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}
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- if (rule == LayoutRule::GLSLStd140 ||
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- rule == LayoutRule::RelaxedGLSLStd140) {
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+ if (rule == SpirvLayoutRule::GLSLStd140 ||
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+ rule == SpirvLayoutRule::RelaxedGLSLStd140) {
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// ... and rounded up to the base alignment of a vec4.
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maxAlignment = roundToPow2(maxAlignment, kStd140Vec4Alignment);
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}
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- if (rule != LayoutRule::FxcCTBuffer && rule != LayoutRule::FxcSBuffer) {
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+ if (rule != SpirvLayoutRule::FxcCTBuffer &&
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+ rule != SpirvLayoutRule::FxcSBuffer) {
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// The base offset of the member following the sub-structure is rounded up
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// to the next multiple of the base alignment of the structure.
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structSize = roundToPow2(structSize, maxAlignment);
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@@ -1953,21 +1956,21 @@ TypeTranslator::getAlignmentAndSize(QualType type, LayoutRule rule,
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std::tie(alignment, size) =
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getAlignmentAndSize(arrayType->getElementType(), rule, stride);
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- if (rule == LayoutRule::FxcSBuffer) {
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+ if (rule == SpirvLayoutRule::FxcSBuffer) {
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*stride = size;
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// Use element alignment for fxc structured buffers
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return {alignment, size * elemCount};
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}
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- if (rule == LayoutRule::GLSLStd140 ||
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- rule == LayoutRule::RelaxedGLSLStd140 ||
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- rule == LayoutRule::FxcCTBuffer) {
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+ if (rule == SpirvLayoutRule::GLSLStd140 ||
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+ rule == SpirvLayoutRule::RelaxedGLSLStd140 ||
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+ rule == SpirvLayoutRule::FxcCTBuffer) {
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// The base alignment and array stride are set to match the base alignment
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// of a single array element, according to rules 1, 2, and 3, and rounded
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// up to the base alignment of a vec4.
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alignment = roundToPow2(alignment, kStd140Vec4Alignment);
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}
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- if (rule == LayoutRule::FxcCTBuffer) {
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+ if (rule == SpirvLayoutRule::FxcCTBuffer) {
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// In fxc cbuffer/tbuffer packing rules, arrays does not affect the data
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// packing after it. But we still need to make sure paddings are inserted
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// internally if necessary.
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