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@@ -3620,6 +3620,14 @@ uint32_t SPIRVEmitter::createImageSample(
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texelTypeId = theBuilder.getVecType(elemTypeId, 4);
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}
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+ // The Lod and Grad image operands requires explicit-lod instructions.
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+ // Otherwise we use implicit-lod instructions.
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+ const bool isExplicit = lod || (grad.first && grad.second);
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+
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+ // Implicit-lod instructions are only allowed in pixel shader.
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+ if (!shaderModel.IsPS() && !isExplicit)
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+ needsLegalization = true;
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+
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uint32_t retVal = theBuilder.createImageSample(
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texelTypeId, imageType, image, sampler, coordinate, compareVal, bias, lod,
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grad, constOffset, varOffset, constOffsets, sample, minLod,
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@@ -7227,6 +7235,21 @@ uint32_t SPIRVEmitter::processIntrinsicF32ToF16(const CallExpr *callExpr) {
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uint32_t SPIRVEmitter::processIntrinsicUsingSpirvInst(
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const CallExpr *callExpr, spv::Op opcode, bool actPerRowForMatrices) {
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+ // Certain opcodes are only allowed in pixel shader
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+ if (!shaderModel.IsPS())
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+ switch (opcode) {
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+ case spv::Op::OpDPdx:
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+ case spv::Op::OpDPdy:
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+ case spv::Op::OpDPdxFine:
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+ case spv::Op::OpDPdyFine:
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+ case spv::Op::OpDPdxCoarse:
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+ case spv::Op::OpDPdyCoarse:
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+ case spv::Op::OpFwidth:
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+ case spv::Op::OpFwidthFine:
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+ case spv::Op::OpFwidthCoarse:
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+ needsLegalization = true;
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+ }
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+
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const uint32_t returnType = typeTranslator.translateType(callExpr->getType());
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if (callExpr->getNumArgs() == 1u) {
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const Expr *arg = callExpr->getArg(0);
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