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@@ -637,6 +637,10 @@ public:
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return doCallExpr(funcCall);
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return doCallExpr(funcCall);
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}
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}
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+ if (const auto *condExpr = dyn_cast<ConditionalOperator>(expr)) {
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+ return doConditionalOperator(condExpr);
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+ }
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+
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emitError("Expr '%0' is not supported yet.") << expr->getStmtClassName();
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emitError("Expr '%0' is not supported yet.") << expr->getStmtClassName();
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// TODO: handle other expressions
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// TODO: handle other expressions
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return 0;
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return 0;
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@@ -683,7 +687,9 @@ public:
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case BO_Or:
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case BO_Or:
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case BO_Xor:
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case BO_Xor:
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case BO_Shl:
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case BO_Shl:
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- case BO_Shr: {
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+ case BO_Shr:
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+ case BO_LAnd:
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+ case BO_LOr: {
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const spv::Op spvOp = translateOp(opcode, elemType);
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const spv::Op spvOp = translateOp(opcode, elemType);
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return theBuilder.createBinaryOp(spvOp, typeId, lhs, rhs);
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return theBuilder.createBinaryOp(spvOp, typeId, lhs, rhs);
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}
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}
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@@ -1010,6 +1016,17 @@ public:
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return 0;
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return 0;
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}
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}
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+ uint32_t doConditionalOperator(const ConditionalOperator *expr) {
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+ // According to HLSL doc, all sides of the ?: expression are always
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+ // evaluated.
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+ const uint32_t type = typeTranslator.translateType(expr->getType());
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+ const uint32_t condition = doExpr(expr->getCond());
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+ const uint32_t trueBranch = doExpr(expr->getTrueExpr());
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+ const uint32_t falseBranch = doExpr(expr->getFalseExpr());
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+
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+ return theBuilder.createSelect(type, condition, trueBranch, falseBranch);
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+ }
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+
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/// Translates a floatN * float multiplication into SPIR-V instructions and
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/// Translates a floatN * float multiplication into SPIR-V instructions and
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/// returns the <result-id>. Returns 0 if the given binary operation is not
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/// returns the <result-id>. Returns 0 if the given binary operation is not
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/// floatN * float.
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/// floatN * float.
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@@ -1162,6 +1179,12 @@ case BO_##kind : { \
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BIN_OP_CASE_SINT_UINT(ShlAssign, ShiftLeftLogical, ShiftLeftLogical);
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BIN_OP_CASE_SINT_UINT(ShlAssign, ShiftLeftLogical, ShiftLeftLogical);
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BIN_OP_CASE_SINT_UINT(Shr, ShiftRightArithmetic, ShiftRightLogical);
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BIN_OP_CASE_SINT_UINT(Shr, ShiftRightArithmetic, ShiftRightLogical);
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BIN_OP_CASE_SINT_UINT(ShrAssign, ShiftRightArithmetic, ShiftRightLogical);
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BIN_OP_CASE_SINT_UINT(ShrAssign, ShiftRightArithmetic, ShiftRightLogical);
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+ // According to HLSL doc, all sides of the && and || expression are always
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+ // evaluated.
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+ case BO_LAnd:
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+ return spv::Op::OpLogicalAnd;
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+ case BO_LOr:
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+ return spv::Op::OpLogicalOr;
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default:
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default:
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break;
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break;
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}
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}
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