MIPS: Add MIPS32R2 compile-time/runtime CPU detection.

src/lib_jit.c

@@ -615,7 +615,21 @@ static uint32_t jit_cpudetect(lua_State *L)
 #elif LJ_TARGET_PPC || LJ_TARGET_PPCSPE
   /* Nothing to do. */
 #elif LJ_TARGET_MIPS
-  /* NYI */
+#if LJ_HASJIT
+  /* Compile-time MIPS CPU detection. */
+#if _MIPS_ARCH_MIPS32R2
+  flags |= JIT_F_MIPS32R2;
+#endif
+  /* Runtime MIPS CPU detection. */
+#if defined(__GNUC__)
+  if (!(flags & JIT_F_MIPS32R2)) {
+    int x;
+    /* On MIPS32R1 rotr is treated as srl. rotr r2,r2,1 -> srl r2,r2,1. */
+    __asm__("li $2, 1\n\t.long 0x00221042\n\tmove %0, $2" : "=r"(x) : : "$2");
+    if (x) flags |= JIT_F_MIPS32R2;  /* Either 0x80000000 (R2) or 0 (R1). */
+  }
+#endif
+#endif
 #else
 #error "Missing CPU detection for this architecture"
 #endif

src/lj_jit.h

@@ -34,6 +34,12 @@
 /* Names for the CPU-specific flags. Must match the order above. */
 #define JIT_F_CPU_FIRST		JIT_F_ARMV6
 #define JIT_F_CPUSTRING		"\5ARMv6\7ARMv6T2\5ARMv7"
+#elif LJ_TARGET_MIPS
+#define JIT_F_MIPS32R2		0x00000010
+
+/* Names for the CPU-specific flags. Must match the order above. */
+#define JIT_F_CPU_FIRST		JIT_F_MIPS32R2
+#define JIT_F_CPUSTRING		"\010MIPS32R2"
 #else
 #define JIT_F_CPU_FIRST		0
 #define JIT_F_CPUSTRING		""