ARM, PPC, MIPS: Improve XLOAD operand fusion and register hinting.

src/lj_asm.c

@@ -1749,8 +1749,12 @@ static void asm_setup_regsp(ASMState *as)
       }
       break;
 #endif
-    /* Do not propagate hints across type conversions. */
+    /* Do not propagate hints across type conversions or loads. */
     case IR_TOBIT:
+    case IR_XLOAD:
+#if !LJ_TARGET_ARM
+    case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
+#endif
       break;
     case IR_CONV:
       if (irt_isfp(ir->t) || (ir->op2 & IRCONV_SRCMASK) == IRT_NUM ||

src/lj_asm_arm.h

@@ -237,7 +237,7 @@ static void asm_fusexref(ASMState *as, ARMIns ai, Reg rd, IRRef ref,
 {
   IRIns *ir = IR(ref);
   Reg base;
-  if (ra_noreg(ir->r) && mayfuse(as, ref)) {
+  if (ra_noreg(ir->r) && canfuse(as, ir)) {
     int32_t lim = (!LJ_SOFTFP && (ai & 0x08000000)) ? 1024 :
 		   (ai & 0x04000000) ? 4096 : 256;
     if (ir->o == IR_ADD) {

src/lj_asm_mips.h

@@ -187,7 +187,7 @@ static void asm_fusexref(ASMState *as, MIPSIns mi, Reg rt, IRRef ref,
 {
   IRIns *ir = IR(ref);
   Reg base;
-  if (ra_noreg(ir->r) && mayfuse(as, ref)) {
+  if (ra_noreg(ir->r) && canfuse(as, ir)) {
     if (ir->o == IR_ADD) {
       int32_t ofs2;
       if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {

src/lj_asm_ppc.h

@@ -166,7 +166,7 @@ static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
 {
   IRIns *ir = IR(ref);
   Reg base;
-  if (ra_noreg(ir->r) && mayfuse(as, ref)) {
+  if (ra_noreg(ir->r) && canfuse(as, ir)) {
     if (ir->o == IR_ADD) {
       int32_t ofs2;
       if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
@@ -214,7 +214,7 @@ static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
 {
   IRIns *ira = IR(ref);
   Reg right, left;
-  if (mayfuse(as, ref) && ira->o == IR_ADD && ra_noreg(ira->r)) {
+  if (canfuse(as, ira) && ira->o == IR_ADD && ra_noreg(ira->r)) {
     left = ra_alloc2(as, ira, allow);
     right = (left >> 8); left &= 255;
   } else {