Browse Source

Merge pull request #2944 from Kelimion/microarch-help

Add -microarch:?
Jeroen van Rijn 1 year ago
parent
commit
8a56bb3b5f
5 changed files with 113 additions and 18 deletions
  1. 1 0
      build.bat
  2. 17 3
      src/build_settings.cpp
  3. 27 15
      src/llvm_backend.cpp
  4. 44 0
      src/main.cpp
  5. 24 0
      src/string.cpp

+ 1 - 0
build.bat

@@ -110,6 +110,7 @@ if %errorlevel% neq 0 goto end_of_build
 call build_vendor.bat
 if %errorlevel% neq 0 goto end_of_build
 
+rem If the demo doesn't run for you and your CPU is more than a decade old, try -microarch:native
 if %release_mode% EQU 0 odin run examples/demo
 
 del *.obj > NUL 2> NUL

+ 17 - 3
src/build_settings.cpp

@@ -82,6 +82,23 @@ gb_global String target_arch_names[TargetArch_COUNT] = {
 	str_lit("wasm64p32"),
 };
 
+gb_global String target_microarch_list[TargetArch_COUNT] = {
+	// TargetArch_Invalid,
+	str_lit("Invalid!"),
+	// TargetArch_amd64,
+	str_lit("alderlake,amdfam10,athlon-fx,athlon64,athlon64-sse3,atom_sse4_2,atom_sse4_2_movbe,barcelona,bdver1,bdver2,bdver3,bdver4,broadwell,btver1,btver2,cannonlake,cascadelake,cooperlake,core-avx-i,core-avx2,core2,core_2_duo_sse4_1,core_2_duo_ssse3,core_2nd_gen_avx,core_3rd_gen_avx,core_4th_gen_avx,core_4th_gen_avx_tsx,core_5th_gen_avx,core_5th_gen_avx_tsx,core_aes_pclmulqdq,core_i7_sse4_2,corei7,corei7-avx,generic,goldmont,goldmont-plus,goldmont_plus,grandridge,graniterapids,graniterapids-d,graniterapids_d,haswell,icelake-client,icelake-server,icelake_client,icelake_server,ivybridge,k8,k8-sse3,knl,knm,meteorlake,mic_avx512,native,nehalem,nocona,opteron,opteron-sse3,penryn,raptorlake,rocketlake,sandybridge,sapphirerapids,sierraforest,silvermont,skx,skylake,skylake-avx512,skylake_avx512,slm,tigerlake,tremont,westmere,x86-64,x86-64-v2,x86-64-v3,x86-64-v4,znver1,znver2,znver3,znver4"),
+	// TargetArch_i386,
+	str_lit("athlon,athlon-4,athlon-mp,athlon-tbird,athlon-xp,atom,bonnell,c3,c3-2,generic,geode,i386,i486,i586,i686,k6,k6-2,k6-3,lakemont,native,pentium,pentium-m,pentium-mmx,pentium2,pentium3,pentium3m,pentium4,pentium4m,pentium_4,pentium_4_sse3,pentium_ii,pentium_iii,pentium_iii_no_xmm_regs,pentium_m,pentium_mmx,pentium_pro,pentiumpro,prescott,winchip-c6,winchip2,yonah"),
+	// TargetArch_arm32,
+	str_lit("arm1020e,arm1020t,arm1022e,arm10e,arm10tdmi,arm1136j-s,arm1136jf-s,arm1156t2-s,arm1156t2f-s,arm1176jz-s,arm1176jzf-s,arm710t,arm720t,arm7tdmi,arm7tdmi-s,arm8,arm810,arm9,arm920,arm920t,arm922t,arm926ej-s,arm940t,arm946e-s,arm966e-s,arm968e-s,arm9e,arm9tdmi,cortex-a12,cortex-a15,cortex-a17,cortex-a32,cortex-a35,cortex-a5,cortex-a53,cortex-a55,cortex-a57,cortex-a7,cortex-a710,cortex-a72,cortex-a73,cortex-a75,cortex-a76,cortex-a76ae,cortex-a77,cortex-a78,cortex-a78c,cortex-a8,cortex-a9,cortex-m0,cortex-m0plus,cortex-m1,cortex-m23,cortex-m3,cortex-m33,cortex-m35p,cortex-m4,cortex-m55,cortex-m7,cortex-m85,cortex-r4,cortex-r4f,cortex-r5,cortex-r52,cortex-r7,cortex-r8,cortex-x1,cortex-x1c,cyclone,ep9312,exynos-m3,exynos-m4,exynos-m5,generic,iwmmxt,krait,kryo,mpcore,mpcorenovfp,native,neoverse-n1,neoverse-n2,neoverse-v1,sc000,sc300,strongarm,strongarm110,strongarm1100,strongarm1110,swift,xscale"),
+	// TargetArch_arm64,
+	str_lit("a64fx,ampere1,ampere1a,apple-a10,apple-a11,apple-a12,apple-a13,apple-a14,apple-a15,apple-a16,apple-a7,apple-a8,apple-a9,apple-latest,apple-m1,apple-m2,apple-s4,apple-s5,carmel,cortex-a34,cortex-a35,cortex-a510,cortex-a53,cortex-a55,cortex-a57,cortex-a65,cortex-a65ae,cortex-a710,cortex-a715,cortex-a72,cortex-a73,cortex-a75,cortex-a76,cortex-a76ae,cortex-a77,cortex-a78,cortex-a78c,cortex-r82,cortex-x1,cortex-x1c,cortex-x2,cortex-x3,cyclone,exynos-m3,exynos-m4,exynos-m5,falkor,generic,kryo,native,neoverse-512tvb,neoverse-e1,neoverse-n1,neoverse-n2,neoverse-v1,neoverse-v2,saphira,thunderx,thunderx2t99,thunderx3t110,thunderxt81,thunderxt83,thunderxt88,tsv110"),
+	// TargetArch_wasm32,
+	str_lit("generic"),
+	// TargetArch_wasm64p32,
+	str_lit("generic"),
+};
+
 gb_global String target_endian_names[TargetEndian_COUNT] = {
 	str_lit("little"),
 	str_lit("big"),
@@ -109,8 +126,6 @@ gb_global TargetEndianKind target_endians[TargetArch_COUNT] = {
 
 gb_global String const ODIN_VERSION = str_lit(ODIN_VERSION_RAW);
 
-
-
 struct TargetMetrics {
 	TargetOsKind   os;
 	TargetArchKind arch;
@@ -623,7 +638,6 @@ gb_internal TargetArchKind get_target_arch_from_string(String str) {
 	return TargetArch_Invalid;
 }
 
-
 gb_internal bool is_excluded_target_filename(String name) {
 	String original_name = name;
 	name = remove_extension_from_path(name);

+ 27 - 15
src/llvm_backend.cpp

@@ -21,6 +21,25 @@
 #include "llvm_backend_stmt.cpp"
 #include "llvm_backend_proc.cpp"
 
+char *get_default_microarchitecture() {
+	char * default_march = "generic";
+	if (build_context.metrics.arch == TargetArch_amd64) {
+		// NOTE(bill): x86-64-v2 is more than enough for everyone
+		//
+		// x86-64: CMOV, CMPXCHG8B, FPU, FXSR, MMX, FXSR, SCE, SSE, SSE2
+		// x86-64-v2: (close to Nehalem) CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3
+		// x86-64-v3: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE
+		// x86-64-v4: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL
+		if (ODIN_LLVM_MINIMUM_VERSION_12) {
+			if (build_context.metrics.os == TargetOs_freestanding) {
+				default_march = "x86-64";
+			} else {
+				default_march = "x86-64-v2";
+			}
+		}
+	}
+	return default_march;
+}
 
 gb_internal void lb_add_foreign_library_path(lbModule *m, Entity *e) {
 	if (e == nullptr) {
@@ -2491,7 +2510,7 @@ gb_internal bool lb_generate_code(lbGenerator *gen) {
 	}
 
 	char const *host_cpu_name = LLVMGetHostCPUName();
-	char const *llvm_cpu = "generic";
+	char const *llvm_cpu = get_default_microarchitecture();
 	char const *llvm_features = "";
 	if (build_context.microarch.len != 0) {
 		if (build_context.microarch == "native") {
@@ -2502,22 +2521,15 @@ gb_internal bool lb_generate_code(lbGenerator *gen) {
 		if (gb_strcmp(llvm_cpu, host_cpu_name) == 0) {
 			llvm_features = LLVMGetHostCPUFeatures();
 		}
-	} else if (build_context.metrics.arch == TargetArch_amd64) {
-		// NOTE(bill): x86-64-v2 is more than enough for everyone
-		//
-		// x86-64: CMOV, CMPXCHG8B, FPU, FXSR, MMX, FXSR, SCE, SSE, SSE2
-		// x86-64-v2: (close to Nehalem) CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3
-		// x86-64-v3: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE
-		// x86-64-v4: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL
-		if (ODIN_LLVM_MINIMUM_VERSION_12) {
-			if (build_context.metrics.os == TargetOs_freestanding) {
-				llvm_cpu = "x86-64";
-			} else {
-				llvm_cpu = "x86-64-v2";
-			}
-		}
 	}
 
+	// NOTE(Jeroen): Uncomment to get the list of supported microarchitectures.
+	/*
+	if (build_context.microarch == "?") {
+		string_set_add(&build_context.target_features_set, str_lit("+cpuhelp"));
+	}
+	*/
+
 	if (build_context.target_features_set.entries.count != 0) {
 		llvm_features = target_features_set_to_cstring(permanent_allocator(), false);
 	}

+ 44 - 0
src/main.cpp

@@ -1876,6 +1876,7 @@ gb_internal void print_show_help(String const arg0, String const &command) {
 		print_usage_line(2, "Examples:");
 		print_usage_line(3, "-microarch:sandybridge");
 		print_usage_line(3, "-microarch:native");
+		print_usage_line(3, "-microarch:? for a list");
 		print_usage_line(0, "");
 
 		print_usage_line(1, "-reloc-mode:<string>");
@@ -2518,6 +2519,49 @@ int main(int arg_count, char const **arg_ptr) {
 	// 	return 1;
 	// }
 
+	// Check chosen microarchitecture. If not found or ?, print list.
+	bool print_microarch_list = true;
+	if (build_context.microarch.len == 0) {
+		// Autodetect, no need to print list.
+		print_microarch_list = false;
+	} else {
+		String march_list = target_microarch_list[build_context.metrics.arch];
+		String_Iterator it = {march_list, 0};
+		for (;;) {
+			String str = string_split_iterator(&it, ',');
+			if (str == "") break;
+			if (str == build_context.microarch) {
+				// Found matching microarch
+				print_microarch_list = false;
+				break;
+			}
+		}
+	}
+
+	if (print_microarch_list) {
+		if (build_context.microarch != "?") {
+			gb_printf("Unknown microarchitecture '%.*s'.\n", LIT(build_context.microarch));
+		}
+		gb_printf("Possible -microarch values for target %.*s are:\n", LIT(target_arch_names[build_context.metrics.arch]));
+		gb_printf("\n");
+
+		String march_list  = target_microarch_list[build_context.metrics.arch];
+		String_Iterator it = {march_list, 0};
+
+		String default_march = make_string_c(get_default_microarchitecture());
+
+		for (;;) {
+			String str = string_split_iterator(&it, ',');
+			if (str == "") break;
+			if (str == default_march) {
+				gb_printf("\t%.*s (default)\n", LIT(str));
+			} else {
+				gb_printf("\t%.*s\n", LIT(str));
+			}
+		}
+		return 0;
+	}
+
 	// Set and check build paths...
 	if (!init_build_paths(init_filename)) {
 		return 1;

+ 24 - 0
src/string.cpp

@@ -10,6 +10,10 @@ struct String {
 		return text[i];
 	}
 };
+struct String_Iterator {
+	String const &str;
+	isize  pos;
+};
 // NOTE(bill): used for printf style arguments
 #define LIT(x) ((int)(x).len), (x).text
 #if defined(GB_COMPILER_MSVC) && _MSC_VER < 1700
@@ -201,6 +205,26 @@ gb_internal gb_inline String string_trim_starts_with(String const &s, String con
 }
 
 
+gb_internal String string_split_iterator(String_Iterator *it, const char sep) {
+	isize start = it->pos;
+	isize end   = it->str.len;
+
+	if (start == end) {
+		return str_lit("");
+	}
+
+	isize i = start;
+	for (; i < it->str.len; i++) {
+		if (it->str[i] == sep) {
+			String res = substring(it->str, start, i);
+			it->pos += res.len + 1;
+			return res;
+		}
+	}
+	it->pos = end;
+	return substring(it->str, start, end);
+}
+
 gb_internal gb_inline isize string_extension_position(String const &str) {
 	isize dot_pos = -1;
 	isize i = str.len;