LLVM Binaries

.gitignore

@@ -252,5 +252,6 @@ paket-files/
 
 # Project Specific
 bin/
-misc/
 *.sln
+!misc/llvm-bim/lli.exe
+!misc/llvm-bim/opt.exe

misc/debug.bat

@@ -0,0 +1,3 @@
+@echo off
+
+call devenv odin.sln

misc/llvm-bin/CODE_OWNERS.TXT

@@ -0,0 +1,200 @@
+This file is a list of the people responsible for ensuring that patches for a
+particular part of LLVM are reviewed, either by themself or by someone else.
+They are also the gatekeepers for their part of LLVM, with the final word on
+what goes in or not.
+
+The list is sorted by surname and formatted to allow easy grepping and
+beautification by scripts.  The fields are: name (N), email (E), web-address
+(W), PGP key ID and fingerprint (P), description (D), and snail-mail address
+(S). Each entry should contain at least the (N), (E) and (D) fields.
+
+N: Joe Abbey
+E: [email protected]
+D: LLVM Bitcode (lib/Bitcode/* include/llvm/Bitcode/*)
+
+N: Owen Anderson
+E: [email protected]
+D: SelectionDAG (lib/CodeGen/SelectionDAG/*)
+
+N: Rafael Avila de Espindola
+E: [email protected]
+D: Gold plugin (tools/gold/*)
+
+N: Justin Bogner
+E: [email protected]
+D: InstrProfiling and related parts of ProfileData
+
+N: Chandler Carruth
+E: [email protected]
+E: [email protected]
+D: Config, ADT, Support, inlining & related passes, SROA/mem2reg & related passes, CMake, library layering
+
+N: Evan Cheng
+E: [email protected]
+D: parts of code generator not covered by someone else
+
+N: Eric Christopher
+E: [email protected]
+D: Debug Information, autotools/configure/make build, inline assembly
+
+N: Greg Clayton
+E: [email protected]
+D: LLDB
+
+N: Marshall Clow
+E: [email protected]
+D: libc++
+
+N: Peter Collingbourne
+E: [email protected]
+D: llgo
+
+N: Quentin Colombet
+E: [email protected]
+D: Register allocators
+
+N: Duncan P. N. Exon Smith
+E: [email protected]
+D: Branch weights and BlockFrequencyInfo
+
+N: Hal Finkel
+E: [email protected]
+D: BBVectorize, the loop reroller, alias analysis and the PowerPC target
+
+N: Dan Gohman
+E: [email protected]
+D: WebAssembly Backend (lib/Target/WebAssembly/*)
+
+N: Renato Golin
+E: [email protected]
+D: ARM Linux support
+
+N: Venkatraman Govindaraju
+E: [email protected]
+D: Sparc Backend (lib/Target/Sparc/*)
+
+N: Tobias Grosser
+E: [email protected]
+D: Polly
+
+N: James Grosbach
+E: [email protected]
+D: MC layer
+
+N: Justin Holewinski
+E: [email protected]
+D: NVPTX Target (lib/Target/NVPTX/*)
+
+N: Lang Hames
+E: [email protected]
+D: MCJIT, RuntimeDyld and JIT event listeners
+
+N: Galina Kistanova
+E: [email protected]
+D: LLVM Buildbot
+
+N: Anton Korobeynikov
+E: [email protected]
+D: Exception handling, Windows codegen, ARM EABI
+
+N: Benjamin Kramer
+E: [email protected]
+D: DWARF Parser
+
+N: Sergei Larin
+E: [email protected]
+D: VLIW Instruction Scheduling, Packetization
+
+N: Chris Lattner
+E: [email protected]
+W: http://nondot.org/~sabre/
+D: Everything not covered by someone else
+
+N: David Majnemer
+E: [email protected]
+D: IR Constant Folder, InstCombine
+
+N: Dylan McKay
+E: [email protected]
+D: AVR Backend
+
+N: Tim Northover
+E: [email protected]
+D: AArch64 backend, misc ARM backend
+
+N: Diego Novillo
+E: [email protected]
+D: SampleProfile and related parts of ProfileData
+
+N: Jakob Olesen
+E: [email protected]
+D: TableGen
+
+N: Richard Osborne
+E: [email protected]
+D: XCore Backend
+
+N: Krzysztof Parzyszek
+E: [email protected]
+D: Hexagon Backend
+
+N: Paul Robinson
+E: [email protected]
+D: Sony PlayStation®4 support
+
+N: Chad Rosier
+E: [email protected]
+D: Fast-Isel
+
+N: Nadav Rotem
+E: [email protected]
+D: X86 Backend, Loop Vectorizer
+
+N: Daniel Sanders
+E: [email protected]
+D: MIPS Backend (lib/Target/Mips/*)
+
+N: Duncan Sands
+E: [email protected]
+D: DragonEgg
+
+N: Kostya Serebryany
+E: [email protected]
+D: AddressSanitizer, ThreadSanitizer (LLVM parts)
+
+N: Michael Spencer
+E: [email protected]
+D: Windows parts of Support, Object, ar, nm, objdump, ranlib, size
+
+N: Alexei Starovoitov
+E: [email protected]
+D: BPF backend
+
+N: Tom Stellard
+E: [email protected]
+E: [email protected]
+D: Release manager for the 3.5 and 3.6 branches, R600 Backend, libclc
+
+N: Evgeniy Stepanov
+E: [email protected]
+D: MemorySanitizer (LLVM part)
+
+N: Andrew Trick
+E: [email protected]
+D: IndVar Simplify, Loop Strength Reduction, Instruction Scheduling
+
+N: Ulrich Weigand
+E: [email protected]
+D: SystemZ Backend
+
+N: Bill Wendling
+E: [email protected]
+D: libLTO, IR Linker
+
+N: Peter Zotov
+E: [email protected]
+D: OCaml bindings
+
+N: Andrey Churbanov
+E: [email protected]
+D: OpenMP runtime library

misc/llvm-bin/CREDITS.TXT

@@ -0,0 +1,467 @@
+This file is a partial list of people who have contributed to the LLVM
+project.  If you have contributed a patch or made some other contribution to
+LLVM, please submit a patch to this file to add yourself, and it will be
+done!
+
+The list is sorted by surname and formatted to allow easy grepping and
+beautification by scripts.  The fields are: name (N), email (E), web-address
+(W), PGP key ID and fingerprint (P), description (D), snail-mail address
+(S), and (I) IRC handle.
+
+
+N: Vikram Adve
+E: [email protected]
+W: http://www.cs.uiuc.edu/~vadve/
+D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
+
+N: Owen Anderson
+E: [email protected]
+D: LCSSA pass and related LoopUnswitch work
+D: GVNPRE pass, DataLayout refactoring, random improvements
+
+N: Henrik Bach
+D: MingW Win32 API portability layer
+
+N: Aaron Ballman
+E: [email protected]
+D: __declspec attributes, Windows support, general bug fixing
+
+N: Nate Begeman
+E: [email protected]
+D: PowerPC backend developer
+D: Target-independent code generator and analysis improvements
+
+N: Daniel Berlin
+E: [email protected]
+D: ET-Forest implementation.
+D: Sparse bitmap
+
+N: David Blaikie
+E: [email protected]
+D: General bug fixing/fit & finish, mostly in Clang
+
+N: Neil Booth
+E: [email protected]
+D: APFloat implementation.
+
+N: Misha Brukman
+E: [email protected]
+W: http://misha.brukman.net
+D: Portions of X86 and Sparc JIT compilers, PowerPC backend
+D: Incremental bitcode loader
+
+N: Cameron Buschardt
+E: [email protected]
+D: The `mem2reg' pass - promotes values stored in memory to registers
+
+N: Brendon Cahoon
+E: [email protected]
+D: Loop unrolling with run-time trip counts.
+
+N: Chandler Carruth
+E: [email protected]
+E: [email protected]
+D: Hashing algorithms and interfaces
+D: Inline cost analysis
+D: Machine block placement pass
+D: SROA
+
+N: Casey Carter
+E: [email protected]
+D: Fixes to the Reassociation pass, various improvement patches
+
+N: Evan Cheng
+E: [email protected]
+D: ARM and X86 backends
+D: Instruction scheduler improvements
+D: Register allocator improvements
+D: Loop optimizer improvements
+D: Target-independent code generator improvements
+
+N: Dan Villiom Podlaski Christiansen
+E: [email protected]
+E: [email protected]
+W: http://villiom.dk
+D: LLVM Makefile improvements
+D: Clang diagnostic & driver tweaks
+S: Aarhus, Denmark
+
+N: Jeff Cohen
+E: [email protected]
+W: http://jolt-lang.org
+D: Native Win32 API portability layer
+
+N: John T. Criswell
+E: [email protected]
+D: Original Autoconf support, documentation improvements, bug fixes
+
+N: Anshuman Dasgupta
+E: [email protected]
+D: Deterministic finite automaton based infrastructure for VLIW packetization
+
+N: Stefanus Du Toit
+E: [email protected]
+D: Bug fixes and minor improvements
+
+N: Rafael Avila de Espindola
+E: [email protected]
+D: The ARM backend
+
+N: Dave Estes
+E: [email protected]
+D: AArch64 machine description for Cortex-A53
+
+N: Alkis Evlogimenos
+E: [email protected]
+D: Linear scan register allocator, many codegen improvements, Java frontend
+
+N: Hal Finkel
+E: [email protected]
+D: Basic-block autovectorization, PowerPC backend improvements
+
+N: Eric Fiselier
+E: [email protected]
+D: LIT patches and documentation.
+
+N: Ryan Flynn
+E: [email protected]
+D: Miscellaneous bug fixes
+
+N: Brian Gaeke
+E: [email protected]
+W: http://www.students.uiuc.edu/~gaeke/
+D: Portions of X86 static and JIT compilers; initial SparcV8 backend
+D: Dynamic trace optimizer
+D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
+
+N: Nicolas Geoffray
+E: [email protected]
+W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
+D: PPC backend fixes for Linux
+
+N: Louis Gerbarg
+E: [email protected]
+D: Portions of the PowerPC backend
+
+N: Saem Ghani
+E: [email protected]
+D: Callgraph class cleanups
+
+N: Mikhail Glushenkov
+E: [email protected]
+D: Author of llvmc2
+
+N: Dan Gohman
+E: [email protected]
+D: Miscellaneous bug fixes
+D: WebAssembly Backend
+
+N: David Goodwin
+E: [email protected]
+D: Thumb-2 code generator
+
+N: David Greene
+E: [email protected]
+D: Miscellaneous bug fixes
+D: Register allocation refactoring
+
+N: Gabor Greif
+E: [email protected]
+D: Improvements for space efficiency
+
+N: James Grosbach
+E: [email protected]
+I: grosbach
+D: SjLj exception handling support
+D: General fixes and improvements for the ARM back-end
+D: MCJIT
+D: ARM integrated assembler and assembly parser
+D: Led effort for the backend formerly known as ARM64
+
+N: Lang Hames
+E: [email protected]
+D: PBQP-based register allocator
+
+N: Gordon Henriksen
+E: [email protected]
+D: Pluggable GC support
+D: C interface
+D: Ocaml bindings
+
+N: Raul Fernandes Herbster
+E: [email protected]
+D: JIT support for ARM
+
+N: Paolo Invernizzi
+E: [email protected]
+D: Visual C++ compatibility fixes
+
+N: Patrick Jenkins
+E: [email protected]
+D: Nightly Tester
+
+N: Dale Johannesen
+E: [email protected]
+D: ARM constant islands improvements
+D: Tail merging improvements
+D: Rewrite X87 back end
+D: Use APFloat for floating point constants widely throughout compiler
+D: Implement X87 long double
+
+N: Brad Jones
+E: [email protected]
+D: Support for packed types
+
+N: Rod Kay
+E: [email protected]
+D: Author of LLVM Ada bindings
+
+N: Eric Kidd
+W: http://randomhacks.net/
+D: llvm-config script
+
+N: Anton Korobeynikov
+E: [email protected]
+D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
+D: x86/linux PIC codegen, aliases, regparm/visibility attributes
+D: Switch lowering refactoring
+
+N: Sumant Kowshik
+E: [email protected]
+D: Author of the original C backend
+
+N: Benjamin Kramer
+E: [email protected]
+D: Miscellaneous bug fixes
+
+N: Sundeep Kushwaha
+E: [email protected]
+D: Implemented DFA-based target independent VLIW packetizer
+
+N: Christopher Lamb
+E: [email protected]
+D: aligned load/store support, parts of noalias and restrict support
+D: vreg subreg infrastructure, X86 codegen improvements based on subregs
+D: address spaces
+
+N: Jim Laskey
+E: [email protected]
+D: Improvements to the PPC backend, instruction scheduling
+D: Debug and Dwarf implementation
+D: Auto upgrade mangler
+D: llvm-gcc4 svn wrangler
+
+N: Chris Lattner
+E: [email protected]
+W: http://nondot.org/~sabre/
+D: Primary architect of LLVM
+
+N: Tanya Lattner (Tanya Brethour)
+E: [email protected]
+W: http://nondot.org/~tonic/
+D: The initial llvm-ar tool, converted regression testsuite to dejagnu
+D: Modulo scheduling in the SparcV9 backend
+D: Release manager (1.7+)
+
+N: Sylvestre Ledru
+E: [email protected]
+W: http://sylvestre.ledru.info/
+W: http://llvm.org/apt/
+D: Debian and Ubuntu packaging
+D: Continuous integration with jenkins
+
+N: Andrew Lenharth
+E: [email protected]
+W: http://www.lenharth.org/~andrewl/
+D: Alpha backend
+D: Sampling based profiling
+
+N: Nick Lewycky
+E: [email protected]
+D: PredicateSimplifier pass
+
+N: Tony Linthicum, et. al.
+E: [email protected]
+D: Backend for Qualcomm's Hexagon VLIW processor.
+
+N: Bruno Cardoso Lopes
+E: [email protected]
+I: bruno
+W: http://brunocardoso.cc
+D: Mips backend
+D: Random ARM integrated assembler and assembly parser improvements
+D: General X86 AVX1 support
+
+N: Duraid Madina
+E: [email protected]
+W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
+D: IA64 backend, BigBlock register allocator
+
+N: John McCall
+E: [email protected]
+D: Clang semantic analysis and IR generation
+
+N: Michael McCracken
+E: [email protected]
+D: Line number support for llvmgcc
+
+N: Vladimir Merzliakov
+E: [email protected]
+D: Test suite fixes for FreeBSD
+
+N: Scott Michel
+E: [email protected]
+D: Added STI Cell SPU backend.
+
+N: Kai Nacke
+E: [email protected]
+D: Support for implicit TLS model used with MS VC runtime
+D: Dumping of Win64 EH structures
+
+N: Takumi Nakamura
+E: [email protected]
+E: [email protected]
+D: Cygwin and MinGW support.
+D: Win32 tweaks.
+S: Yokohama, Japan
+
+N: Edward O'Callaghan
+E: [email protected]
+W: http://www.auroraux.org
+D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
+D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
+D: and error clean ups.
+
+N: Morten Ofstad
+E: [email protected]
+D: Visual C++ compatibility fixes
+
+N: Jakob Stoklund Olesen
+E: [email protected]
+D: Machine code verifier
+D: Blackfin backend
+D: Fast register allocator
+D: Greedy register allocator
+
+N: Richard Osborne
+E: [email protected]
+D: XCore backend
+
+N: Devang Patel
+E: [email protected]
+D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
+D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
+D: Optimizer improvements, Loop Index Split
+
+N: Ana Pazos
+E: [email protected]
+D: Fixes and improvements to the AArch64 backend
+
+N: Wesley Peck
+E: [email protected]
+W: http://wesleypeck.com/
+D: MicroBlaze backend
+
+N: Francois Pichet
+E: [email protected]
+D: MSVC support
+
+N: Vladimir Prus
+W: http://vladimir_prus.blogspot.com
+E: [email protected]
+D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
+
+N: Kalle Raiskila
+E: [email protected]
+D: Some bugfixes to CellSPU
+
+N: Xerxes Ranby
+E: [email protected]
+D: Cmake dependency chain and various bug fixes
+
+N: Alex Rosenberg
+E: [email protected]
+I: arosenberg
+D: ARM calling conventions rewrite, hard float support
+
+N: Chad Rosier
+E: [email protected]
+I: mcrosier
+D: AArch64 fast instruction selection pass
+D: Fixes and improvements to the ARM fast-isel pass
+D: Fixes and improvements to the AArch64 backend
+
+N: Nadav Rotem
+E: [email protected]
+D: X86 code generation improvements, Loop Vectorizer.
+
+N: Roman Samoilov
+E: [email protected]
+D: MSIL backend
+
+N: Duncan Sands
+E: [email protected]
+I: baldrick
+D: Ada support in llvm-gcc
+D: Dragonegg plugin
+D: Exception handling improvements
+D: Type legalizer rewrite
+
+N: Ruchira Sasanka
+E: [email protected]
+D: Graph coloring register allocator for the Sparc64 backend
+
+N: Arnold Schwaighofer
+E: [email protected]
+D: Tail call optimization for the x86 backend
+
+N: Shantonu Sen
+E: [email protected]
+D: Miscellaneous bug fixes
+
+N: Anand Shukla
+E: [email protected]
+D: The `paths' pass
+
+N: Michael J. Spencer
+E: [email protected]
+D: Shepherding Windows COFF support into MC.
+D: Lots of Windows stuff.
+
+N: Reid Spencer
+E: [email protected]
+W: http://reidspencer.com/
+D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
+
+N: Alp Toker
+E: [email protected]
+W: http://atoker.com/
+D: C++ frontend next generation standards implementation
+
+N: Craig Topper
+E: [email protected]
+D: X86 codegen and disassembler improvements. AVX2 support.
+
+N: Edwin Torok
+E: [email protected]
+D: Miscellaneous bug fixes
+
+N: Adam Treat
+E: [email protected]
+D: C++ bugs filed, and C++ front-end bug fixes.
+
+N: Lauro Ramos Venancio
+E: [email protected]
+D: ARM backend improvements
+D: Thread Local Storage implementation
+
+N: Bill Wendling
+I: wendling
+E: [email protected]
+D: Release manager, IR Linker, LTO
+D: Bunches of stuff
+
+N: Bob Wilson
+E: [email protected]
+D: Advanced SIMD (NEON) support in the ARM backend.
+

misc/llvm-bin/LICENSE.TXT

@@ -0,0 +1,70 @@
+==============================================================================
+LLVM Release License
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2015 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+==============================================================================
+Copyrights and Licenses for Third Party Software Distributed with LLVM:
+==============================================================================
+The LLVM software contains code written by third parties.  Such software will
+have its own individual LICENSE.TXT file in the directory in which it appears.
+This file will describe the copyrights, license, and restrictions which apply
+to that code.
+
+The disclaimer of warranty in the University of Illinois Open Source License
+applies to all code in the LLVM Distribution, and nothing in any of the
+other licenses gives permission to use the names of the LLVM Team or the
+University of Illinois to endorse or promote products derived from this
+Software.
+
+The following pieces of software have additional or alternate copyrights,
+licenses, and/or restrictions:
+
+Program             Directory
+-------             ---------
+Autoconf            llvm/autoconf
+                    llvm/projects/ModuleMaker/autoconf
+Google Test         llvm/utils/unittest/googletest
+OpenBSD regex       llvm/lib/Support/{reg*, COPYRIGHT.regex}
+pyyaml tests        llvm/test/YAMLParser/{*.data, LICENSE.TXT}
+ARM contributions   llvm/lib/Target/ARM/LICENSE.TXT
+md5 contributions   llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h

misc/shell.bat

@@ -0,0 +1,9 @@
+@echo off
+
+call "C:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\vcvarsall.bat" x64 1> NUL
+rem call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" x64 1> NUL
+set _NO_DEBUG_HEAP=1
+
+set path=w:\Odin\misc;%path%
+
+cls