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@@ -4093,7 +4093,7 @@
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// Used when you know that your algorithm is only going to work with float types and you need the extra performance.
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// Some processors have AVX but not AVX2, meaning that it has 256-bit SIMD for floats, but only 128-bit SIMD for integers.
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// F32xF
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- // The longest available SIMD vector for storing 32-bit float values. Iterating laneCountF_32Bit floats at a time.
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+ // The longest available SIMD vector for storing 32-bit float values. Iterating laneCountF floats at a time.
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#if defined(USE_256BIT_F_SIMD) || defined(EMULATE_256BIT_F_SIMD)
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#define DSR_FLOAT_VECTOR_SIZE 32
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#define DSR_FLOAT_ALIGNMENT 32
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