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@@ -215,6 +215,9 @@ enum class ExecutionMode : unsigned {
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StreamingInterfaceINTEL = 6154,
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RegisterMapInterfaceINTEL = 6160,
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NamedBarrierCountINTEL = 6417,
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+ MaximumRegistersINTEL = 6461,
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+ MaximumRegistersIdINTEL = 6462,
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+ NamedMaximumRegistersINTEL = 6463,
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Max = 0x7fffffff,
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};
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@@ -1152,6 +1155,7 @@ enum class Capability : unsigned {
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RayQueryPositionFetchKHR = 5391,
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AtomicFloat16VectorNV = 5404,
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RayTracingDisplacementMicromapNV = 5409,
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+ RawAccessChainsNV = 5414,
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SubgroupShuffleINTEL = 5568,
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SubgroupBufferBlockIOINTEL = 5569,
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SubgroupImageBlockIOINTEL = 5570,
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@@ -1225,6 +1229,7 @@ enum class Capability : unsigned {
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GroupUniformArithmeticKHR = 6400,
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MaskedGatherScatterINTEL = 6427,
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CacheControlsINTEL = 6441,
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+ RegisterLimitsINTEL = 6460,
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Max = 0x7fffffff,
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};
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@@ -1393,6 +1398,23 @@ enum class StoreCacheControl : unsigned {
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Max = 0x7fffffff,
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};
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+enum class NamedMaximumNumberOfRegisters : unsigned {
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+ AutoINTEL = 0,
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+ Max = 0x7fffffff,
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+};
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+
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+enum class RawAccessChainOperandsShift : unsigned {
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+ RobustnessPerComponentNV = 0,
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+ RobustnessPerElementNV = 1,
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+ Max = 0x7fffffff,
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+};
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+
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+enum class RawAccessChainOperandsMask : unsigned {
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+ MaskNone = 0,
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+ RobustnessPerComponentNV = 0x00000001,
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+ RobustnessPerElementNV = 0x00000002,
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+};
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+
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enum class Op : unsigned {
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OpNop = 0,
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OpUndef = 1,
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@@ -1870,6 +1892,7 @@ enum class Op : unsigned {
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OpConvertUToSampledImageNV = 5395,
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OpConvertSampledImageToUNV = 5396,
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OpSamplerImageAddressingModeNV = 5397,
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+ OpRawAccessChainNV = 5398,
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OpSubgroupShuffleINTEL = 5571,
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OpSubgroupShuffleDownINTEL = 5572,
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OpSubgroupShuffleUpINTEL = 5573,
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@@ -2604,6 +2627,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
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case Op::OpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break;
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case Op::OpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break;
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case Op::OpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break;
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+ case Op::OpRawAccessChainNV: *hasResult = true; *hasResultType = true; break;
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case Op::OpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break;
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case Op::OpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break;
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case Op::OpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break;
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@@ -2908,6 +2932,10 @@ constexpr CooperativeMatrixOperandsMask operator|(CooperativeMatrixOperandsMask
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constexpr CooperativeMatrixOperandsMask operator&(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) & unsigned(b)); }
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constexpr CooperativeMatrixOperandsMask operator^(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) ^ unsigned(b)); }
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constexpr CooperativeMatrixOperandsMask operator~(CooperativeMatrixOperandsMask a) { return CooperativeMatrixOperandsMask(~unsigned(a)); }
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+constexpr RawAccessChainOperandsMask operator|(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) | unsigned(b)); }
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+constexpr RawAccessChainOperandsMask operator&(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) & unsigned(b)); }
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+constexpr RawAccessChainOperandsMask operator^(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) ^ unsigned(b)); }
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+constexpr RawAccessChainOperandsMask operator~(RawAccessChainOperandsMask a) { return RawAccessChainOperandsMask(~unsigned(a)); }
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} // end namespace spv
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