Fixed missing bitfieldInterleave definisions

glm/gtx/bit.inl

@@ -420,6 +420,62 @@ namespace glm
 			return REG1 | (REG2 << 1);
 		}
 
+		template <>
+		GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(glm::uint8 x, glm::uint8 y, glm::uint8 z)
+		{
+			glm::uint32 REG1(x);
+			glm::uint32 REG2(y);
+			glm::uint32 REG3(z);
+			
+			REG1 = ((REG1 << 16) | REG1) & glm::uint32(0x00FF0000FF0000FF);
+			REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF);
+			REG3 = ((REG3 << 16) | REG3) & glm::uint32(0x00FF0000FF0000FF);
+			
+			REG1 = ((REG1 <<  8) | REG1) & glm::uint32(0xF00F00F00F00F00F);
+			REG2 = ((REG2 <<  8) | REG2) & glm::uint32(0xF00F00F00F00F00F);
+			REG3 = ((REG3 <<  8) | REG3) & glm::uint32(0xF00F00F00F00F00F);
+			
+			REG1 = ((REG1 <<  4) | REG1) & glm::uint32(0x30C30C30C30C30C3);
+			REG2 = ((REG2 <<  4) | REG2) & glm::uint32(0x30C30C30C30C30C3);
+			REG3 = ((REG3 <<  4) | REG3) & glm::uint32(0x30C30C30C30C30C3);
+			
+			REG1 = ((REG1 <<  2) | REG1) & glm::uint32(0x9249249249249249);
+			REG2 = ((REG2 <<  2) | REG2) & glm::uint32(0x9249249249249249);
+			REG3 = ((REG3 <<  2) | REG3) & glm::uint32(0x9249249249249249);
+			
+			return REG1 | (REG2 << 1) | (REG3 << 2);
+		}
+		
+		template <>
+		GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint16 x, glm::uint16 y, glm::uint16 z)
+		{
+			glm::uint64 REG1(x);
+			glm::uint64 REG2(y);
+			glm::uint64 REG3(z);
+			
+			REG1 = ((REG1 << 32) | REG1) & glm::uint64(0xFFFF00000000FFFF);
+			REG2 = ((REG2 << 32) | REG2) & glm::uint64(0xFFFF00000000FFFF);
+			REG3 = ((REG3 << 32) | REG3) & glm::uint64(0xFFFF00000000FFFF);
+			
+			REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x00FF0000FF0000FF);
+			REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x00FF0000FF0000FF);
+			REG3 = ((REG3 << 16) | REG3) & glm::uint64(0x00FF0000FF0000FF);
+			
+			REG1 = ((REG1 <<  8) | REG1) & glm::uint64(0xF00F00F00F00F00F);
+			REG2 = ((REG2 <<  8) | REG2) & glm::uint64(0xF00F00F00F00F00F);
+			REG3 = ((REG3 <<  8) | REG3) & glm::uint64(0xF00F00F00F00F00F);
+			
+			REG1 = ((REG1 <<  4) | REG1) & glm::uint64(0x30C30C30C30C30C3);
+			REG2 = ((REG2 <<  4) | REG2) & glm::uint64(0x30C30C30C30C30C3);
+			REG3 = ((REG3 <<  4) | REG3) & glm::uint64(0x30C30C30C30C30C3);
+			
+			REG1 = ((REG1 <<  2) | REG1) & glm::uint64(0x9249249249249249);
+			REG2 = ((REG2 <<  2) | REG2) & glm::uint64(0x9249249249249249);
+			REG3 = ((REG3 <<  2) | REG3) & glm::uint64(0x9249249249249249);
+			
+			return REG1 | (REG2 << 1) | (REG3 << 2);
+		}
+		
 		template <>
 		GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint32 x, glm::uint32 y, glm::uint32 z)
 		{
@@ -450,6 +506,32 @@ namespace glm
 			return REG1 | (REG2 << 1) | (REG3 << 2);
 		}
 
+		template <>
+		GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(glm::uint8 x, glm::uint8 y, glm::uint8 z, glm::uint8 w)
+		{
+			glm::uint32 REG1(x);
+			glm::uint32 REG2(y);
+			glm::uint32 REG3(z);
+			glm::uint32 REG4(w);
+			
+			REG1 = ((REG1 << 12) | REG1) & glm::uint32(0x000F000F000F000F);
+			REG2 = ((REG2 << 12) | REG2) & glm::uint32(0x000F000F000F000F);
+			REG3 = ((REG3 << 12) | REG3) & glm::uint32(0x000F000F000F000F);
+			REG4 = ((REG4 << 12) | REG4) & glm::uint32(0x000F000F000F000F);
+			
+			REG1 = ((REG1 <<  6) | REG1) & glm::uint32(0x0303030303030303);
+			REG2 = ((REG2 <<  6) | REG2) & glm::uint32(0x0303030303030303);
+			REG3 = ((REG3 <<  6) | REG3) & glm::uint32(0x0303030303030303);
+			REG4 = ((REG4 <<  6) | REG4) & glm::uint32(0x0303030303030303);
+			
+			REG1 = ((REG1 <<  3) | REG1) & glm::uint32(0x1111111111111111);
+			REG2 = ((REG2 <<  3) | REG2) & glm::uint32(0x1111111111111111);
+			REG3 = ((REG3 <<  3) | REG3) & glm::uint32(0x1111111111111111);
+			REG4 = ((REG4 <<  3) | REG4) & glm::uint32(0x1111111111111111);
+			
+			return REG1 | (REG2 << 1) | (REG3 << 2) | (REG4 << 3);
+		}
+		
 		template <>
 		GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint16 x, glm::uint16 y, glm::uint16 z, glm::uint16 w)
 		{

readme.txt

@@ -47,6 +47,7 @@ GLM 0.9.5.3: 2014-0X-XX
 - Fixed CUDA issues (#169, #168, #183, #182)
 - Added support for all extensions but GTX_string_cast to CUDA
 - Fixed strict aliasing warnings in GCC 4.8.1 / Android NDK 9c (#152)
+- Fixed missing bitfieldInterleave definisions
 
 ================================================================================
 GLM 0.9.5.2: 2014-02-08