Fixed SIMD support detection

glm/detail/setup.hpp

@@ -700,73 +700,73 @@ namespace glm
 #	endif
 
 	// Report build target
-#	if GLM_ARCH == GLM_ARCH_X86
-#		if GLM_MODEL == GLM_MODEL_64
-#			pragma message("GLM: x86 64 bits build target")
-#		else
-#			pragma message("GLM: x86 32 bits build target")
-#		endif
-#	elif GLM_ARCH == GLM_ARCH_AVX2
+#	if GLM_ARCH & GLM_ARCH_AVX2_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: x86 64 bits with AVX2 instruction set build target")
 #		else
 #			pragma message("GLM: x86 32 bits with AVX2 instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_AVX)
+#	elif GLM_ARCH & GLM_ARCH_AVX_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: x86 64 bits with AVX instruction set build target")
 #		else
 #			pragma message("GLM: x86 32 bits with AVX instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_SSE42)
+#	elif GLM_ARCH & GLM_ARCH_SSE42_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: x86 64 bits with SSE4.2 instruction set build target")
 #		else
 #			pragma message("GLM: x86 32 bits with SSE4.2 instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_SSE41)
+#	elif GLM_ARCH & GLM_ARCH_SSE41_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: x86 64 bits with SSE4.1 instruction set build target")
 #		else
 #			pragma message("GLM: x86 32 bits with SSE4.1 instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_SSSE3)
+#	elif GLM_ARCH & GLM_ARCH_SSSE3_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: x86 64 bits with SSSE3 instruction set build target")
 #		else
 #			pragma message("GLM: x86 32 bits with SSSE3 instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_SSE3)
+#	elif GLM_ARCH & GLM_ARCH_SSE3_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: x86 64 bits with SSE3 instruction set build target")
 #		else
 #			pragma message("GLM: x86 32 bits with SSE3 instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_SSE2)
+#	elif GLM_ARCH & GLM_ARCH_SSE2_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: x86 64 bits with SSE2 instruction set build target")
 #		else
 #			pragma message("GLM: x86 32 bits with SSE2 instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_ARM)
+#	elif GLM_ARCH & GLM_ARCH_X86_BIT
 #		if GLM_MODEL == GLM_MODEL_64
-#			pragma message("GLM: ARM 64 bits build target")
+#			pragma message("GLM: x86 64 bits build target")
 #		else
-#			pragma message("GLM: ARM 32 bits build target")
+#			pragma message("GLM: x86 32 bits build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_NEON)
+#	elif GLM_ARCH & GLM_ARCH_NEON_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: ARM 64 bits with Neon instruction set build target")
 #		else
 #			pragma message("GLM: ARM 32 bits with Neon instruction set build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_MIPS)
+#	elif GLM_ARCH & GLM_ARCH_ARM_BIT
+#		if GLM_MODEL == GLM_MODEL_64
+#			pragma message("GLM: ARM 64 bits build target")
+#		else
+#			pragma message("GLM: ARM 32 bits build target")
+#		endif
+#	elif GLM_ARCH & GLM_ARCH_MIPS_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: MIPS 64 bits build target")
 #		else
 #			pragma message("GLM: MIPS 32 bits build target")
 #		endif
-#	elif(GLM_ARCH == GLM_ARCH_PPC)
+#	elif GLM_ARCH & GLM_ARCH_PPC_BIT
 #		if GLM_MODEL == GLM_MODEL_64
 #			pragma message("GLM: PowerPC 64 bits build target")
 #		else

glm/simd/platform.h

@@ -222,23 +222,25 @@
 
 // User defines: GLM_FORCE_PURE GLM_FORCE_SSE2 GLM_FORCE_SSE3 GLM_FORCE_AVX GLM_FORCE_AVX2 GLM_FORCE_AVX2
 
-#define GLM_ARCH_SIMD_BIT	(0x00001000)
 #define GLM_ARCH_MIPS_BIT	(0x10000000)
 #define GLM_ARCH_PPC_BIT	(0x20000000)
 #define GLM_ARCH_ARM_BIT	(0x40000000)
-#define GLM_ARCH_NEON_BIT	(0x00000001 | GLM_ARCH_SIMD_BIT)
 #define GLM_ARCH_X86_BIT	(0x80000000)
-#define GLM_ARCH_SSE2_BIT	(0x80000002 | GLM_ARCH_SIMD_BIT)
-#define GLM_ARCH_SSE3_BIT	(0x80000004 | GLM_ARCH_SIMD_BIT)
-#define GLM_ARCH_SSSE3_BIT	(0x80000008 | GLM_ARCH_SIMD_BIT)
-#define GLM_ARCH_SSE41_BIT	(0x80000010 | GLM_ARCH_SIMD_BIT)
-#define GLM_ARCH_SSE42_BIT	(0x80000020 | GLM_ARCH_SIMD_BIT)
-#define GLM_ARCH_AVX_BIT	(0x80000040 | GLM_ARCH_SIMD_BIT)
-#define GLM_ARCH_AVX2_BIT	(0x80000080 | GLM_ARCH_SIMD_BIT)
+
+#define GLM_ARCH_SIMD_BIT	(0x00001000)
+
+#define GLM_ARCH_NEON_BIT	(0x00000001)
+#define GLM_ARCH_SSE2_BIT	(0x00000002)
+#define GLM_ARCH_SSE3_BIT	(0x00000004)
+#define GLM_ARCH_SSSE3_BIT	(0x00000008)
+#define GLM_ARCH_SSE41_BIT	(0x00000010)
+#define GLM_ARCH_SSE42_BIT	(0x00000020)
+#define GLM_ARCH_AVX_BIT	(0x00000040)
+#define GLM_ARCH_AVX2_BIT	(0x00000080)
 
 #define GLM_ARCH_UNKNOWED	(0)
 #define GLM_ARCH_X86		(GLM_ARCH_X86_BIT)
-#define GLM_ARCH_SSE2		(GLM_ARCH_SSE2_BIT | GLM_ARCH_X86)
+#define GLM_ARCH_SSE2		(GLM_ARCH_SSE2_BIT | GLM_ARCH_SIMD_BIT | GLM_ARCH_X86)
 #define GLM_ARCH_SSE3		(GLM_ARCH_SSE3_BIT | GLM_ARCH_SSE2)
 #define GLM_ARCH_SSSE3		(GLM_ARCH_SSSE3_BIT | GLM_ARCH_SSE3)
 #define GLM_ARCH_SSE41		(GLM_ARCH_SSE41_BIT | GLM_ARCH_SSSE3)
@@ -246,7 +248,7 @@
 #define GLM_ARCH_AVX		(GLM_ARCH_AVX_BIT | GLM_ARCH_SSE42)
 #define GLM_ARCH_AVX2		(GLM_ARCH_AVX2_BIT | GLM_ARCH_AVX)
 #define GLM_ARCH_ARM		(GLM_ARCH_ARM_BIT)
-#define GLM_ARCH_NEON		(GLM_ARCH_NEON_BIT | GLM_ARCH_ARM)
+#define GLM_ARCH_NEON		(GLM_ARCH_NEON_BIT | GLM_ARCH_SIMD_BIT | GLM_ARCH_ARM)
 #define GLM_ARCH_MIPS		(GLM_ARCH_MIPS_BIT)
 #define GLM_ARCH_PPC		(GLM_ARCH_PPC_BIT)