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@@ -1,6 +1,6 @@
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/*
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** ARM64 IR assembler (SSA IR -> machine code).
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-** Copyright (C) 2005-2022 Mike Pall. See Copyright Notice in luajit.h
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+** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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**
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** Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
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** Sponsored by Cisco Systems, Inc.
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@@ -84,18 +84,23 @@ static void asm_guardcc(ASMState *as, A64CC cc)
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emit_cond_branch(as, cc, target);
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}
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-/* Emit test and branch instruction to exit for guard. */
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-static void asm_guardtnb(ASMState *as, A64Ins ai, Reg r, uint32_t bit)
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+/* Emit test and branch instruction to exit for guard, if in range. */
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+static int asm_guardtnb(ASMState *as, A64Ins ai, Reg r, uint32_t bit)
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{
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MCode *target = asm_exitstub_addr(as, as->snapno);
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MCode *p = as->mcp;
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+ ptrdiff_t delta = target - p;
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if (LJ_UNLIKELY(p == as->invmcp)) {
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+ if (as->orignins > 1023) return 0; /* Delta might end up too large. */
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as->loopinv = 1;
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- *p = A64I_B | A64F_S26(target-p);
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- emit_tnb(as, ai^0x01000000u, r, bit, p-1);
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- return;
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+ *p = A64I_B | A64F_S26(delta);
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+ ai ^= 0x01000000u;
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+ target = p-1;
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+ } else if (LJ_UNLIKELY(delta >= 0x1fff)) {
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+ return 0;
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}
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emit_tnb(as, ai, r, bit, target);
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+ return 1;
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}
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/* Emit compare and branch instruction to exit for guard. */
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@@ -211,16 +216,13 @@ static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow,
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static uint32_t asm_fuseopm(ASMState *as, A64Ins ai, IRRef ref, RegSet allow)
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{
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IRIns *ir = IR(ref);
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+ int logical = (ai & 0x1f000000) == 0x0a000000;
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if (ra_hasreg(ir->r)) {
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ra_noweak(as, ir->r);
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return A64F_M(ir->r);
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} else if (irref_isk(ref)) {
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- uint32_t m;
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int64_t k = get_k64val(as, ref);
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- if ((ai & 0x1f000000) == 0x0a000000)
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- m = emit_isk13(k, irt_is64(ir->t));
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- else
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- m = emit_isk12(k);
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+ uint32_t m = logical ? emit_isk13(k, irt_is64(ir->t)) : emit_isk12(k);
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if (m)
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return m;
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} else if (mayfuse(as, ref)) {
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@@ -232,7 +234,7 @@ static uint32_t asm_fuseopm(ASMState *as, A64Ins ai, IRRef ref, RegSet allow)
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(IR(ir->op2)->i & (irt_is64(ir->t) ? 63 : 31));
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IRIns *irl = IR(ir->op1);
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if (sh == A64SH_LSL &&
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- irl->o == IR_CONV &&
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+ irl->o == IR_CONV && !logical &&
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irl->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT) &&
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shift <= 4 &&
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canfuse(as, irl)) {
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@@ -242,7 +244,11 @@ static uint32_t asm_fuseopm(ASMState *as, A64Ins ai, IRRef ref, RegSet allow)
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Reg m = ra_alloc1(as, ir->op1, allow);
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return A64F_M(m) | A64F_SH(sh, shift);
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}
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- } else if (ir->o == IR_CONV &&
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+ } else if (ir->o == IR_BROR && logical && irref_isk(ir->op2)) {
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+ Reg m = ra_alloc1(as, ir->op1, allow);
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+ int shift = (IR(ir->op2)->i & (irt_is64(ir->t) ? 63 : 31));
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+ return A64F_M(m) | A64F_SH(A64SH_ROR, shift);
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+ } else if (ir->o == IR_CONV && !logical &&
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ir->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT)) {
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Reg m = ra_alloc1(as, ir->op1, allow);
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return A64F_M(m) | A64F_EX(A64EX_SXTW);
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@@ -419,7 +425,7 @@ static int asm_fuseorshift(ASMState *as, IRIns *ir)
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static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
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{
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uint32_t n, nargs = CCI_XNARGS(ci);
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- int32_t ofs = 0;
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+ int32_t spofs = 0, spalign = LJ_HASFFI && LJ_TARGET_OSX ? 0 : 7;
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Reg gpr, fpr = REGARG_FIRSTFPR;
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if (ci->func)
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emit_call(as, ci->func);
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@@ -438,8 +444,14 @@ static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
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fpr++;
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} else {
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Reg r = ra_alloc1(as, ref, RSET_FPR);
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- emit_spstore(as, ir, r, ofs + ((LJ_BE && !irt_isnum(ir->t)) ? 4 : 0));
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- ofs += 8;
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+ int32_t al = spalign;
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+#if LJ_HASFFI && LJ_TARGET_OSX
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+ al |= irt_isnum(ir->t) ? 7 : 3;
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+#endif
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+ spofs = (spofs + al) & ~al;
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+ if (LJ_BE && al >= 7 && !irt_isnum(ir->t)) spofs += 4, al -= 4;
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+ emit_spstore(as, ir, r, spofs);
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+ spofs += al + 1;
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}
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} else {
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if (gpr <= REGARG_LASTGPR) {
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@@ -449,10 +461,27 @@ static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
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gpr++;
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} else {
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Reg r = ra_alloc1(as, ref, RSET_GPR);
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- emit_spstore(as, ir, r, ofs + ((LJ_BE && !irt_is64(ir->t)) ? 4 : 0));
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- ofs += 8;
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+ int32_t al = spalign;
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+#if LJ_HASFFI && LJ_TARGET_OSX
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+ al |= irt_size(ir->t) - 1;
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+#endif
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+ spofs = (spofs + al) & ~al;
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+ if (al >= 3) {
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+ if (LJ_BE && al >= 7 && !irt_is64(ir->t)) spofs += 4, al -= 4;
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+ emit_spstore(as, ir, r, spofs);
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+ } else {
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+ lj_assertA(al == 0 || al == 1, "size %d unexpected", al + 1);
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+ emit_lso(as, al ? A64I_STRH : A64I_STRB, r, RID_SP, spofs);
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+ }
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+ spofs += al + 1;
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}
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}
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+#if LJ_HASFFI && LJ_TARGET_OSX
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+ } else { /* Marker for start of varargs. */
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+ gpr = REGARG_LASTGPR+1;
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+ fpr = REGARG_LASTFPR+1;
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+ spalign = 7;
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+#endif
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}
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}
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}
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@@ -518,8 +547,6 @@ static void asm_retf(ASMState *as, IRIns *ir)
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as->topslot -= (BCReg)delta;
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if ((int32_t)as->topslot < 0) as->topslot = 0;
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irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
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- /* Need to force a spill on REF_BASE now to update the stack slot. */
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- emit_lso(as, A64I_STRx, base, RID_SP, ra_spill(as, IR(REF_BASE)));
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emit_setgl(as, base, jit_base);
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emit_addptr(as, base, -8*delta);
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asm_guardcc(as, CC_NE);
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@@ -643,25 +670,22 @@ static void asm_strto(ASMState *as, IRIns *ir)
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{
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const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
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IRRef args[2];
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- Reg dest = 0, tmp;
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- int destused = ra_used(ir);
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+ Reg tmp;
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int32_t ofs = 0;
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ra_evictset(as, RSET_SCRATCH);
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- if (destused) {
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+ if (ra_used(ir)) {
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if (ra_hasspill(ir->s)) {
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ofs = sps_scale(ir->s);
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- destused = 0;
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if (ra_hasreg(ir->r)) {
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ra_free(as, ir->r);
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ra_modified(as, ir->r);
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emit_spload(as, ir, ir->r, ofs);
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}
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} else {
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- dest = ra_dest(as, ir, RSET_FPR);
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+ Reg dest = ra_dest(as, ir, RSET_FPR);
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+ emit_lso(as, A64I_LDRd, (dest & 31), RID_SP, 0);
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}
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}
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- if (destused)
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- emit_lso(as, A64I_LDRd, (dest & 31), RID_SP, 0);
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asm_guardcnb(as, A64I_CBZ, RID_RET);
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args[0] = ir->op1; /* GCstr *str */
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args[1] = ASMREF_TMP1; /* TValue *n */
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@@ -752,113 +776,76 @@ static void asm_href(ASMState *as, IRIns *ir, IROp merge)
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int destused = ra_used(ir);
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Reg dest = ra_dest(as, ir, allow);
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Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
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- Reg key = 0, tmp = RID_TMP;
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- Reg ftmp = RID_NONE, type = RID_NONE, scr = RID_NONE, tisnum = RID_NONE;
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+ Reg key = 0, tmp = RID_TMP, type = RID_NONE, tkey;
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IRRef refkey = ir->op2;
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IRIns *irkey = IR(refkey);
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- int isk = irref_isk(ir->op2);
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+ int isk = irref_isk(refkey);
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IRType1 kt = irkey->t;
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uint32_t k = 0;
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uint32_t khash;
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- MCLabel l_end, l_loop, l_next;
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+ MCLabel l_end, l_loop;
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rset_clear(allow, tab);
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- if (!isk) {
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- key = ra_alloc1(as, ir->op2, irt_isnum(kt) ? RSET_FPR : allow);
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+ /* Allocate registers outside of the loop. */
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+ if (irkey->o != IR_KNUM || !(k = emit_isk12((int64_t)ir_knum(irkey)->u64))) {
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+ key = ra_alloc1(as, refkey, irt_isnum(kt) ? RSET_FPR : allow);
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rset_clear(allow, key);
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- if (!irt_isstr(kt)) {
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- tmp = ra_scratch(as, allow);
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- rset_clear(allow, tmp);
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- }
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- } else if (irt_isnum(kt)) {
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- int64_t val = (int64_t)ir_knum(irkey)->u64;
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- if (!(k = emit_isk12(val))) {
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- key = ra_allock(as, val, allow);
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- rset_clear(allow, key);
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- }
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- } else if (!irt_ispri(kt)) {
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- if (!(k = emit_isk12(irkey->i))) {
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- key = ra_alloc1(as, refkey, allow);
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- rset_clear(allow, key);
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- }
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}
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-
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- /* Allocate constants early. */
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- if (irt_isnum(kt)) {
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- if (!isk) {
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- tisnum = ra_allock(as, LJ_TISNUM << 15, allow);
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- ftmp = ra_scratch(as, rset_exclude(RSET_FPR, key));
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- rset_clear(allow, tisnum);
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- }
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- } else if (irt_isaddr(kt)) {
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- if (isk) {
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- int64_t kk = ((int64_t)irt_toitype(kt) << 47) | irkey[1].tv.u64;
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- scr = ra_allock(as, kk, allow);
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+ if (!isk) {
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+ tkey = ra_scratch(as, allow);
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+ rset_clear(allow, tkey);
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+ } else if (irt_isnum(kt)) {
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+ tkey = key; /* Assumes -0.0 is already canonicalized to +0.0. */
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+ } else {
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+ int64_t kk;
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+ if (irt_isaddr(kt)) {
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+ kk = ((int64_t)irt_toitype(kt) << 47) | irkey[1].tv.u64;
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} else {
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- scr = ra_scratch(as, allow);
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+ lj_assertA(irt_ispri(kt) && !irt_isnil(kt), "bad HREF key type");
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+ kk = ~((int64_t)~irt_toitype(kt) << 47);
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}
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- rset_clear(allow, scr);
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- } else {
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- lj_assertA(irt_ispri(kt) && !irt_isnil(kt), "bad HREF key type");
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- type = ra_allock(as, ~((int64_t)~irt_toitype(kt) << 47), allow);
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- scr = ra_scratch(as, rset_clear(allow, type));
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- rset_clear(allow, scr);
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+ tkey = ra_allock(as, kk, allow);
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+ rset_clear(allow, tkey);
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}
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/* Key not found in chain: jump to exit (if merged) or load niltv. */
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l_end = emit_label(as);
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as->invmcp = NULL;
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- if (merge == IR_NE)
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+ if (merge == IR_NE) {
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asm_guardcc(as, CC_AL);
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- else if (destused)
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- emit_loada(as, dest, niltvg(J2G(as->J)));
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+ } else if (destused) {
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+ uint32_t k12 = emit_isk12(offsetof(global_State, nilnode.val));
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+ lj_assertA(k12 != 0, "Cannot k12 encode niltv(L)");
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+ emit_dn(as, A64I_ADDx^k12, dest, RID_GL);
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+ }
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/* Follow hash chain until the end. */
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l_loop = --as->mcp;
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- emit_n(as, A64I_CMPx^A64I_K12^0, dest);
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- emit_lso(as, A64I_LDRx, dest, dest, offsetof(Node, next));
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- l_next = emit_label(as);
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+ if (destused)
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+ emit_lso(as, A64I_LDRx, dest, dest, offsetof(Node, next));
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/* Type and value comparison. */
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if (merge == IR_EQ)
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asm_guardcc(as, CC_EQ);
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else
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emit_cond_branch(as, CC_EQ, l_end);
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+ emit_nm(as, A64I_CMPx^k, tmp, tkey);
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+ if (!destused)
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+ emit_lso(as, A64I_LDRx, dest, dest, offsetof(Node, next));
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+ emit_lso(as, A64I_LDRx, tmp, dest, offsetof(Node, key));
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+ *l_loop = A64I_X | A64I_CBNZ | A64F_S19(as->mcp - l_loop) | dest;
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- if (irt_isnum(kt)) {
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- if (isk) {
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- /* Assumes -0.0 is already canonicalized to +0.0. */
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- if (k)
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- emit_n(as, A64I_CMPx^k, tmp);
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- else
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- emit_nm(as, A64I_CMPx, key, tmp);
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- emit_lso(as, A64I_LDRx, tmp, dest, offsetof(Node, key.u64));
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- } else {
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- emit_nm(as, A64I_FCMPd, key, ftmp);
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- emit_dn(as, A64I_FMOV_D_R, (ftmp & 31), (tmp & 31));
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- emit_cond_branch(as, CC_LO, l_next);
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- emit_nm(as, A64I_CMPx | A64F_SH(A64SH_LSR, 32), tisnum, tmp);
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- emit_lso(as, A64I_LDRx, tmp, dest, offsetof(Node, key.n));
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- }
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- } else if (irt_isaddr(kt)) {
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- if (isk) {
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- emit_nm(as, A64I_CMPx, scr, tmp);
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- emit_lso(as, A64I_LDRx, tmp, dest, offsetof(Node, key.u64));
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+ /* Construct tkey as canonicalized or tagged key. */
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+ if (!isk) {
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+ if (irt_isnum(kt)) {
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+ emit_dnm(as, A64I_CSELx | A64F_CC(CC_EQ), tkey, RID_ZERO, tkey);
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} else {
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- emit_nm(as, A64I_CMPx, tmp, scr);
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- emit_lso(as, A64I_LDRx, scr, dest, offsetof(Node, key.u64));
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+ lj_assertA(irt_isaddr(kt), "bad HREF key type");
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+ type = ra_allock(as, irt_toitype(kt) << 15, allow);
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+ emit_dnm(as, A64I_ADDx | A64F_SH(A64SH_LSL, 32), tkey, key, type);
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}
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- } else {
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- emit_nm(as, A64I_CMPx, scr, type);
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- emit_lso(as, A64I_LDRx, scr, dest, offsetof(Node, key));
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}
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- *l_loop = A64I_BCC | A64F_S19(as->mcp - l_loop) | CC_NE;
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- if (!isk && irt_isaddr(kt)) {
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- type = ra_allock(as, (int32_t)irt_toitype(kt), allow);
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- emit_dnm(as, A64I_ADDx | A64F_SH(A64SH_LSL, 47), tmp, key, type);
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- rset_clear(allow, type);
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- }
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|
|
/* Load main position relative to tab->node into dest. */
|
|
|
khash = isk ? ir_khash(as, irkey) : 1;
|
|
|
if (khash == 0) {
|
|
|
@@ -872,7 +859,6 @@ static void asm_href(ASMState *as, IRIns *ir, IROp merge)
|
|
|
emit_dnm(as, A64I_ANDw, dest, dest, tmphash);
|
|
|
emit_lso(as, A64I_LDRw, dest, tab, offsetof(GCtab, hmask));
|
|
|
} else if (irt_isstr(kt)) {
|
|
|
- /* Fetch of str->sid is cheaper than ra_allock. */
|
|
|
emit_dnm(as, A64I_ANDw, dest, dest, tmp);
|
|
|
emit_lso(as, A64I_LDRw, tmp, key, offsetof(GCstr, sid));
|
|
|
emit_lso(as, A64I_LDRw, dest, tab, offsetof(GCtab, hmask));
|
|
|
@@ -881,23 +867,18 @@ static void asm_href(ASMState *as, IRIns *ir, IROp merge)
|
|
|
emit_lso(as, A64I_LDRw, tmp, tab, offsetof(GCtab, hmask));
|
|
|
emit_dnm(as, A64I_SUBw, dest, dest, tmp);
|
|
|
emit_dnm(as, A64I_EXTRw | (A64F_IMMS(32-HASH_ROT3)), tmp, tmp, tmp);
|
|
|
- emit_dnm(as, A64I_EORw, dest, dest, tmp);
|
|
|
- emit_dnm(as, A64I_EXTRw | (A64F_IMMS(32-HASH_ROT2)), dest, dest, dest);
|
|
|
+ emit_dnm(as, A64I_EORw | A64F_SH(A64SH_ROR, 32-HASH_ROT2), dest, tmp, dest);
|
|
|
emit_dnm(as, A64I_SUBw, tmp, tmp, dest);
|
|
|
emit_dnm(as, A64I_EXTRw | (A64F_IMMS(32-HASH_ROT1)), dest, dest, dest);
|
|
|
- emit_dnm(as, A64I_EORw, tmp, tmp, dest);
|
|
|
if (irt_isnum(kt)) {
|
|
|
+ emit_dnm(as, A64I_EORw, tmp, tkey, dest);
|
|
|
emit_dnm(as, A64I_ADDw, dest, dest, dest);
|
|
|
- emit_dn(as, A64I_LSRx | A64F_IMMR(32)|A64F_IMMS(32), dest, dest);
|
|
|
- emit_dm(as, A64I_MOVw, tmp, dest);
|
|
|
- emit_dn(as, A64I_FMOV_R_D, dest, (key & 31));
|
|
|
+ emit_dn(as, A64I_LSRx | A64F_IMMR(32)|A64F_IMMS(32), dest, tkey);
|
|
|
+ emit_nm(as, A64I_FCMPZd, (key & 31), 0);
|
|
|
+ emit_dn(as, A64I_FMOV_R_D, tkey, (key & 31));
|
|
|
} else {
|
|
|
- checkmclim(as);
|
|
|
- emit_dm(as, A64I_MOVw, tmp, key);
|
|
|
- emit_dnm(as, A64I_EORw, dest, dest,
|
|
|
- ra_allock(as, irt_toitype(kt) << 15, allow));
|
|
|
- emit_dn(as, A64I_LSRx | A64F_IMMR(32)|A64F_IMMS(32), dest, dest);
|
|
|
- emit_dm(as, A64I_MOVx, dest, key);
|
|
|
+ emit_dnm(as, A64I_EORw, tmp, key, dest);
|
|
|
+ emit_dnm(as, A64I_EORx | A64F_SH(A64SH_LSR, 32), dest, type, key);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
@@ -912,7 +893,7 @@ static void asm_hrefk(ASMState *as, IRIns *ir)
|
|
|
int bigofs = !emit_checkofs(A64I_LDRx, kofs);
|
|
|
Reg dest = (ra_used(ir) || bigofs) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
|
|
|
Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
|
|
|
- Reg key, idx = node;
|
|
|
+ Reg idx = node;
|
|
|
RegSet allow = rset_exclude(RSET_GPR, node);
|
|
|
uint64_t k;
|
|
|
lj_assertA(ofs % sizeof(Node) == 0, "unaligned HREFK slot");
|
|
|
@@ -931,9 +912,8 @@ static void asm_hrefk(ASMState *as, IRIns *ir)
|
|
|
} else {
|
|
|
k = ((uint64_t)irt_toitype(irkey->t) << 47) | (uint64_t)ir_kgc(irkey);
|
|
|
}
|
|
|
- key = ra_scratch(as, allow);
|
|
|
- emit_nm(as, A64I_CMPx, key, ra_allock(as, k, rset_exclude(allow, key)));
|
|
|
- emit_lso(as, A64I_LDRx, key, idx, kofs);
|
|
|
+ emit_nm(as, A64I_CMPx, RID_TMP, ra_allock(as, k, allow));
|
|
|
+ emit_lso(as, A64I_LDRx, RID_TMP, idx, kofs);
|
|
|
if (bigofs)
|
|
|
emit_opk(as, A64I_ADDx, dest, node, ofs, rset_exclude(RSET_GPR, node));
|
|
|
}
|
|
|
@@ -946,18 +926,16 @@ static void asm_uref(ASMState *as, IRIns *ir)
|
|
|
MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
|
|
|
emit_lsptr(as, A64I_LDRx, dest, v);
|
|
|
} else {
|
|
|
- Reg uv = ra_scratch(as, RSET_GPR);
|
|
|
- Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
|
|
|
if (ir->o == IR_UREFC) {
|
|
|
- asm_guardcc(as, CC_NE);
|
|
|
- emit_n(as, (A64I_CMPx^A64I_K12) | A64F_U12(1), RID_TMP);
|
|
|
- emit_opk(as, A64I_ADDx, dest, uv,
|
|
|
+ asm_guardcnb(as, A64I_CBZ, RID_TMP);
|
|
|
+ emit_opk(as, A64I_ADDx, dest, dest,
|
|
|
(int32_t)offsetof(GCupval, tv), RSET_GPR);
|
|
|
- emit_lso(as, A64I_LDRB, RID_TMP, uv, (int32_t)offsetof(GCupval, closed));
|
|
|
+ emit_lso(as, A64I_LDRB, RID_TMP, dest,
|
|
|
+ (int32_t)offsetof(GCupval, closed));
|
|
|
} else {
|
|
|
- emit_lso(as, A64I_LDRx, dest, uv, (int32_t)offsetof(GCupval, v));
|
|
|
+ emit_lso(as, A64I_LDRx, dest, dest, (int32_t)offsetof(GCupval, v));
|
|
|
}
|
|
|
- emit_lso(as, A64I_LDRx, uv, func,
|
|
|
+ emit_lso(as, A64I_LDRx, dest, ra_alloc1(as, ir->op1, RSET_GPR),
|
|
|
(int32_t)offsetof(GCfuncL, uvptr) + 8*(int32_t)(ir->op2 >> 8));
|
|
|
}
|
|
|
}
|
|
|
@@ -1063,7 +1041,7 @@ static void asm_xstore(ASMState *as, IRIns *ir)
|
|
|
|
|
|
static void asm_ahuvload(ASMState *as, IRIns *ir)
|
|
|
{
|
|
|
- Reg idx, tmp, type;
|
|
|
+ Reg idx, tmp;
|
|
|
int32_t ofs = 0;
|
|
|
RegSet gpr = RSET_GPR, allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR;
|
|
|
lj_assertA(irt_isnum(ir->t) || irt_ispri(ir->t) || irt_isaddr(ir->t) ||
|
|
|
@@ -1082,8 +1060,9 @@ static void asm_ahuvload(ASMState *as, IRIns *ir)
|
|
|
} else {
|
|
|
tmp = ra_scratch(as, gpr);
|
|
|
}
|
|
|
- type = ra_scratch(as, rset_clear(gpr, tmp));
|
|
|
- idx = asm_fuseahuref(as, ir->op1, &ofs, rset_clear(gpr, type), A64I_LDRx);
|
|
|
+ idx = asm_fuseahuref(as, ir->op1, &ofs, rset_clear(gpr, tmp), A64I_LDRx);
|
|
|
+ rset_clear(gpr, idx);
|
|
|
+ if (ofs & FUSE_REG) rset_clear(gpr, ofs & 31);
|
|
|
if (ir->o == IR_VLOAD) ofs += 8 * ir->op2;
|
|
|
/* Always do the type check, even if the load result is unused. */
|
|
|
asm_guardcc(as, irt_isnum(ir->t) ? CC_LS : CC_NE);
|
|
|
@@ -1091,10 +1070,10 @@ static void asm_ahuvload(ASMState *as, IRIns *ir)
|
|
|
lj_assertA(irt_isinteger(ir->t) || irt_isnum(ir->t),
|
|
|
"bad load type %d", irt_type(ir->t));
|
|
|
emit_nm(as, A64I_CMPx | A64F_SH(A64SH_LSR, 32),
|
|
|
- ra_allock(as, LJ_TISNUM << 15, rset_exclude(gpr, idx)), tmp);
|
|
|
+ ra_allock(as, LJ_TISNUM << 15, gpr), tmp);
|
|
|
} else if (irt_isaddr(ir->t)) {
|
|
|
- emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(-irt_toitype(ir->t)), type);
|
|
|
- emit_dn(as, A64I_ASRx | A64F_IMMR(47), type, tmp);
|
|
|
+ emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(-irt_toitype(ir->t)), RID_TMP);
|
|
|
+ emit_dn(as, A64I_ASRx | A64F_IMMR(47), RID_TMP, tmp);
|
|
|
} else if (irt_isnil(ir->t)) {
|
|
|
emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(1), tmp);
|
|
|
} else {
|
|
|
@@ -1217,9 +1196,8 @@ dotypecheck:
|
|
|
emit_nm(as, A64I_CMPx,
|
|
|
ra_allock(as, ~((int64_t)~irt_toitype(t) << 47) , allow), tmp);
|
|
|
} else {
|
|
|
- Reg type = ra_scratch(as, allow);
|
|
|
- emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(-irt_toitype(t)), type);
|
|
|
- emit_dn(as, A64I_ASRx | A64F_IMMR(47), type, tmp);
|
|
|
+ emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(-irt_toitype(t)), RID_TMP);
|
|
|
+ emit_dn(as, A64I_ASRx | A64F_IMMR(47), RID_TMP, tmp);
|
|
|
}
|
|
|
emit_lso(as, A64I_LDRx, tmp, base, ofs);
|
|
|
return;
|
|
|
@@ -1289,8 +1267,9 @@ static void asm_tbar(ASMState *as, IRIns *ir)
|
|
|
Reg link = ra_scratch(as, rset_exclude(RSET_GPR, tab));
|
|
|
Reg mark = RID_TMP;
|
|
|
MCLabel l_end = emit_label(as);
|
|
|
- emit_lso(as, A64I_STRx, link, tab, (int32_t)offsetof(GCtab, gclist));
|
|
|
emit_lso(as, A64I_STRB, mark, tab, (int32_t)offsetof(GCtab, marked));
|
|
|
+ /* Keep STRx in the middle to avoid LDP/STP fusion with surrounding code. */
|
|
|
+ emit_lso(as, A64I_STRx, link, tab, (int32_t)offsetof(GCtab, gclist));
|
|
|
emit_setgl(as, tab, gc.grayagain);
|
|
|
emit_dn(as, A64I_ANDw^emit_isk13(~LJ_GC_BLACK, 0), mark, mark);
|
|
|
emit_getgl(as, link, gc.grayagain);
|
|
|
@@ -1304,7 +1283,6 @@ static void asm_obar(ASMState *as, IRIns *ir)
|
|
|
const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
|
|
|
IRRef args[2];
|
|
|
MCLabel l_end;
|
|
|
- RegSet allow = RSET_GPR;
|
|
|
Reg obj, val, tmp;
|
|
|
/* No need for other object barriers (yet). */
|
|
|
lj_assertA(IR(ir->op1)->o == IR_UREFC, "bad OBAR type");
|
|
|
@@ -1315,14 +1293,13 @@ static void asm_obar(ASMState *as, IRIns *ir)
|
|
|
asm_gencall(as, ci, args);
|
|
|
emit_dm(as, A64I_MOVx, ra_releasetmp(as, ASMREF_TMP1), RID_GL);
|
|
|
obj = IR(ir->op1)->r;
|
|
|
- tmp = ra_scratch(as, rset_exclude(allow, obj));
|
|
|
- emit_cond_branch(as, CC_EQ, l_end);
|
|
|
- emit_n(as, A64I_TSTw^emit_isk13(LJ_GC_BLACK, 0), tmp);
|
|
|
+ tmp = ra_scratch(as, rset_exclude(RSET_GPR, obj));
|
|
|
+ emit_tnb(as, A64I_TBZ, tmp, lj_ffs(LJ_GC_BLACK), l_end);
|
|
|
emit_cond_branch(as, CC_EQ, l_end);
|
|
|
emit_n(as, A64I_TSTw^emit_isk13(LJ_GC_WHITES, 0), RID_TMP);
|
|
|
val = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, obj));
|
|
|
emit_lso(as, A64I_LDRB, tmp, obj,
|
|
|
- (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
|
|
|
+ (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
|
|
|
emit_lso(as, A64I_LDRB, RID_TMP, val, (int32_t)offsetof(GChead, marked));
|
|
|
}
|
|
|
|
|
|
@@ -1364,12 +1341,12 @@ static int asm_swapops(ASMState *as, IRRef lref, IRRef rref)
|
|
|
if (irref_isk(lref))
|
|
|
return 1; /* But swap constants to the right. */
|
|
|
ir = IR(rref);
|
|
|
- if ((ir->o >= IR_BSHL && ir->o <= IR_BSAR) ||
|
|
|
+ if ((ir->o >= IR_BSHL && ir->o <= IR_BROR) ||
|
|
|
(ir->o == IR_ADD && ir->op1 == ir->op2) ||
|
|
|
(ir->o == IR_CONV && ir->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT)))
|
|
|
return 0; /* Don't swap fusable operands to the left. */
|
|
|
ir = IR(lref);
|
|
|
- if ((ir->o >= IR_BSHL && ir->o <= IR_BSAR) ||
|
|
|
+ if ((ir->o >= IR_BSHL && ir->o <= IR_BROR) ||
|
|
|
(ir->o == IR_ADD && ir->op1 == ir->op2) ||
|
|
|
(ir->o == IR_CONV && ir->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT)))
|
|
|
return 1; /* But swap fusable operands to the right. */
|
|
|
@@ -1415,13 +1392,12 @@ static void asm_intneg(ASMState *as, IRIns *ir)
|
|
|
static void asm_intmul(ASMState *as, IRIns *ir)
|
|
|
{
|
|
|
Reg dest = ra_dest(as, ir, RSET_GPR);
|
|
|
- Reg left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, dest));
|
|
|
+ Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
|
|
|
Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
|
|
|
if (irt_isguard(ir->t)) { /* IR_MULOV */
|
|
|
asm_guardcc(as, CC_NE);
|
|
|
emit_dm(as, A64I_MOVw, dest, dest); /* Zero-extend. */
|
|
|
- emit_nm(as, A64I_CMPw | A64F_SH(A64SH_ASR, 31), RID_TMP, dest);
|
|
|
- emit_dn(as, A64I_ASRx | A64F_IMMR(32), RID_TMP, dest);
|
|
|
+ emit_nm(as, A64I_CMPx | A64F_EX(A64EX_SXTW), dest, dest);
|
|
|
emit_dnm(as, A64I_SMULL, dest, right, left);
|
|
|
} else {
|
|
|
emit_dnm(as, irt_is64(ir->t) ? A64I_MULx : A64I_MULw, dest, left, right);
|
|
|
@@ -1681,16 +1657,15 @@ static void asm_intcomp(ASMState *as, IRIns *ir)
|
|
|
if (asm_swapops(as, blref, brref)) {
|
|
|
Reg tmp = blref; blref = brref; brref = tmp;
|
|
|
}
|
|
|
+ bleft = ra_alloc1(as, blref, RSET_GPR);
|
|
|
if (irref_isk(brref)) {
|
|
|
uint64_t k = get_k64val(as, brref);
|
|
|
- if (k && !(k & (k-1)) && (cc == CC_EQ || cc == CC_NE)) {
|
|
|
- asm_guardtnb(as, cc == CC_EQ ? A64I_TBZ : A64I_TBNZ,
|
|
|
- ra_alloc1(as, blref, RSET_GPR), emit_ctz64(k));
|
|
|
+ if (k && !(k & (k-1)) && (cc == CC_EQ || cc == CC_NE) &&
|
|
|
+ asm_guardtnb(as, cc == CC_EQ ? A64I_TBZ : A64I_TBNZ, bleft,
|
|
|
+ emit_ctz64(k)))
|
|
|
return;
|
|
|
- }
|
|
|
m2 = emit_isk13(k, irt_is64(irl->t));
|
|
|
}
|
|
|
- bleft = ra_alloc1(as, blref, RSET_GPR);
|
|
|
ai = (irt_is64(irl->t) ? A64I_TSTx : A64I_TSTw);
|
|
|
if (!m2)
|
|
|
m2 = asm_fuseopm(as, ai, brref, rset_exclude(RSET_GPR, bleft));
|
|
|
@@ -1765,37 +1740,28 @@ static void asm_prof(ASMState *as, IRIns *ir)
|
|
|
static void asm_stack_check(ASMState *as, BCReg topslot,
|
|
|
IRIns *irp, RegSet allow, ExitNo exitno)
|
|
|
{
|
|
|
- Reg pbase;
|
|
|
uint32_t k;
|
|
|
+ Reg pbase = RID_BASE;
|
|
|
if (irp) {
|
|
|
- if (!ra_hasspill(irp->s)) {
|
|
|
- pbase = irp->r;
|
|
|
- lj_assertA(ra_hasreg(pbase), "base reg lost");
|
|
|
- } else if (allow) {
|
|
|
- pbase = rset_pickbot(allow);
|
|
|
- } else {
|
|
|
- pbase = RID_RET;
|
|
|
- emit_lso(as, A64I_LDRx, RID_RET, RID_SP, 0); /* Restore temp register. */
|
|
|
- }
|
|
|
- } else {
|
|
|
- pbase = RID_BASE;
|
|
|
+ pbase = irp->r;
|
|
|
+ if (!ra_hasreg(pbase))
|
|
|
+ pbase = allow ? (0x40 | rset_pickbot(allow)) : (0xC0 | RID_RET);
|
|
|
}
|
|
|
emit_cond_branch(as, CC_LS, asm_exitstub_addr(as, exitno));
|
|
|
+ if (pbase & 0x80) /* Restore temp. register. */
|
|
|
+ emit_lso(as, A64I_LDRx, (pbase & 31), RID_SP, 0);
|
|
|
k = emit_isk12((8*topslot));
|
|
|
lj_assertA(k, "slot offset %d does not fit in K12", 8*topslot);
|
|
|
emit_n(as, A64I_CMPx^k, RID_TMP);
|
|
|
- emit_dnm(as, A64I_SUBx, RID_TMP, RID_TMP, pbase);
|
|
|
+ emit_dnm(as, A64I_SUBx, RID_TMP, RID_TMP, (pbase & 31));
|
|
|
emit_lso(as, A64I_LDRx, RID_TMP, RID_TMP,
|
|
|
(int32_t)offsetof(lua_State, maxstack));
|
|
|
- if (irp) { /* Must not spill arbitrary registers in head of side trace. */
|
|
|
- if (ra_hasspill(irp->s))
|
|
|
- emit_lso(as, A64I_LDRx, pbase, RID_SP, sps_scale(irp->s));
|
|
|
- emit_lso(as, A64I_LDRx, RID_TMP, RID_GL, glofs(as, &J2G(as->J)->cur_L));
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- if (ra_hasspill(irp->s) && !allow)
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- emit_lso(as, A64I_STRx, RID_RET, RID_SP, 0); /* Save temp register. */
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- } else {
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- emit_getgl(as, RID_TMP, cur_L);
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+ if (pbase & 0x40) {
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+ emit_getgl(as, (pbase & 31), jit_base);
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+ if (pbase & 0x80) /* Save temp register. */
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+ emit_lso(as, A64I_STRx, (pbase & 31), RID_SP, 0);
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}
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+ emit_getgl(as, RID_TMP, cur_L);
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}
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|
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/* Restore Lua stack from on-trace state. */
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@@ -1837,7 +1803,7 @@ static void asm_stack_restore(ASMState *as, SnapShot *snap)
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|
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/* Marker to prevent patching the GC check exit. */
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#define ARM64_NOPATCH_GC_CHECK \
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- (A64I_ORRx|A64F_D(RID_TMP)|A64F_M(RID_TMP)|A64F_N(RID_TMP))
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+ (A64I_ORRx|A64F_D(RID_ZERO)|A64F_M(RID_ZERO)|A64F_N(RID_ZERO))
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|
|
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|
/* Check GC threshold and do one or more GC steps. */
|
|
|
static void asm_gc_check(ASMState *as)
|
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|
@@ -1892,46 +1858,40 @@ static void asm_loop_tail_fixup(ASMState *as)
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|
|
|
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|
/* -- Head of trace ------------------------------------------------------- */
|
|
|
|
|
|
-/* Reload L register from g->cur_L. */
|
|
|
-static void asm_head_lreg(ASMState *as)
|
|
|
-{
|
|
|
- IRIns *ir = IR(ASMREF_L);
|
|
|
- if (ra_used(ir)) {
|
|
|
- Reg r = ra_dest(as, ir, RSET_GPR);
|
|
|
- emit_getgl(as, r, cur_L);
|
|
|
- ra_evictk(as);
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
/* Coalesce BASE register for a root trace. */
|
|
|
static void asm_head_root_base(ASMState *as)
|
|
|
{
|
|
|
- IRIns *ir;
|
|
|
- asm_head_lreg(as);
|
|
|
- ir = IR(REF_BASE);
|
|
|
- if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
|
|
|
- ra_spill(as, ir);
|
|
|
- ra_destreg(as, ir, RID_BASE);
|
|
|
+ IRIns *ir = IR(REF_BASE);
|
|
|
+ Reg r = ir->r;
|
|
|
+ if (ra_hasreg(r)) {
|
|
|
+ ra_free(as, r);
|
|
|
+ if (rset_test(as->modset, r) || irt_ismarked(ir->t))
|
|
|
+ ir->r = RID_INIT; /* No inheritance for modified BASE register. */
|
|
|
+ if (r != RID_BASE)
|
|
|
+ emit_movrr(as, ir, r, RID_BASE);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
/* Coalesce BASE register for a side trace. */
|
|
|
static Reg asm_head_side_base(ASMState *as, IRIns *irp)
|
|
|
{
|
|
|
- IRIns *ir;
|
|
|
- asm_head_lreg(as);
|
|
|
- ir = IR(REF_BASE);
|
|
|
- if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
|
|
|
- ra_spill(as, ir);
|
|
|
- if (ra_hasspill(irp->s)) {
|
|
|
- return ra_dest(as, ir, RSET_GPR);
|
|
|
- } else {
|
|
|
- Reg r = irp->r;
|
|
|
- lj_assertA(ra_hasreg(r), "base reg lost");
|
|
|
- if (r != ir->r && !rset_test(as->freeset, r))
|
|
|
- ra_restore(as, regcost_ref(as->cost[r]));
|
|
|
- ra_destreg(as, ir, r);
|
|
|
- return r;
|
|
|
+ IRIns *ir = IR(REF_BASE);
|
|
|
+ Reg r = ir->r;
|
|
|
+ if (ra_hasreg(r)) {
|
|
|
+ ra_free(as, r);
|
|
|
+ if (rset_test(as->modset, r) || irt_ismarked(ir->t))
|
|
|
+ ir->r = RID_INIT; /* No inheritance for modified BASE register. */
|
|
|
+ if (irp->r == r) {
|
|
|
+ return r; /* Same BASE register already coalesced. */
|
|
|
+ } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
|
|
|
+ /* Move from coalesced parent reg. */
|
|
|
+ emit_movrr(as, ir, r, irp->r);
|
|
|
+ return irp->r;
|
|
|
+ } else {
|
|
|
+ emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
|
|
|
+ }
|
|
|
}
|
|
|
+ return RID_NONE;
|
|
|
}
|
|
|
|
|
|
/* -- Tail of trace ------------------------------------------------------- */
|
|
|
@@ -1975,19 +1935,41 @@ static void asm_tail_prep(ASMState *as)
|
|
|
/* Ensure there are enough stack slots for call arguments. */
|
|
|
static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
|
|
|
{
|
|
|
- IRRef args[CCI_NARGS_MAX*2];
|
|
|
+#if LJ_HASFFI
|
|
|
uint32_t i, nargs = CCI_XNARGS(ci);
|
|
|
- int nslots = 0, ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
|
|
|
- asm_collectargs(as, ir, ci, args);
|
|
|
- for (i = 0; i < nargs; i++) {
|
|
|
- if (args[i] && irt_isfp(IR(args[i])->t)) {
|
|
|
- if (nfpr > 0) nfpr--; else nslots += 2;
|
|
|
- } else {
|
|
|
- if (ngpr > 0) ngpr--; else nslots += 2;
|
|
|
+ if (nargs > (REGARG_NUMGPR < REGARG_NUMFPR ? REGARG_NUMGPR : REGARG_NUMFPR) ||
|
|
|
+ (LJ_TARGET_OSX && (ci->flags & CCI_VARARG))) {
|
|
|
+ IRRef args[CCI_NARGS_MAX*2];
|
|
|
+ int ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
|
|
|
+ int spofs = 0, spalign = LJ_TARGET_OSX ? 0 : 7, nslots;
|
|
|
+ asm_collectargs(as, ir, ci, args);
|
|
|
+ for (i = 0; i < nargs; i++) {
|
|
|
+ int al = spalign;
|
|
|
+ if (!args[i]) {
|
|
|
+#if LJ_TARGET_OSX
|
|
|
+ /* Marker for start of varaargs. */
|
|
|
+ nfpr = 0;
|
|
|
+ ngpr = 0;
|
|
|
+ spalign = 7;
|
|
|
+#endif
|
|
|
+ } else if (irt_isfp(IR(args[i])->t)) {
|
|
|
+ if (nfpr > 0) { nfpr--; continue; }
|
|
|
+#if LJ_TARGET_OSX
|
|
|
+ al |= irt_isnum(IR(args[i])->t) ? 7 : 3;
|
|
|
+#endif
|
|
|
+ } else {
|
|
|
+ if (ngpr > 0) { ngpr--; continue; }
|
|
|
+#if LJ_TARGET_OSX
|
|
|
+ al |= irt_size(IR(args[i])->t) - 1;
|
|
|
+#endif
|
|
|
+ }
|
|
|
+ spofs = (spofs + 2*al+1) & ~al; /* Align and bump stack pointer. */
|
|
|
}
|
|
|
+ nslots = (spofs + 3) >> 2;
|
|
|
+ if (nslots > as->evenspill) /* Leave room for args in stack slots. */
|
|
|
+ as->evenspill = nslots;
|
|
|
}
|
|
|
- if (nslots > as->evenspill) /* Leave room for args in stack slots. */
|
|
|
- as->evenspill = nslots;
|
|
|
+#endif
|
|
|
return REGSP_HINT(RID_RET);
|
|
|
}
|
|
|
|