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@@ -1246,7 +1246,7 @@ let load_native ctx lib name t =
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(function
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(function
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| [VType t] -> alloc_obj ctx t
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| [VType t] -> alloc_obj ctx t
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| _ -> assert false)
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| _ -> assert false)
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- | "alloc_enum" ->
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+ | "alloc_enum_dyn" ->
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(function
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(function
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| [VType (HEnum e); VInt idx; VArray (vl,vt); VInt len] ->
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| [VType (HEnum e); VInt idx; VArray (vl,vt); VInt len] ->
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let idx = int idx in
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let idx = int idx in
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@@ -2040,6 +2040,54 @@ let load_native ctx lib name t =
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| [VBytes file;VInt min;VInt max] ->
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| [VBytes file;VInt min;VInt max] ->
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VAbstract (APos { Globals.pfile = String.sub file 0 (String.length file - 1); pmin = Int32.to_int min; pmax = Int32.to_int max })
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VAbstract (APos { Globals.pfile = String.sub file 0 (String.length file - 1); pmin = Int32.to_int min; pmax = Int32.to_int max })
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| _ -> assert false)
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| _ -> assert false)
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+ | "dyn_op" ->
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+ let op_names = [|"+";"-";"*";"%";"/";"<<";">>";">>>";"&";"|";"^"|] in
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+ (function
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+ | [VInt op; a; b] ->
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+ let op = Int32.to_int op in
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+ let is_number v =
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+ match v with
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+ | VNull -> true
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+ | VDyn (_,t) -> is_number t
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+ | _ -> false
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+ in
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+ let error() =
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+ failwith ("Can't perform dyn op " ^ vstr ctx a HDyn ^ " " ^ op_names.(op) ^ " " ^ vstr ctx b HDyn)
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+ in
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+ let fop op =
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+ if is_number a && is_number b then begin
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+ let a = dyn_cast ctx a HDyn HF64 in
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+ let b = dyn_cast ctx b HDyn HF64 in
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+ match a, b with
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+ | VFloat a, VFloat b -> VDyn (VFloat (op a b),HF64)
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+ | _ -> assert false
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+ end else
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+ error();
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+ in
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+ let iop op =
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+ if is_number a && is_number b then begin
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+ let a = dyn_cast ctx a HDyn HI32 in
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+ let b = dyn_cast ctx b HDyn HI32 in
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+ match a, b with
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+ | VInt a, VInt b -> VDyn (VInt (op a b),HI32)
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+ | _ -> assert false
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+ end else
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+ error();
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+ in
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+ (match op with
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+ | 0 -> fop ( +. )
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+ | 1 -> fop ( -. )
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+ | 2 -> fop ( *. )
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+ | 3 -> fop mod_float
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+ | 4 -> fop ( /. )
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+ | 5 -> iop (fun a b -> Int32.shift_left a (Int32.to_int b))
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+ | 6 -> iop (fun a b -> Int32.shift_right a (Int32.to_int b))
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+ | 7 -> iop (fun a b -> Int32.shift_right_logical a (Int32.to_int b))
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+ | 8 -> iop Int32.logand
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+ | 9 -> iop Int32.logor
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+ | 10 -> iop Int32.logxor
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+ | _ -> assert false)
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+ | _ -> assert false)
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| _ ->
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| _ ->
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unresolved())
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unresolved())
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| "macro" ->
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| "macro" ->
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