* reverted r18262 and fixed tcgint-related range check errors correctly at

    the caller sides of that routine

git-svn-id: trunk@18272 -

compiler/powerpc/cgcpu.pas

@@ -77,7 +77,7 @@ unit cgcpu;
 
         { find out whether a is of the form 11..00..11b or 00..11...00. If }
         { that's the case, we can use rlwinm to do an AND operation        }
-        function get_rlwi_const(a: tcgint; var l1, l2: longint): boolean;
+        function get_rlwi_const(a: aint; var l1, l2: longint): boolean;
 
       protected
        procedure a_load_regconst_subsetreg_intern(list : TAsmList; fromsize, subsetsize: tcgsize; fromreg: tregister; const sreg: tsubsetregister; slopt: tsubsetloadopt); override;
@@ -435,7 +435,7 @@ const
           end;
         ophi := TOpCG2AsmOpConstHi[op];
         oplo := TOpCG2AsmOpConstLo[op];
-        gotrlwi := get_rlwi_const(a,l1,l2);
+        gotrlwi := get_rlwi_const(aint(a),l1,l2);
         if (op in [OP_AND,OP_OR,OP_XOR]) then
           begin
             if (a = 0) then
@@ -1627,11 +1627,11 @@ const
 
     { find out whether a is of the form 11..00..11b or 00..11...00. If }
     { that's the case, we can use rlwinm to do an AND operation        }
-    function tcgppc.get_rlwi_const(a: tcgint; var l1, l2: longint): boolean;
+    function tcgppc.get_rlwi_const(a: aint; var l1, l2: longint): boolean;
 
       var
         temp : longint;
-        testbit : tcgint;
+        testbit : aint;
         compare: boolean;
 
       begin
@@ -1742,8 +1742,8 @@ const
         case op of
           OP_AND,OP_OR,OP_XOR:
             begin
-              cg.a_op_const_reg_reg(list,op,OS_32,tcgint(value),regsrc.reglo,regdst.reglo);
-              cg.a_op_const_reg_reg(list,op,OS_32,tcgint(value shr 32),regsrc.reghi,
+              cg.a_op_const_reg_reg(list,op,OS_32,aint(value),regsrc.reglo,regdst.reglo);
+              cg.a_op_const_reg_reg(list,op,OS_32,aint(value shr 32),regsrc.reghi,
                 regdst.reghi);
             end;
           OP_ADD, OP_SUB:
@@ -1771,7 +1771,7 @@ const
                   else if ((value shr 32) = 0) then
                     begin
                       tmpreg := tcgppc(cg).rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
-                      cg.a_load_const_reg(list,OS_32,tcgint(value),tmpreg);
+                      cg.a_load_const_reg(list,OS_32,aint(value),tmpreg);
                       list.concat(taicpu.op_reg_reg_reg(ops[issub,2],
                         regdst.reglo,regsrc.reglo,tmpreg));
                       list.concat(taicpu.op_reg_reg(ops[issub,3],
@@ -1788,7 +1788,7 @@ const
               else
                 begin
                   cg.a_load_reg_reg(list,OS_INT,OS_INT,regsrc.reglo,regdst.reglo);
-                  cg.a_op_const_reg_reg(list,op,OS_32,tcgint(value shr 32),regsrc.reghi,
+                  cg.a_op_const_reg_reg(list,op,OS_32,aint(value shr 32),regsrc.reghi,
                     regdst.reghi);
                 end;
             end;