o merge of the branch laksen/arm-embedded of Jeppe Johansen:

  fixes a couple of arm-embedded stuff, 
  adds some controllers, start of fpv4_s16 support, for a complete list of
  changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line

Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line

Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line

Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line

Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines

Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line

Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line

Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line

Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines

Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines

Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines

Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines

Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines

Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines

Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)

git-svn-id: trunk@22792 -

.gitattributes

@@ -7429,12 +7429,17 @@ rtl/darwin/x86_64/sighnd.inc svneol=native#text/plain
 rtl/embedded/Makefile svneol=native#text/plain
 rtl/embedded/Makefile.fpc svneol=native#text/plain
 rtl/embedded/arm/at91sam7x256.pp svneol=native#text/plain
+rtl/embedded/arm/cortexm3_start.inc svneol=native#text/pascal
 rtl/embedded/arm/lm3fury.pp svneol=native#text/pascal
 rtl/embedded/arm/lm3tempest.pp svneol=native#text/pascal
 rtl/embedded/arm/lpc1768.pp svneol=native#text/pascal
 rtl/embedded/arm/lpc21x4.pp svneol=native#text/plain
 rtl/embedded/arm/sc32442b.pp svneol=native#text/pascal
-rtl/embedded/arm/stm32f103.pp svneol=native#text/plain
+rtl/embedded/arm/stm32f10x_conn.pp svneol=native#text/pascal
+rtl/embedded/arm/stm32f10x_hd.pp svneol=native#text/pascal
+rtl/embedded/arm/stm32f10x_ld.pp svneol=native#text/pascal
+rtl/embedded/arm/stm32f10x_md.pp svneol=native#text/pascal
+rtl/embedded/arm/stm32f10x_xl.pp svneol=native#text/pascal
 rtl/embedded/avr/atmega128.pp svneol=native#text/plain
 rtl/embedded/avr/start.inc svneol=native#text/plain
 rtl/embedded/buildrtl.lpi svneol=native#text/plain

compiler/aasmtai.pas

@@ -85,7 +85,10 @@ interface
 {$endif m68k}
 {$ifdef arm}
           ait_thumb_func,
+          ait_thumb_set,
 {$endif arm}
+          ait_set,
+          ait_weak,
           { used to split into tiny assembler files }
           ait_cutobject,
           ait_regalloc,
@@ -94,11 +97,13 @@ interface
           ait_marker,
           { used to describe a new location of a variable }
           ait_varloc,
-          { SEH directives used in ARM,MIPS and x86_64 COFF targets }
-          ait_seh_directive,
+{$ifdef JVM}
           { JVM only }
           ait_jvar,    { debug information for a local variable }
-          ait_jcatch   { exception catch clause }
+          ait_jcatch,  { exception catch clause }
+{$endif JVM}
+          { SEH directives used in ARM,MIPS and x86_64 COFF targets }
+          ait_seh_directive
           );
 
         taiconst_type = (
@@ -187,15 +192,20 @@ interface
 {$endif m68k}
 {$ifdef arm}
           'thumb_func',
+          'thumb_set',
 {$endif arm}
+          'set',
+          'weak',
           'cut',
           'regalloc',
           'tempalloc',
           'marker',
           'varloc',
-          'seh_directive',
+{$ifdef JVM}
           'jvar',
-          'jcatch'
+          'jcatch',
+{$endif JVM}
+          'seh_directive'
           );
 
     type
@@ -275,8 +285,11 @@ interface
                    ,ait_stab, ait_function_name, ait_force_line
                    ,ait_regalloc, ait_tempalloc, ait_symbol_end
 				   ,ait_ent, ait_ent_end, ait_directive
-                   ,ait_varloc,ait_seh_directive
-                   ,ait_jvar, ait_jcatch];
+                   ,ait_varloc,
+{$ifdef JVM}
+                   ait_jvar, ait_jcatch,
+{$endif JVM}
+                   ait_seh_directive];
 
       { ait_* types which do not have line information (and hence which are of type
         tai, otherwise, they are of type tailineinfo }
@@ -288,11 +301,15 @@ interface
 					 ait_ent, ait_ent_end,
 {$ifdef arm}
                      ait_thumb_func,
+                     ait_thumb_set,
 {$endif arm}
+                     ait_set,ait_weak,
                      ait_real_32bit,ait_real_64bit,ait_real_80bit,ait_comp_64bit,ait_real_128bit,
                      ait_symbol,
-                     ait_seh_directive,
-                     ait_jvar,ait_jcatch
+{$ifdef JVM}
+                     ait_jvar, ait_jcatch,
+{$endif JVM}
+                     ait_seh_directive
                     ];
 
 
@@ -790,6 +807,7 @@ interface
         end;
         tai_seh_directive_class=class of tai_seh_directive;
 
+{$ifdef JVM}
         { JVM variable live range description }
         tai_jvar = class(tai)
           stackslot: longint;
@@ -814,6 +832,30 @@ interface
           procedure ppuwrite(ppufile:tcompilerppufile);override;
         end;
         tai_jcatch_class = class of tai_jcatch;
+{$endif JVM}
+
+        tai_set = class(tai)
+          sym,
+          value: pshortstring;
+          constructor create(const asym, avalue: string);
+          destructor destroy;override;
+          constructor ppuload(t:taitype;ppufile:tcompilerppufile);override;
+          procedure ppuwrite(ppufile:tcompilerppufile);override;
+        end;
+
+{$ifdef arm}
+        tai_thumb_set = class(tai_set)
+          constructor create(const asym, avalue: string);
+        end;
+{$endif arm}
+
+        tai_weak = class(tai)
+          sym: pshortstring;
+          constructor create(const asym: string);
+          destructor destroy;override;
+          constructor ppuload(t:taitype;ppufile:tcompilerppufile);override;
+          procedure ppuwrite(ppufile:tcompilerppufile);override;
+        end;
 
     var
       { array with all class types for tais }
@@ -927,6 +969,69 @@ implementation
       end;
 
 
+    constructor tai_weak.create(const asym: string);
+      begin
+        inherited create;
+        typ:=ait_weak;
+        sym:=stringdup(asym);
+      end;
+
+    destructor tai_weak.destroy;
+      begin
+        stringdispose(sym);
+        inherited destroy;
+      end;
+
+    constructor tai_weak.ppuload(t: taitype; ppufile: tcompilerppufile);
+      begin
+        inherited ppuload(t,ppufile);
+        sym:=stringdup(ppufile.getstring);
+      end;
+
+    procedure tai_weak.ppuwrite(ppufile: tcompilerppufile);
+      begin
+        inherited ppuwrite(ppufile);
+        ppufile.putstring(sym^);
+      end;
+
+{$ifdef arm}
+    constructor tai_thumb_set.create(const asym, avalue: string);
+      begin
+        inherited create(asym, avalue);
+        typ:=ait_thumb_set;
+      end;
+{$endif arm}
+
+    constructor tai_set.create(const asym, avalue: string);
+      begin
+        inherited create;
+        typ:=ait_set;
+        sym:=stringdup(asym);
+        value:=stringdup(avalue);
+      end;
+
+    destructor tai_set.destroy;
+      begin
+        stringdispose(sym);
+        stringdispose(value);
+        inherited destroy;
+      end;
+
+    constructor tai_set.ppuload(t: taitype; ppufile: tcompilerppufile);
+      begin
+        inherited ppuload(t,ppufile);
+        sym:=stringdup(ppufile.getstring);
+        value:=stringdup(ppufile.getstring);
+      end;
+
+    procedure tai_set.ppuwrite(ppufile: tcompilerppufile);
+      begin
+        inherited ppuwrite(ppufile);
+        ppufile.putstring(sym^);
+        ppufile.putstring(value^);
+      end;
+
+
     constructor tai_varloc.create(sym: tsym; loc: tregister);
       begin
         inherited Create;
@@ -2823,6 +2928,7 @@ implementation
       begin
       end;
 
+{$ifdef JVM}
 
 {****************************************************************************
                               tai_jvar
@@ -2913,6 +3019,7 @@ implementation
         ppufile.putasmsymbol(handlerlab);
       end;
 
+{$endif JVM}
 
 begin
 {$push}{$warnings off}

compiler/aggas.pas

@@ -1286,7 +1286,19 @@ implementation
              begin
                AsmWriteLn(#9'.thumb_func');
              end;
+           ait_thumb_set:
+             begin
+               AsmWriteLn(#9'.thumb_set '+tai_thumb_set(hp).sym^+', '+tai_thumb_set(hp).value^);
+             end;
 {$endif arm}
+           ait_set:
+             begin
+               AsmWriteLn(#9'.set '+tai_set(hp).sym^+', '+tai_set(hp).value^);
+             end;
+           ait_weak:
+             begin
+               AsmWriteLn(#9'.weak '+tai_weak(hp).sym^);
+             end;
            ait_ent:
              begin
                AsmWrite(#9'.ent'#9);

compiler/arm/aasmcpu.pas

@@ -175,6 +175,7 @@ uses
          constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
          constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
 
+         constructor op_regset(op:tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
          constructor op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
 
          constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
@@ -269,7 +270,7 @@ uses
 implementation
 
   uses
-    cutils,rgobj,itcpugas;
+    cutils,rgobj,itcpugas,aoptcpu;
 
 
     procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop);
@@ -415,6 +416,13 @@ implementation
          loadconst(1,aint(_op2));
       end;
 
+    constructor taicpu.op_regset(op: tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
+      begin
+        inherited create(op);
+        ops:=1;
+        loadregset(0,regtype,subreg,_op1);
+      end;
+
 
     constructor taicpu.op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
       begin
@@ -478,8 +486,8 @@ implementation
     constructor taicpu.op_cond(op: tasmop; cond: tasmcond);
       begin
         inherited create(op);
-        ops:=0;
-        condition := cond;
+        ops:=1;
+        loadconditioncode(0, cond);
       end;
 
     constructor taicpu.op_modeflags(op: tasmop; flags: tcpumodeflags);
@@ -1090,13 +1098,110 @@ implementation
           end;
       end;
 
-    procedure finalizearmcode(list, listtoinsert: TAsmList);
+
+    function getMergedInstruction(FirstOp,LastOp:TAsmOp;InvertLast:boolean) : TAsmOp;
+      const
+        opTable: array[A_IT..A_ITTTT] of string =
+          ('T','TE','TT','TEE','TTE','TET','TTT',
+           'TEEE','TTEE','TETE','TTTE',
+           'TEET','TTET','TETT','TTTT');
+        invertedOpTable: array[A_IT..A_ITTTT] of string =
+          ('E','ET','EE','ETT','EET','ETE','EEE',
+           'ETTT','EETT','ETET','EEET',
+           'ETTE','EETE','ETEE','EEEE');
+      var
+        resStr : string;
+        i : TAsmOp;
       begin
-        insertpcrelativedata(list, listtoinsert);
+        if InvertLast then
+          resStr := opTable[FirstOp]+invertedOpTable[LastOp]
+        else
+          resStr := opTable[FirstOp]+opTable[LastOp];
+        if length(resStr) > 4 then
+          internalerror(2012100805);
+
+        for i := low(opTable) to high(opTable) do
+          if opTable[i] = resStr then
+            exit(i);
+
+        internalerror(2012100806);
+      end;
+
+    procedure foldITInstructions(list: TAsmList);
+      var
+        curtai,hp1 : tai;
+        levels,i : LongInt;
+      begin
+        curtai:=tai(list.First);
+        while assigned(curtai) do
+          begin
+            case curtai.typ of
+              ait_instruction:
+                if IsIT(taicpu(curtai).opcode) then
+                  begin
+                    levels := GetITLevels(taicpu(curtai).opcode);
+                    if levels < 4 then
+                      begin
+                        i:=levels;
+                        hp1:=tai(curtai.Next);
+                        while assigned(hp1) and
+                          (i > 0) do
+                          begin
+                            if hp1.typ=ait_instruction then
+                              begin
+                                dec(i);
+                                if (i = 0) and
+                                  mustbelast(hp1) then
+                                  begin
+                                    hp1:=nil;
+                                    break;
+                                  end;
+                              end;
+                            hp1:=tai(hp1.Next);
+                          end;
+
+                        if assigned(hp1) then
+                          begin
+                            // We are pointing at the first instruction after the IT block
+                            while assigned(hp1) and
+                              (hp1.typ<>ait_instruction) do
+                                hp1:=tai(hp1.Next);
+
+                            if assigned(hp1) and
+                              (hp1.typ=ait_instruction) and
+                              IsIT(taicpu(hp1).opcode) then
+                              begin
+                                if (levels+GetITLevels(taicpu(hp1).opcode) <= 4) and
+                                  ((taicpu(curtai).oper[0]^.cc=taicpu(hp1).oper[0]^.cc) or
+                                   (taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc))) then
+                                  begin
+                                    taicpu(curtai).opcode:=getMergedInstruction(taicpu(curtai).opcode,
+                                                                                taicpu(hp1).opcode,
+                                                                                taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc));
+
+                                    list.Remove(hp1);
+                                    hp1.Free;
+                                  end;
+                              end;
+                          end;
+                      end;
+                  end;
+            end;
+
+            curtai:=tai(curtai.Next);
+          end;
+      end;
 
+    procedure finalizearmcode(list, listtoinsert: TAsmList);
+      begin
         { Do Thumb-2 16bit -> 32bit transformations }
         if current_settings.cputype in cpu_thumb2 then
-          ensurethumb2encodings(list);
+          begin
+            ensurethumb2encodings(list);
+            foldITInstructions(list);
+          end;
+
+        insertpcrelativedata(list, listtoinsert);
       end;
 
     procedure InsertPData;

compiler/arm/agarmgas.pas

@@ -106,11 +106,13 @@ unit agarmgas;
           result:='-mfpu=vfpv3 '+result;
         if (current_settings.fputype = fpu_vfpv3_d16) then
           result:='-mfpu=vfpv3-d16 '+result;
+        if (current_settings.fputype = fpu_fpv4_s16) then
+          result:='-mfpu=fpv4-sp-d16 '+result;
 
         if current_settings.cputype=cpu_armv7m then
           result:='-march=armv7m -mthumb -mthumb-interwork '+result
-        { pass only cpu types >= armv6 because the rtl uses runtime selected code with armv5te statements }
-        else if current_settings.cputype>=cpu_armv6 then
+        // EDSP instructions in RTL require armv5te at least to not generate error
+        else if current_settings.cputype >= cpu_armv5te then
           result:='-march='+cputype_to_gas_march[current_settings.cputype]+' '+result;
 
         if target_info.abi = abi_eabihf then
@@ -292,8 +294,10 @@ unit agarmgas;
 
           if taicpu(hp).ops = 0 then
             s:=#9+gas_op2str[op]+' '+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix]
+          else if (taicpu(hp).opcode>=A_VABS) and (taicpu(hp).opcode<=A_VSUB) then
+            s:=#9+gas_op2str[op]+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix]
           else
-            s:=#9+gas_op2str[op]+oppostfix2str[taicpu(hp).oppostfix]+postfix+cond2str[taicpu(hp).condition]; // Conditional infixes are deprecated in unified syntax
+            s:=#9+gas_op2str[op]+oppostfix2str[taicpu(hp).oppostfix]+cond2str[taicpu(hp).condition]+postfix; // Conditional infixes are deprecated in unified syntax
         end
       else
         s:=#9+gas_op2str[op]+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix];

compiler/arm/aoptcpu.pas

@@ -30,7 +30,7 @@ Unit aoptcpu;
 
 Interface
 
-uses cgbase, cpubase, aasmtai, aasmcpu,aopt, aoptcpub, aoptobj;
+uses cgbase, cpubase, aasmtai, aasmcpu,aopt, aoptcpub, aoptobj, cclasses;
 
 Type
   TCpuAsmOptimizer = class(TAsmOptimizer)
@@ -62,9 +62,12 @@ Type
 
   TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
     { uses the same constructor as TAopObj }
+    function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
     procedure PeepHoleOptPass2;override;
   End;
 
+  function MustBeLast(p : tai) : boolean;
+
 Implementation
 
   uses
@@ -79,6 +82,9 @@ Implementation
       result:=
         (p.typ=ait_instruction) and
         (taicpu(p).condition=C_None) and
+        ((taicpu(p).opcode<A_IT) or (taicpu(p).opcode>A_ITTTT)) and
+        (taicpu(p).opcode<>A_CBZ) and
+        (taicpu(p).opcode<>A_CBNZ) and
         (taicpu(p).opcode<>A_PLD) and
         ((taicpu(p).opcode<>A_BLX) or
          (taicpu(p).oper[0]^.typ=top_reg));
@@ -269,6 +275,15 @@ Implementation
       end;
   end;
 
+  function isValidConstLoadStoreOffset(const aoffset: longint; const pf: TOpPostfix) : boolean;
+    begin
+      if current_settings.cputype in cpu_thumb2 then
+        result := (aoffset<4096) and (aoffset>-256)
+      else
+        result := ((pf in [PF_None,PF_B]) and
+                   (abs(aoffset)<4096)) or
+                  (abs(aoffset)<256);
+    end;
 
   function TCpuAsmOptimizer.RegUsedAfterInstruction(reg: Tregister; p: tai;
     var AllUsedRegs: TAllUsedRegs): Boolean;
@@ -321,6 +336,9 @@ Implementation
          (taicpu(movp).oper[0]^.reg<>NR_R14) and
          { the destination register of the mov might not be used beween p and movp }
          not(RegUsedBetween(taicpu(movp).oper[0]^.reg,p,movp)) and
+         { cb[n]z are thumb instructions which require specific registers, with no wide forms }
+         (taicpu(p).opcode<>A_CBZ) and
+         (taicpu(p).opcode<>A_CBNZ) and
          {There is a special requirement for MUL and MLA, oper[0] and oper[1] are not allowed to be the same}
          not (
            (taicpu(p).opcode in [A_MLA, A_MUL]) and
@@ -1106,16 +1124,10 @@ Implementation
                           { new offset must be valid: either in the range of 8 or 12 bit, depend on the
                             ldr postfix }
                           (((taicpu(p).opcode=A_ADD) and
-                            (((taicpu(hp1).oppostfix in [PF_None,PF_B]) and
-                              (abs(taicpu(hp1).oper[1]^.ref^.offset+taicpu(p).oper[2]^.val)<4096)) or
-                             (abs(taicpu(hp1).oper[1]^.ref^.offset+taicpu(p).oper[2]^.val)<256)
-                            )
+                           isValidConstLoadStoreOffset(taicpu(hp1).oper[1]^.ref^.offset+taicpu(p).oper[2]^.val, taicpu(hp1).oppostfix)
                            ) or
                            ((taicpu(p).opcode=A_SUB) and
-                             (((taicpu(hp1).oppostfix in [PF_None,PF_B]) and
-                               (abs(taicpu(hp1).oper[1]^.ref^.offset-taicpu(p).oper[2]^.val)<4096)) or
-                              (abs(taicpu(hp1).oper[1]^.ref^.offset-taicpu(p).oper[2]^.val)<256)
-                             )
+                            isValidConstLoadStoreOffset(taicpu(hp1).oper[1]^.ref^.offset-taicpu(p).oper[2]^.val, taicpu(hp1).oppostfix)
                            )
                           ) do
                           begin
@@ -1160,6 +1172,114 @@ Implementation
                     if GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) then
                       RemoveSuperfluousMove(p, hp1, 'DataMov2Data');
                   end;
+                A_MVN:
+                  begin
+                    {
+                      change
+                      mvn reg2,reg1
+                      and reg3,reg4,reg2
+                      dealloc reg2
+                      to
+                      bic reg3,reg4,reg1
+                    }
+                    if (taicpu(p).oper[1]^.typ = top_reg) and
+                      GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
+                      MatchInstruction(hp1,A_AND,[],[]) and
+                      (((taicpu(hp1).ops=3) and
+                        (taicpu(hp1).oper[2]^.typ=top_reg) and
+                        (MatchOperand(taicpu(hp1).oper[2]^, taicpu(p).oper[0]^.reg) or
+                         MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg))) or
+                       ((taicpu(hp1).ops=2) and
+                        (taicpu(hp1).oper[1]^.typ=top_reg) and
+                        MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg))) and
+                      assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
+                      { reg1 might not be modified inbetween }
+                      not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
+                      begin
+                        DebugMsg('Peephole MvnAnd2Bic done', p);
+                        taicpu(hp1).opcode:=A_BIC;
+
+                        if taicpu(hp1).ops=3 then
+                          begin
+                            if MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) then
+                              taicpu(hp1).loadReg(1,taicpu(hp1).oper[2]^.reg); // Swap operands
+
+                            taicpu(hp1).loadReg(2,taicpu(p).oper[1]^.reg);
+                          end
+                        else
+                          taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
+                        asml.remove(p);
+                        p.free;
+                        p:=hp1;
+                      end;
+                  end;
+                A_UXTB:
+                  begin
+                    {
+                      change
+                      uxtb reg2,reg1
+                      strb reg2,[...]
+                      dealloc reg2
+                      to
+                      strb reg1,[...]
+                    }
+                    if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
+                      GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
+                      MatchInstruction(hp1, A_STR, [C_None], [PF_B]) and
+                      assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
+                      { the reference in strb might not use reg2 }
+                      not(RegInRef(taicpu(p).oper[0]^.reg,taicpu(hp1).oper[1]^.ref^)) and
+                      { reg1 might not be modified inbetween }
+                      not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
+                      begin
+                        DebugMsg('Peephole UxtbStrb2Strb done', p);
+                        taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
+                        asml.remove(p);
+                        p.free;
+                        p:=hp1;
+                      end
+                    {
+                      change
+                      uxtb reg2,reg1
+                      uxth reg3,reg2
+                      dealloc reg2
+                      to
+                      uxtb reg3,reg1
+                    }
+                    else if MatchInstruction(p, A_UXTB, [C_None], [PF_None]) and
+                      GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
+                      MatchInstruction(hp1, A_UXTH, [C_None], [PF_None]) and
+                      (assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) or
+                       (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg)) and
+                      { reg1 might not be modified inbetween }
+                      not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
+                      begin
+                        DebugMsg('Peephole UxtbUxth2Uxtb done', p);
+                        taicpu(hp1).opcode:=A_UXTB;
+                        taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
+                        asml.remove(p);
+                        p.free;
+                        p:=hp1;
+                      end;
+                  end;
+                A_UXTH:
+                  begin
+                    if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
+                      GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
+                      MatchInstruction(hp1, A_STR, [C_None], [PF_H]) and
+                      assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
+                      { the reference in strb might not use reg2 }
+                      not(RegInRef(taicpu(p).oper[0]^.reg,taicpu(hp1).oper[1]^.ref^)) and
+                      { reg1 might not be modified inbetween }
+                      not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
+                      begin
+                        DebugMsg('Peephole UXTHStrh2Strh done', p);
+                        taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
+                        asml.remove(p);
+                        p.free;
+                        p:=hp1;
+                      end;
+                  end;
                 A_CMP:
                   begin
                     {
@@ -1574,9 +1694,355 @@ Implementation
     end;
 
 
+  procedure DecrementPreceedingIT(list: TAsmList; p: tai);
+    var
+      hp : tai;
+      l : longint;
+    begin
+      hp := tai(p.Previous);
+      l := 1;
+
+      while assigned(hp) and
+        (l <= 4) do
+        begin
+          if hp.typ=ait_instruction then
+            begin
+              if (taicpu(hp).opcode>=A_IT) and
+                (taicpu(hp).opcode <= A_ITTTT) then
+                begin
+                  if (taicpu(hp).opcode = A_IT) and
+                     (l=1) then
+                    list.Remove(hp)
+                  else
+                    case taicpu(hp).opcode of
+                      A_ITE:
+                        if l=2 then taicpu(hp).opcode := A_IT;
+                      A_ITT:
+                        if l=2 then taicpu(hp).opcode := A_IT;
+                      A_ITEE:
+                        if l=3 then taicpu(hp).opcode := A_ITE;
+                      A_ITTE:
+                        if l=3 then taicpu(hp).opcode := A_ITT;
+                      A_ITET:
+                        if l=3 then taicpu(hp).opcode := A_ITE;
+                      A_ITTT:
+                        if l=3 then taicpu(hp).opcode := A_ITT;
+                      A_ITEEE:
+                        if l=4 then taicpu(hp).opcode := A_ITEE;
+                      A_ITTEE:
+                        if l=4 then taicpu(hp).opcode := A_ITTE;
+                      A_ITETE:
+                        if l=4 then taicpu(hp).opcode := A_ITET;
+                      A_ITTTE:
+                        if l=4 then taicpu(hp).opcode := A_ITTT;
+                      A_ITEET:
+                        if l=4 then taicpu(hp).opcode := A_ITEE;
+                      A_ITTET:
+                        if l=4 then taicpu(hp).opcode := A_ITTE;
+                      A_ITETT:
+                        if l=4 then taicpu(hp).opcode := A_ITET;
+                      A_ITTTT:
+                        if l=4 then taicpu(hp).opcode := A_ITTT;
+                    end;
+
+                  break;
+                end;
+              {else if (taicpu(hp).condition<>taicpu(p).condition) or
+                (taicpu(hp).condition<>inverse_cond(taicpu(p).condition)) then
+                break;}
+
+              inc(l);
+            end;
+          hp := tai(hp.Previous);
+        end;
+    end;
+
+  function TCpuThumb2AsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
+    var
+      hp : taicpu;
+      hp1,hp2 : tai;
+    begin
+      if (p.typ=ait_instruction) and
+        MatchInstruction(p, A_STM, [C_None], [PF_FD,PF_DB]) and
+        (taicpu(p).oper[0]^.ref^.addressmode=AM_PREINDEXED) and
+        (taicpu(p).oper[0]^.ref^.index=NR_STACK_POINTER_REG) and
+        ((taicpu(p).oper[1]^.regset^*[8..13,15])=[]) then
+        begin
+          hp := taicpu.op_regset(A_PUSH, R_INTREGISTER, R_SUBWHOLE, taicpu(p).oper[1]^.regset^);
+          AsmL.InsertAfter(hp, p);
+          asml.Remove(p);
+          p:=hp;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, A_STR, [C_None], [PF_None]) and
+        (taicpu(p).oper[1]^.ref^.addressmode=AM_PREINDEXED) and
+        (taicpu(p).oper[1]^.ref^.index=NR_STACK_POINTER_REG) and
+        (taicpu(p).oper[1]^.ref^.offset=-4) and
+        (getsupreg(taicpu(p).oper[0]^.reg) in [0..7,14]) then
+        begin
+          hp := taicpu.op_regset(A_PUSH, R_INTREGISTER, R_SUBWHOLE, [getsupreg(taicpu(p).oper[0]^.reg)]);
+          asml.InsertAfter(hp, p);
+          asml.Remove(p);
+          p.Free;
+          p:=hp;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, A_LDM, [C_None], [PF_FD,PF_IA]) and
+        (taicpu(p).oper[0]^.ref^.addressmode=AM_PREINDEXED) and
+        (taicpu(p).oper[0]^.ref^.index=NR_STACK_POINTER_REG) and
+        ((taicpu(p).oper[1]^.regset^*[8..14])=[]) then
+        begin
+          hp := taicpu.op_regset(A_POP, R_INTREGISTER, R_SUBWHOLE, taicpu(p).oper[1]^.regset^);
+          asml.InsertBefore(hp, p);
+          asml.Remove(p);
+          p.Free;
+          p:=hp;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, A_LDR, [C_None], [PF_None]) and
+        (taicpu(p).oper[1]^.ref^.addressmode=AM_POSTINDEXED) and
+        (taicpu(p).oper[1]^.ref^.index=NR_STACK_POINTER_REG) and
+        (taicpu(p).oper[1]^.ref^.offset=4) and
+        (getsupreg(taicpu(p).oper[0]^.reg) in [0..7,15]) then
+        begin
+          hp := taicpu.op_regset(A_POP, R_INTREGISTER, R_SUBWHOLE, [getsupreg(taicpu(p).oper[0]^.reg)]);
+          asml.InsertBefore(hp, p);
+          asml.Remove(p);
+          p.Free;
+          p:=hp;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, A_MOV, [C_None], [PF_None]) and
+        (taicpu(p).oper[1]^.typ=top_const) and
+        (taicpu(p).oper[1]^.val >= 0) and
+        (taicpu(p).oper[1]^.val < 256) and
+        (not RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
+        begin
+          asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
+          asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,p), p);
+          IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
+          taicpu(p).oppostfix:=PF_S;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, A_MVN, [C_None], [PF_None]) and
+        (taicpu(p).oper[1]^.typ=top_reg) and
+        (not RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
+        begin
+          asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
+          asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,p), p);
+          IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
+          taicpu(p).oppostfix:=PF_S;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, [A_ADD,A_SUB], [C_None], [PF_None]) and
+        (taicpu(p).ops = 3) and
+        MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[1]^) and
+        (not MatchOperand(taicpu(p).oper[0]^, NR_STACK_POINTER_REG)) and
+        (taicpu(p).oper[2]^.typ=top_const) and
+        (taicpu(p).oper[2]^.val >= 0) and
+        (taicpu(p).oper[2]^.val < 256) and
+        (not RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
+        begin
+          asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
+          asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,p), p);
+          IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
+          taicpu(p).loadconst(1,taicpu(p).oper[2]^.val);
+          taicpu(p).oppostfix:=PF_S;
+          taicpu(p).ops := 2;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, [A_AND,A_ORR,A_EOR,A_LSL,A_LSR,A_ASR,A_ROR], [C_None], [PF_None,PF_S]) and
+        (taicpu(p).ops = 3) and
+        MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[1]^) and
+        (taicpu(p).oper[2]^.typ=top_reg) and
+        (not RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
+        begin
+          asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
+          asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,p), p);
+          IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
+          taicpu(p).ops := 2;
+          taicpu(p).loadreg(1,taicpu(p).oper[2]^.reg);
+          taicpu(p).oppostfix:=PF_S;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, [A_AND,A_ORR,A_EOR], [], [PF_None,PF_S]) and
+        (taicpu(p).ops = 3) and
+        MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[2]^) and
+        (not RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
+        begin
+          asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
+          asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,p), p);
+          IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
+          taicpu(p).oppostfix:=PF_S;
+          taicpu(p).ops := 2;
+          result:=true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, [A_AND], [], [PF_None]) and
+        (taicpu(p).ops = 2) and
+        (taicpu(p).oper[1]^.typ=top_const) and
+        ((taicpu(p).oper[1]^.val=255) or
+         (taicpu(p).oper[1]^.val=65535)) then
+        begin
+          if taicpu(p).oper[1]^.val=255 then
+            taicpu(p).opcode:=A_UXTB
+          else
+            taicpu(p).opcode:=A_UXTH;
+
+          taicpu(p).loadreg(1, taicpu(p).oper[0]^.reg);
+
+          result := true;
+        end
+      else if (p.typ=ait_instruction) and
+        MatchInstruction(p, [A_AND], [], [PF_None]) and
+        (taicpu(p).ops = 3) and
+        (taicpu(p).oper[2]^.typ=top_const) and
+        ((taicpu(p).oper[2]^.val=255) or
+         (taicpu(p).oper[2]^.val=65535)) then
+        begin
+          if taicpu(p).oper[2]^.val=255 then
+            taicpu(p).opcode:=A_UXTB
+          else
+            taicpu(p).opcode:=A_UXTH;
+
+          taicpu(p).ops:=2;
+
+          result := true;
+        end
+      {else if (p.typ=ait_instruction) and
+        MatchInstruction(p, [A_CMP], [C_None], [PF_None]) and
+        (taicpu(p).oper[1]^.typ=top_const) and
+        (taicpu(p).oper[1]^.val=0) and
+        GetNextInstruction(p,hp1) and
+        (taicpu(hp1).opcode=A_B) and
+        (taicpu(hp1).condition in [C_EQ,C_NE]) then
+        begin
+          if taicpu(hp1).condition = C_EQ then
+            hp2:=taicpu.op_reg_ref(A_CBZ, taicpu(p).oper[0]^.reg, taicpu(hp1).oper[0]^.ref^)
+          else
+            hp2:=taicpu.op_reg_ref(A_CBNZ, taicpu(p).oper[0]^.reg, taicpu(hp1).oper[0]^.ref^);
+
+          taicpu(hp2).is_jmp := true;
+
+          asml.InsertAfter(hp2, hp1);
+
+          asml.Remove(hp1);
+          hp1.Free;
+          asml.Remove(p);
+          p.Free;
+
+          p := hp2;
+
+          result := true;
+        end}
+      else
+        Result := inherited PeepHoleOptPass1Cpu(p);
+    end;
+
   procedure TCpuThumb2AsmOptimizer.PeepHoleOptPass2;
+    var
+      p,hp1,hp2: tai;
+      l,l2 : longint;
+      condition : tasmcond;
+      hp3: tai;
+      WasLast: boolean;
+      { UsedRegs, TmpUsedRegs: TRegSet; }
+
     begin
-      { TODO: Add optimizer code }
+      p := BlockStart;
+      { UsedRegs := []; }
+      while (p <> BlockEnd) Do
+        begin
+          { UpdateUsedRegs(UsedRegs, tai(p.next)); }
+          case p.Typ Of
+            Ait_Instruction:
+              begin
+                case taicpu(p).opcode Of
+                  A_B:
+                    if taicpu(p).condition<>C_None then
+                      begin
+                         { check for
+                                Bxx   xxx
+                                <several instructions>
+                             xxx:
+                         }
+                         l:=0;
+                         GetNextInstruction(p, hp1);
+                         while assigned(hp1) and
+                           (l<=4) and
+                           CanBeCond(hp1) and
+                           { stop on labels }
+                           not(hp1.typ=ait_label) do
+                           begin
+                              inc(l);
+                              if MustBeLast(hp1) then
+                                begin
+                                  //hp1:=nil;
+                                  GetNextInstruction(hp1,hp1);
+                                  break;
+                                end
+                              else
+                                GetNextInstruction(hp1,hp1);
+                           end;
+                         if assigned(hp1) then
+                           begin
+                              if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
+                                begin
+                                  if (l<=4) and (l>0) then
+                                    begin
+                                      condition:=inverse_cond(taicpu(p).condition);
+                                      hp2:=p;
+                                      GetNextInstruction(p,hp1);
+                                      p:=hp1;
+                                      repeat
+                                        if hp1.typ=ait_instruction then
+                                          taicpu(hp1).condition:=condition;
+                                        if MustBeLast(hp1) then
+                                          begin
+                                            GetNextInstruction(hp1,hp1);
+                                            break;
+                                          end
+                                        else
+                                          GetNextInstruction(hp1,hp1);
+                                      until not(assigned(hp1)) or
+                                        not(CanBeCond(hp1)) or
+                                        (hp1.typ=ait_label);
+                                      { wait with removing else GetNextInstruction could
+                                        ignore the label if it was the only usage in the
+                                        jump moved away }
+
+                                      asml.InsertAfter(tai_comment.create(strpnew('Collapsed')), hp2);
+
+                                      DecrementPreceedingIT(asml, hp2);
+
+                                      case l of
+                                        1: asml.InsertAfter(taicpu.op_cond(A_IT,condition), hp2);
+                                        2: asml.InsertAfter(taicpu.op_cond(A_ITT,condition), hp2);
+                                        3: asml.InsertAfter(taicpu.op_cond(A_ITTT,condition), hp2);
+                                        4: asml.InsertAfter(taicpu.op_cond(A_ITTTT,condition), hp2);
+                                      end;
+
+                                      tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
+                                      asml.remove(hp2);
+                                      hp2.free;
+                                      continue;
+                                    end;
+                                end;
+                           end;
+                      end;
+                end;
+              end;
+          end;
+          p := tai(p.next)
+        end;
     end;
 
 begin

compiler/arm/armatt.inc

@@ -50,6 +50,7 @@
 'mcr',
 'mla',
 'mov',
+'mrc',
 'mrs',
 'msr',
 'mnf',
@@ -206,6 +207,10 @@
 'sel',
 'setend',
 'sev',
+'asr',
+'lsr',
+'lsl',
+'ror',
 'shadd16',
 'shadd8',
 'shasx',
@@ -270,12 +275,8 @@
 'wfe',
 'wfi',
 'yield',
-'asr',
-'lsr',
-'lsl',
 'pop',
 'push',
-'ror',
 'sdiv',
 'udiv',
 'movt',
@@ -295,5 +296,36 @@
 'itett',
 'itttt',
 'tbb',
-'tbh'
+'tbh',
+'movw',
+'cbz',
+'cbnz',
+'vabs',
+'vadd',
+'vcmp',
+'vcmpe',
+'vcvt',
+'vdiv',
+'vldm',
+'vldr',
+'vmov',
+'vmrs',
+'vmsr',
+'vmul',
+'vmla',
+'vmls',
+'vnmla',
+'vnmls',
+'vfma',
+'vfms',
+'vfnma',
+'vfnms',
+'vneg',
+'vnmul',
+'vpop',
+'vpush',
+'vsqrt',
+'vstm',
+'vstr',
+'vsub'
 );

compiler/arm/armatts.inc

@@ -295,5 +295,37 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufNONE
 );

compiler/arm/armins.dat

@@ -235,7 +235,7 @@ reg32,imm8,fpureg        \xF0\x02\x01                   FPA
 [LOGcc]
 
 [MCR]
-reg32,mem32         \320\301\1\x13\110            ARM7
+; reg32,mem32         \320\301\1\x13\110            ARM7
 
 [MLAcc]
 reg32,reg32,reg32,reg32  \x15\x00\x20\x90               ARM7
@@ -247,7 +247,7 @@ reg32,reg32,reg32,reg32  \x15\x00\x20\x90               ARM7
 ; reg32,reg32,imm          \xA\x1\xA0                     ARM7
 ; reg32,imm                \xB\x3\xA0                     ARM7
 
-; [MRC]
+[MRC]
 ; reg32,reg32         \321\301\1\x13\110                  ARM7
 
 [MRScc]
@@ -618,6 +618,14 @@ reg32,reg32,reg32,reg32  \x16\x00\x80\x90		 ARM7
 
 [SEVcc]
 
+[ASRcc]
+
+[LSRcc]
+
+[LSLcc]
+
+[RORcc]
+
 [SHADD16cc]
 [SHADD8cc]
 [SHASXcc]
@@ -702,18 +710,10 @@ reg32,reg32,reg32,reg32  \x16\x00\x80\x90		 ARM7
 
 ; Thumb-2
 
-[ASRcc]
-
-[LSRcc]
-
-[LSLcc]
-
 [POP]
 
 [PUSH]
 
-[RORcc]
-
 [SDIVcc]
 
 [UDIVcc]
@@ -752,3 +752,38 @@ reg32,reg32,reg32,reg32  \x16\x00\x80\x90		 ARM7
 
 [TBB]
 [TBH]
+
+[MOVW]
+
+[CBZ]
+[CBNZ]
+
+; FPv4-s16 - ARMv7M floating point
+[VABS]
+[VADD]
+[VCMP]
+[VCMPE]
+[VCVT]
+[VDIV]
+[VLDM]
+[VLDR]
+[VMOV]
+[VMRS]
+[VMSR]
+[VMUL]
+[VMLA]
+[VMLS]
+[VNMLA]
+[VNMLS]
+[VFMA]
+[VFMS]
+[VFNMA]
+[VFNMS]
+[VNEG]
+[VNMUL]
+[VPOP]
+[VPUSH]
+[VSQRT]
+[VSTM]
+[VSTR]
+[VSUB]

compiler/arm/armnop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-106;
+105;

compiler/arm/armop.inc

@@ -50,6 +50,7 @@ A_LOG,
 A_MCR,
 A_MLA,
 A_MOV,
+A_MRC,
 A_MRS,
 A_MSR,
 A_MNF,
@@ -206,6 +207,10 @@ A_SBFX,
 A_SEL,
 A_SETEND,
 A_SEV,
+A_ASR,
+A_LSR,
+A_LSL,
+A_ROR,
 A_SHADD16,
 A_SHADD8,
 A_SHASX,
@@ -270,12 +275,8 @@ A_UXTH,
 A_WFE,
 A_WFI,
 A_YIELD,
-A_ASR,
-A_LSR,
-A_LSL,
 A_POP,
 A_PUSH,
-A_ROR,
 A_SDIV,
 A_UDIV,
 A_MOVT,
@@ -295,5 +296,36 @@ A_ITTET,
 A_ITETT,
 A_ITTTT,
 A_TBB,
-A_TBH
+A_TBH,
+A_MOVW,
+A_CBZ,
+A_CBNZ,
+A_VABS,
+A_VADD,
+A_VCMP,
+A_VCMPE,
+A_VCVT,
+A_VDIV,
+A_VLDM,
+A_VLDR,
+A_VMOV,
+A_VMRS,
+A_VMSR,
+A_VMUL,
+A_VMLA,
+A_VMLS,
+A_VNMLA,
+A_VNMLS,
+A_VFMA,
+A_VFMS,
+A_VFNMA,
+A_VFNMS,
+A_VNEG,
+A_VNMUL,
+A_VPOP,
+A_VPUSH,
+A_VSQRT,
+A_VSTM,
+A_VSTR,
+A_VSUB
 );

compiler/arm/armreg.dat

@@ -109,4 +109,24 @@ D31,$04,$07,$1F,d31,0,0
 ; special registers
 CPSR,$05,$00,$00,cpsr,0,0
 FPSCR,$05,$00,$01,fpscr,0,0
-SPSR,$05,$00,$02,spsr,0,0
+SPSR,$05,$00,$02,spsr,0,0
+APSR_nzcv,$05,$00,$03,apsr_nzcv,0,0
+; coprocessor registers
+CR0,$05,$00,$04,cr0,0,0
+CR1,$05,$00,$05,cr1,0,0
+CR2,$05,$00,$06,cr2,0,0
+CR3,$05,$00,$07,cr3,0,0
+CR4,$05,$00,$08,cr4,0,0
+CR5,$05,$00,$09,cr5,0,0
+CR6,$05,$00,$0A,cr6,0,0
+CR7,$05,$00,$0B,cr7,0,0
+CR8,$05,$00,$0C,cr8,0,0
+CR9,$05,$00,$0D,cr9,0,0
+CR10,$05,$00,$0E,cr10,0,0
+CR11,$05,$00,$0F,cr11,0,0
+CR12,$05,$00,$10,cr12,0,0
+CR13,$05,$00,$11,cr13,0,0
+CR14,$05,$00,$12,cr14,0,0
+CR15,$05,$00,$13,cr15,0,0
+; coprocessors
+p15,$05,$00,$14,p15,0,0

compiler/arm/armtab.inc

@@ -385,13 +385,6 @@
     code    : #240#2#1;
     flags   : if_fpa
   ),
-  (
-    opcode  : A_MCR;
-    ops     : 2;
-    optypes : (ot_reg32,ot_memory or ot_bits32,ot_none,ot_none);
-    code    : #208#193#1#19#72;
-    flags   : if_arm7
-  ),
   (
     opcode  : A_MLA;
     ops     : 4;

compiler/arm/cgcpu.pas

@@ -161,6 +161,12 @@ unit cgcpu;
         procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
 
         function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference; override;
+
+        procedure a_loadmm_reg_reg(list: TAsmList; fromsize, tosize : tcgsize;reg1, reg2: tregister;shuffle : pmmshuffle); override;
+        procedure a_loadmm_ref_reg(list: TAsmList; fromsize, tosize : tcgsize;const ref: treference; reg: tregister;shuffle : pmmshuffle); override;
+        procedure a_loadmm_reg_ref(list: TAsmList; fromsize, tosize : tcgsize;reg: tregister; const ref: treference;shuffle : pmmshuffle); override;
+        procedure a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize : tcgsize;intreg, mmreg: tregister; shuffle: pmmshuffle); override;
+        procedure a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize : tcgsize;mmreg, intreg: tregister; shuffle : pmmshuffle); override;
       end;
 
       tthumb2cg64farm = class(tcg64farm)
@@ -3120,10 +3126,17 @@ unit cgcpu;
           rg[R_INTREGISTER]:=trgintcputhumb2.create(R_INTREGISTER,R_SUBWHOLE,
               [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
                RS_R10,RS_R12,RS_R14],first_int_imreg,[]);
-        rg[R_FPUREGISTER]:=trgcputhumb2.create(R_FPUREGISTER,R_SUBNONE,
+        rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
             [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
-        rg[R_MMREGISTER]:=trgcputhumb2.create(R_MMREGISTER,R_SUBNONE,
-            [RS_S0,RS_S1,RS_R2,RS_R3,RS_R4,RS_S31],first_mm_imreg,[]);
+
+        if current_settings.fputype=fpu_fpv4_s16 then
+          rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
+              [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,
+               RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15
+              ],first_mm_imreg,[])
+        else
+          rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
+              [RS_S0,RS_S1,RS_R2,RS_R3,RS_R4,RS_S31],first_mm_imreg,[]);
       end;
 
 
@@ -3959,6 +3972,127 @@ unit cgcpu;
         Result := ref;
       end;
 
+     procedure Tthumb2cgarm.a_loadmm_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister; shuffle: pmmshuffle);
+      var
+        instr: taicpu;
+      begin
+        if (fromsize=OS_F32) and
+          (tosize=OS_F32) then
+          begin
+            instr:=setoppostfix(taicpu.op_reg_reg(A_VMOV,reg2,reg1), PF_F32);
+            list.Concat(instr);
+            add_move_instruction(instr);
+          end
+        else if (fromsize=OS_F64) and
+          (tosize=OS_F64) then
+          begin
+            //list.Concat(setoppostfix(taicpu.op_reg_reg(A_VMOV,tregister(longint(reg2)+1),tregister(longint(reg1)+1)), PF_F32));
+            //list.Concat(setoppostfix(taicpu.op_reg_reg(A_VMOV,reg2,reg1), PF_F32));
+          end
+        else if (fromsize=OS_F32) and
+          (tosize=OS_F64) then
+          //list.Concat(setoppostfix(taicpu.op_reg_reg(A_VCVT,reg2,reg1), PF_F32))
+          begin
+            //list.concat(nil);
+          end;
+      end;
+
+     procedure Tthumb2cgarm.a_loadmm_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister; shuffle: pmmshuffle);
+      var
+        href: treference;
+        tmpreg: TRegister;
+        so: tshifterop;
+      begin
+        href:=ref;
+
+        if (href.base<>NR_NO) and
+          (href.index<>NR_NO) then
+          begin
+            tmpreg:=getintregister(list,OS_INT);
+            if href.shiftmode<>SM_None then
+              begin
+                so.rs:=href.index;
+                so.shiftimm:=href.shiftimm;
+                so.shiftmode:=href.shiftmode;
+                list.concat(taicpu.op_reg_reg_shifterop(A_ADD,tmpreg,href.base,so));
+              end
+            else
+              a_op_reg_reg_reg(list,OP_ADD,OS_INT,href.index,href.base,tmpreg);
+
+            reference_reset_base(href,tmpreg,href.offset,0);
+          end;
+
+        if assigned(href.symbol) then
+          begin
+            tmpreg:=getintregister(list,OS_INT);
+            a_loadaddr_ref_reg(list,href,tmpreg);
+
+            reference_reset_base(href,tmpreg,0,0);
+          end;
+
+        if fromsize=OS_F32 then
+          list.Concat(setoppostfix(taicpu.op_reg_ref(A_VLDR,reg,href), PF_F32))
+        else
+          list.Concat(setoppostfix(taicpu.op_reg_ref(A_VLDR,reg,href), PF_F64));
+      end;
+
+     procedure Tthumb2cgarm.a_loadmm_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference; shuffle: pmmshuffle);
+      var
+        href: treference;
+        so: tshifterop;
+        tmpreg: TRegister;
+      begin
+        href:=ref;
+
+        if (href.base<>NR_NO) and
+          (href.index<>NR_NO) then
+          begin
+            tmpreg:=getintregister(list,OS_INT);
+            if href.shiftmode<>SM_None then
+              begin
+                so.rs:=href.index;
+                so.shiftimm:=href.shiftimm;
+                so.shiftmode:=href.shiftmode;
+                list.concat(taicpu.op_reg_reg_shifterop(A_ADD,tmpreg,href.base,so));
+              end
+            else
+              a_op_reg_reg_reg(list,OP_ADD,OS_INT,href.index,href.base,tmpreg);
+
+            reference_reset_base(href,tmpreg,href.offset,0);
+          end;
+
+        if assigned(href.symbol) then
+          begin
+            tmpreg:=getintregister(list,OS_INT);
+            a_loadaddr_ref_reg(list,href,tmpreg);
+
+            reference_reset_base(href,tmpreg,0,0);
+          end;
+
+        if fromsize=OS_F32 then
+          list.Concat(setoppostfix(taicpu.op_reg_ref(A_VSTR,reg,href), PF_32))
+        else
+          list.Concat(setoppostfix(taicpu.op_reg_ref(A_VSTR,reg,href), PF_64));
+      end;
+
+     procedure Tthumb2cgarm.a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize: tcgsize; intreg, mmreg: tregister; shuffle: pmmshuffle);
+      begin
+        if //(shuffle=nil) and
+          (tosize=OS_F32) then
+          list.Concat(taicpu.op_reg_reg(A_VMOV,mmreg,intreg))
+        else
+          internalerror(2012100813);
+      end;
+
+     procedure Tthumb2cgarm.a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize: tcgsize; mmreg, intreg: tregister; shuffle: pmmshuffle);
+      begin
+        if //(shuffle=nil) and
+          (fromsize=OS_F32) then
+          list.Concat(taicpu.op_reg_reg(A_VMOV,intreg,mmreg))
+        else
+          internalerror(2012100814);
+      end;
+
 
     procedure tthumb2cg64farm.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
       var tmpreg: tregister;

compiler/arm/cpubase.pas

@@ -48,7 +48,7 @@ unit cpubase;
       TAsmOp= {$i armop.inc}
       {This is a bit of a hack, because there are more than 256 ARM Assembly Ops
        But FPC currently can't handle more than 256 elements in a set.}
-      TCommonAsmOps = Set of A_None .. A_UQSADA8;
+      TCommonAsmOps = Set of A_None .. A_UQASX;
 
       { This should define the array of instructions as string }
       op2strtable=array[tasmop] of string[11];
@@ -139,7 +139,11 @@ unit cpubase;
         { multiple load/store vfp address modes }
         PF_IAD,PF_DBD,PF_FDD,PF_EAD,
         PF_IAS,PF_DBS,PF_FDS,PF_EAS,
-        PF_IAX,PF_DBX,PF_FDX,PF_EAX
+        PF_IAX,PF_DBX,PF_FDX,PF_EAX,
+        { FPv4 postfixes }
+        PF_32,PF_64,PF_F32,PF_F64,
+        PF_F32S32,PF_F32U32,
+        PF_S32F32,PF_U32F32
       );
 
       TOpPostfixes = set of TOpPostfix;
@@ -152,14 +156,17 @@ unit cpubase;
         PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,
         PF_S,PF_D,PF_E,PF_None,PF_None);
 
-      oppostfix2str : array[TOpPostfix] of string[3] = ('',
+      oppostfix2str : array[TOpPostfix] of string[8] = ('',
         's',
         'd','e','p','ep',
         'b','sb','bt','h','sh','t',
         'ia','ib','da','db','fd','fa','ed','ea',
         'iad','dbd','fdd','ead',
         'ias','dbs','fds','eas',
-        'iax','dbx','fdx','eax');
+        'iax','dbx','fdx','eax',
+        '.32','.64','.f32','.f64',
+        '.f32.s32','.f32.u32',
+        '.s32.f32','.u32.f32');
 
       roundingmode2str : array[TRoundingMode] of string[1] = ('',
         'p','m','z');
@@ -223,7 +230,7 @@ unit cpubase;
 *****************************************************************************}
 
     const
-      max_operands = 4;
+      max_operands = 6;
 
       maxintregs = 15;
       maxfpuregs = 8;
@@ -361,6 +368,9 @@ unit cpubase;
     function split_into_shifter_const(value : aint;var imm1: dword; var imm2: dword):boolean;
     function dwarf_reg(r:tregister):shortint;
 
+    function IsIT(op: TAsmOp) : boolean;
+    function GetITLevels(op: TAsmOp) : longint;
+
   implementation
 
     uses
@@ -368,7 +378,7 @@ unit cpubase;
 
 
     const
-      std_regname_table : array[tregisterindex] of string[7] = (
+      std_regname_table : array[tregisterindex] of string[10] = (
         {$i rarmstd.inc}
       );
 
@@ -606,4 +616,35 @@ unit cpubase;
         result:=RS_R0;
     end;
 
+    function IsIT(op: TAsmOp) : boolean;
+      begin
+        case op of
+          A_IT,
+          A_ITE, A_ITT,
+          A_ITEE, A_ITTE, A_ITET, A_ITTT,
+          A_ITEEE, A_ITTEE, A_ITETE, A_ITTTE,
+          A_ITEET, A_ITTET, A_ITETT, A_ITTTT:
+            result:=true;
+        else
+          result:=false;
+        end;
+      end;
+
+    function GetITLevels(op: TAsmOp) : longint;
+      begin
+        case op of
+          A_IT:
+            result:=1;
+          A_ITE, A_ITT:
+            result:=2;
+          A_ITEE, A_ITTE, A_ITET, A_ITTT:
+            result:=3;
+          A_ITEEE, A_ITTEE, A_ITETE, A_ITTTE,
+          A_ITEET, A_ITTET, A_ITETT, A_ITTTT:
+            result:=4;
+        else
+          result:=0;
+        end;
+      end;
+
 end.

compiler/arm/cpuinfo.pas

@@ -65,7 +65,8 @@ Type
       fpu_fpa11,
       fpu_vfpv2,
       fpu_vfpv3,
-      fpu_vfpv3_d16
+      fpu_vfpv3_d16,
+      fpu_fpv4_s16
      );
 
    tcontrollertype =
@@ -89,9 +90,38 @@ Type
       ct_at91sam7xc256,
 		
       { STMicroelectronics }
-      ct_stm32f103rb,
-      ct_stm32f103re,
-      ct_stm32f103c4t,
+      ct_stm32f100x4, // LD&MD value line, 4=16,6=32,8=64,b=128
+      ct_stm32f100x6,
+      ct_stm32f100x8,
+      ct_stm32f100xB,
+      ct_stm32f100xC, // HD value line, r=512,d=384,c=256
+      ct_stm32f100xD,
+      ct_stm32f100xE,
+      ct_stm32f101x4, // LD Access line, 4=16,6=32
+      ct_stm32f101x6,
+      ct_stm32f101x8, // MD Access line, 8=64,B=128
+      ct_stm32f101xB,
+      ct_stm32f101xC, // HD Access line, C=256,D=384,E=512
+      ct_stm32f101xD,
+      ct_stm32f101xE,
+      ct_stm32f101xF, // XL Access line, F=768,G=1M
+      ct_stm32f101xG,
+      ct_stm32f102x4, // LD usb access line, 4=16,6=32
+      ct_stm32f102x6,
+      ct_stm32f102x8, // MD usb access line, 8=64,B=128
+      ct_stm32f102xB,
+      ct_stm32f103x4, // LD performance line, 4=16,6=32
+      ct_stm32f103x6,
+      ct_stm32f103x8, // MD performance line, 8=64,B=128
+      ct_stm32f103xB,
+      ct_stm32f103xC, // HD performance line, C=256,D=384,E=512
+      ct_stm32f103xD,
+      ct_stm32f103xE,
+      ct_stm32f103xF, // XL performance line, F=768,G=1M
+      ct_stm32f103xG,
+      ct_stm32f107x8, // MD and HD connectivity line, 8=64,B=128,C=256
+      ct_stm32f107xB,
+      ct_stm32f107xC,
 
       { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
       ct_lm3s1110,
@@ -227,7 +257,8 @@ Const
      'FPA11',
      'VFPV2',
      'VFPV3',
-     'VFPV3_D16'
+     'VFPV3_D16',
+     'FPV4_S16'
    );
 
 
@@ -239,7 +270,6 @@ Const
    ((
    	controllertypestr:'';
         controllerunitstr:'';
-        interruptvectors:0;
         flashbase:0;
         flashsize:0;
         srambase:0;
@@ -249,8 +279,7 @@ Const
         (
     	controllertypestr:'LPC2114';
         controllerunitstr:'LPC21x4';
-        interruptvectors:8;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$40000000;
         sramsize:$00004000
@@ -259,8 +288,7 @@ Const
         (
     	controllertypestr:'LPC2124';
         controllerunitstr:'LPC21x4';
-        interruptvectors:8;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$40000000;
         sramsize:$00004000
@@ -269,8 +297,7 @@ Const
         (
     	controllertypestr:'LPC2194';
         controllerunitstr:'LPC21x4';
-        interruptvectors:8;
-    	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$40000000;
         sramsize:$00004000
@@ -279,8 +306,7 @@ Const
         (
     	controllertypestr:'LPC1754';
         controllerunitstr:'LPC1754';
-        interruptvectors:12;
-    	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$10000000;
         sramsize:$00004000
@@ -289,8 +315,7 @@ Const
         (
     	controllertypestr:'LPC1756';
         controllerunitstr:'LPC1756';
-        interruptvectors:12;
-    	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$10000000;
         sramsize:$00004000
@@ -299,8 +324,7 @@ Const
         (
     	controllertypestr:'LPC1758';
         controllerunitstr:'LPC1758';
-        interruptvectors:12;
-    	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00080000;
         srambase:$10000000;
         sramsize:$00008000
@@ -309,8 +333,7 @@ Const
         (
     	controllertypestr:'LPC1764';
         controllerunitstr:'LPC1764';
-        interruptvectors:12;
-    	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$10000000;
         sramsize:$00004000
@@ -319,8 +342,7 @@ Const
         (
     	controllertypestr:'LPC1766';
         controllerunitstr:'LPC1766';
-        interruptvectors:12;
-    	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$10000000;
         sramsize:$00008000
@@ -329,8 +351,7 @@ Const
         (
     	controllertypestr:'LPC1768';
         controllerunitstr:'LPC1768';
-        interruptvectors:12;
-    	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00080000;
         srambase:$10000000;
         sramsize:$00008000
@@ -339,7 +360,6 @@ Const
         (
     	controllertypestr:'AT91SAM7S256';
         controllerunitstr:'AT91SAM7x256';
-        interruptvectors:8;
         flashbase:$00000000;
         flashsize:$00040000;
         srambase:$00200000;
@@ -349,7 +369,6 @@ Const
         (
     	controllertypestr:'AT91SAM7SE256';
         controllerunitstr:'AT91SAM7x256';
-        interruptvectors:8;
         flashbase:$00000000;
         flashsize:$00040000;
         srambase:$00200000;
@@ -359,7 +378,6 @@ Const
         (
     	controllertypestr:'AT91SAM7X256';
         controllerunitstr:'AT91SAM7x256';
-        interruptvectors:8;
         flashbase:$00000000;
         flashsize:$00040000;
         srambase:$00200000;
@@ -369,51 +387,52 @@ Const
         (
     	controllertypestr:'AT91SAM7XC256';
         controllerunitstr:'AT91SAM7x256';
-        interruptvectors:8;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$00200000;
         sramsize:$00010000
         ),
 
-      	// ct_stm32f103rb,
-        (
-    	controllertypestr:'STM32F103RB';
-        controllerunitstr:'STM32F103';
-        interruptvectors:12;
-        flashbase:$08000000;
-        flashsize:$00020000;
-        srambase:$20000000;
-        sramsize:$00005000
-        ),
-        // ct_stm32f103re,
-        (
-    	controllertypestr:'STM32F103RE';
-        controllerunitstr:'STM32F103';
-        interruptvectors:12;
-        flashbase:$08000000;
-        flashsize:$00080000;
-        srambase:$20000000;
-        sramsize:$00010000
-        ),
-        // ct_stm32f103re,
-        (
-    	controllertypestr:'STM32F103C4T';
-        controllerunitstr:'STM32F103';
-        interruptvectors:12;
-        flashbase:$08000000;
-        flashsize:$00004000;
-        srambase:$20000000;
-        sramsize:$00001800
-        ),
+      { STM32F1 series }
+      	(controllertypestr:'STM32F100X4';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
+        (controllertypestr:'STM32F100X6';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
+        (controllertypestr:'STM32F100X8';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
+        (controllertypestr:'STM32F100XB';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00002000),
+        (controllertypestr:'STM32F100XC';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00006000),
+        (controllertypestr:'STM32F100XD';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00008000),
+        (controllertypestr:'STM32F100XE';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00008000),
+        (controllertypestr:'STM32F101X4';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
+        (controllertypestr:'STM32F101X6';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800),
+        (controllertypestr:'STM32F101X8';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800),
+        (controllertypestr:'STM32F101XB';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000),
+        (controllertypestr:'STM32F101XC';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00008000),
+        (controllertypestr:'STM32F101XD';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$0000C000),
+        (controllertypestr:'STM32F101XE';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$0000C000),
+        (controllertypestr:'STM32F101XF';     controllerunitstr:'STM32F10X_XL';     flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00014000),
+        (controllertypestr:'STM32F101XG';     controllerunitstr:'STM32F10X_XL';     flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00014000),
+        (controllertypestr:'STM32F102X4';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
+        (controllertypestr:'STM32F102X6';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800),
+        (controllertypestr:'STM32F102X8';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800),
+        (controllertypestr:'STM32F102XB';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000),
+        (controllertypestr:'STM32F103X4';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
+        (controllertypestr:'STM32F103X6';     controllerunitstr:'STM32F10X_LD';     flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00002800),
+        (controllertypestr:'STM32F103X8';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00005000),
+        (controllertypestr:'STM32F103XB';     controllerunitstr:'STM32F10X_MD';     flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00005000),
+        (controllertypestr:'STM32F103XC';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$0000C000),
+        (controllertypestr:'STM32F103XD';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00010000),
+        (controllertypestr:'STM32F103XE';     controllerunitstr:'STM32F10X_HD';     flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000),
+        (controllertypestr:'STM32F103XF';     controllerunitstr:'STM32F10X_XL';     flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00018000),
+        (controllertypestr:'STM32F103XG';     controllerunitstr:'STM32F10X_XL';     flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00018000),
+        (controllertypestr:'STM32F107X8';     controllerunitstr:'STM32F10X_CONN';   flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00010000),
+        (controllertypestr:'STM32F107XB';     controllerunitstr:'STM32F10X_CONN';   flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
+        (controllertypestr:'STM32F107XC';     controllerunitstr:'STM32F10X_CONN';   flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
 
       { TI - 64 K Flash, 16 K SRAM Devices }
       	// ct_lm3s1110,
         (
     	controllertypestr:'LM3S1110';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -422,8 +441,7 @@ Const
         (
     	controllertypestr:'LM3S1133';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -432,8 +450,7 @@ Const
         (
     	controllertypestr:'LM3S1138';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -442,8 +459,7 @@ Const
         (
     	controllertypestr:'LM3S1150';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -452,8 +468,7 @@ Const
         (
     	controllertypestr:'LM3S1162';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -462,8 +477,7 @@ Const
         (
     	controllertypestr:'LM3S1165';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -472,8 +486,7 @@ Const
         (
     	controllertypestr:'LM3S1166';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -482,8 +495,7 @@ Const
         (
     	controllertypestr:'LM3S2110';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -492,8 +504,7 @@ Const
         (
     	controllertypestr:'LM3S2139';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -502,8 +513,7 @@ Const
         (
     	controllertypestr:'LM3S6100';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -512,8 +522,7 @@ Const
         (
     	controllertypestr:'LM3S6110';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00010000;
         srambase:$20000000;
         sramsize:$00004000
@@ -524,8 +533,7 @@ Const
         (
     	controllertypestr:'LM3S1601';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -534,8 +542,7 @@ Const
         (
     	controllertypestr:'LM3S1608';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -544,8 +551,7 @@ Const
         (
     	controllertypestr:'LM3S1620';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -554,8 +560,7 @@ Const
         (
     	controllertypestr:'LM3S1635';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -564,8 +569,7 @@ Const
         (
     	controllertypestr:'LM3S1636';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -574,8 +578,7 @@ Const
         (
     	controllertypestr:'LM3S1637';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -584,8 +587,7 @@ Const
         (
     	controllertypestr:'LM3S1651';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -594,8 +596,7 @@ Const
         (
     	controllertypestr:'LM3S2601';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -604,8 +605,7 @@ Const
         (
     	controllertypestr:'LM3S2608';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -614,8 +614,7 @@ Const
         (
     	controllertypestr:'LM3S2620';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -624,8 +623,7 @@ Const
         (
     	controllertypestr:'LM3S2637';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -634,8 +632,7 @@ Const
         (
     	controllertypestr:'LM3S2651';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -644,8 +641,7 @@ Const
         (
     	controllertypestr:'LM3S6610';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -654,8 +650,7 @@ Const
         (
     	controllertypestr:'LM3S6611';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -664,8 +659,7 @@ Const
         (
     	controllertypestr:'LM3S6618';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -674,8 +668,7 @@ Const
         (
     	controllertypestr:'LM3S6633';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -684,8 +677,7 @@ Const
         (
     	controllertypestr:'LM3S6637';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -694,8 +686,7 @@ Const
         (
     	controllertypestr:'LM3S8630';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00020000;
         srambase:$20000000;
         sramsize:$00008000
@@ -706,8 +697,7 @@ Const
         (
     	controllertypestr:'LM3S1911';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -716,8 +706,7 @@ Const
         (
     	controllertypestr:'LM3S1918';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -726,8 +715,7 @@ Const
         (
     	controllertypestr:'LM3S1937';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -736,8 +724,7 @@ Const
         (
     	controllertypestr:'LM3S1958';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -746,8 +733,7 @@ Const
         (
     	controllertypestr:'LM3S1960';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -756,8 +742,7 @@ Const
         (
     	controllertypestr:'LM3S1968';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -766,8 +751,7 @@ Const
         (
     	controllertypestr:'LM3S1969';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -776,8 +760,7 @@ Const
         (
     	controllertypestr:'LM3S2911';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -786,8 +769,7 @@ Const
         (
     	controllertypestr:'LM3S2918';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -796,8 +778,7 @@ Const
         (
     	controllertypestr:'LM3S2919';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -806,8 +787,7 @@ Const
         (
     	controllertypestr:'LM3S2939';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -816,8 +796,7 @@ Const
         (
     	controllertypestr:'LM3S2948';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -826,8 +805,7 @@ Const
         (
     	controllertypestr:'LM3S2950';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -836,8 +814,7 @@ Const
         (
     	controllertypestr:'LM3S2965';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -846,8 +823,7 @@ Const
         (
     	controllertypestr:'LM3S6911';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -856,8 +832,7 @@ Const
         (
     	controllertypestr:'LM3S6918';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -866,8 +841,7 @@ Const
         (
     	controllertypestr:'LM3S6938';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -876,8 +850,7 @@ Const
         (
     	controllertypestr:'LM3S6950';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -886,8 +859,7 @@ Const
         (
     	controllertypestr:'LM3S6952';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -896,8 +868,7 @@ Const
         (
     	controllertypestr:'LM3S6965';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -906,8 +877,7 @@ Const
         (
     	controllertypestr:'LM3S8930';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -916,8 +886,7 @@ Const
         (
     	controllertypestr:'LM3S8933';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -926,8 +895,7 @@ Const
         (
     	controllertypestr:'LM3S8938';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -936,8 +904,7 @@ Const
         (
     	controllertypestr:'LM3S8962';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -946,8 +913,7 @@ Const
         (
     	controllertypestr:'LM3S8970';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -956,8 +922,7 @@ Const
         (
     	controllertypestr:'LM3S8971';
         controllerunitstr:'LM3FURY';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -968,8 +933,7 @@ Const
         (
     	controllertypestr:'LM3S5951';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -978,8 +942,7 @@ Const
         (
     	controllertypestr:'LM3S5956';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -988,8 +951,7 @@ Const
         (
     	controllertypestr:'LM3S1B21';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -998,8 +960,7 @@ Const
         (
     	controllertypestr:'LM3S2B93';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -1008,8 +969,7 @@ Const
         (
     	controllertypestr:'LM3S5B91';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -1018,8 +978,7 @@ Const
         (
     	controllertypestr:'LM3S9B81';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -1028,8 +987,7 @@ Const
         (
     	controllertypestr:'LM3S9B90';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -1038,8 +996,7 @@ Const
         (
     	controllertypestr:'LM3S9B92';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -1048,8 +1005,7 @@ Const
         (
     	controllertypestr:'LM3S9B95';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -1058,8 +1014,7 @@ Const
         (
     	controllertypestr:'LM3S9B96';
         controllerunitstr:'LM3TEMPEST';
-        interruptvectors:72;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00040000;
         srambase:$20000000;
         sramsize:$00010000
@@ -1069,8 +1024,7 @@ Const
         (
     	controllertypestr:'SC32442B';
         controllerunitstr:'sc32442b';
-        interruptvectors:7;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00000000;
         srambase:$00000000;
         sramsize:$08000000
@@ -1080,15 +1034,14 @@ Const
         (
     	controllertypestr:'THUMB2_BARE';
         controllerunitstr:'THUMB2_BARE';
-        interruptvectors:128;
-	flashbase:$00000000;
+        flashbase:$00000000;
         flashsize:$00100000;
         srambase:$20000000;
         sramsize:$00100000
         )
     );
 
-   vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16];
+   vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16,fpu_fpv4_s16];
 
    { Supported optimizations, only used for information }
    supported_optimizerswitches = genericlevel1optimizerswitches+
@@ -1135,8 +1088,8 @@ Const
        { cpu_armv7    } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
        { cpu_armv7a   } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
        { cpu_armv7r   } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
-       { cpu_armv7m   } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV],
-       { cpu_armv7em  } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
+       { cpu_armv7m   } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV],
+       { cpu_armv7em  } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
      );
 
 Implementation

compiler/arm/cpupara.pas

@@ -124,7 +124,7 @@ unit cpupara;
                 getparaloc:=LOC_MMREGISTER
               else if (calloption in [pocall_cdecl,pocall_cppdecl,pocall_softfloat]) or
                  (cs_fp_emulation in current_settings.moduleswitches) or
-                 (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16]) then
+                 (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16,fpu_fpv4_s16]) then
                 { the ARM eabi also allows passing VFP values via VFP registers,
                   but Mac OS X doesn't seem to do that and linux only does it if
                   built with the "-mfloat-abi=hard" option }
@@ -608,7 +608,7 @@ unit cpupara;
               end
             else if (p.proccalloption in [pocall_softfloat]) or
                (cs_fp_emulation in current_settings.moduleswitches) or
-               (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16]) then
+               (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16,fpu_fpv4_s16]) then
               begin
                 case retcgsize of
                   OS_64,

compiler/arm/cpupi.pas

@@ -125,6 +125,14 @@ unit cpupi;
                 if r in regs then
                   inc(floatsavesize,8);
             end;
+          fpu_fpv4_s16:
+            begin
+              floatsavesize:=0;
+              regs:=cg.rg[R_MMREGISTER].used_in_proc-paramanager.get_volatile_registers_mm(pocall_stdcall);
+              for r:=RS_D0 to RS_D15 do
+                if r in regs then
+                  inc(floatsavesize,8);
+            end;
         end;
         floatsavesize:=align(floatsavesize,max(current_settings.alignment.localalignmin,4));
         result:=Align(tg.direction*tg.lasttemp,max(current_settings.alignment.localalignmin,4))+maxpushedparasize+aint(floatsavesize);

compiler/arm/itcpugas.pas

@@ -46,7 +46,7 @@ implementation
       cutils,verbose;
 
     const
-      gas_regname_table : array[tregisterindex] of string[7] = (
+      gas_regname_table : array[tregisterindex] of string[10] = (
         {$i rarmstd.inc}
       );
 

compiler/arm/narmadd.pas

@@ -35,6 +35,7 @@ interface
        public
           function pass_1 : tnode;override;
        protected
+          function first_addfloat: tnode; override;
           procedure second_addfloat;override;
           procedure second_cmpfloat;override;
           procedure second_cmpordinal;override;
@@ -48,12 +49,12 @@ interface
       globtype,systems,
       cutils,verbose,globals,
       constexp,
-      symconst,symdef,paramgr,
+      symconst,symdef,paramgr,symtable,symtype,
       aasmbase,aasmtai,aasmdata,aasmcpu,defutil,htypechk,
       cgbase,cgutils,cgcpu,
       cpuinfo,pass_1,pass_2,regvars,procinfo,
       cpupara,
-      ncon,nset,nadd,
+      ncon,nset,nadd,ncnv,ncal,nmat,
       ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32,
       hlcgobj
       ;
@@ -212,6 +213,36 @@ interface
               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,
                  location.register,left.location.register,right.location.register));
             end;
+          fpu_fpv4_s16:
+            begin
+              { force mmreg as location, left right doesn't matter
+                as both will be in a fpureg }
+              location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,true);
+              location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,true);
+
+              location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
+              if left.location.loc<>LOC_CMMREGISTER then
+                location.register:=left.location.register
+              else if right.location.loc<>LOC_CMMREGISTER then
+                location.register:=right.location.register
+              else
+                location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
+
+              case nodetype of
+                addn :
+                  op:=A_VADD;
+                muln :
+                  op:=A_VMUL;
+                subn :
+                  op:=A_VSUB;
+                slashn :
+                  op:=A_VDIV;
+                else
+                  internalerror(2009111401);
+              end;
+
+              current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op, location.register,left.location.register,right.location.register), PF_F32));
+            end;
           fpu_soft:
             { this case should be handled already by pass1 }
             internalerror(200308252);
@@ -273,6 +304,21 @@ interface
               cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
               current_asmdata.CurrAsmList.concat(taicpu.op_none(A_FMSTAT));
             end;
+          fpu_fpv4_s16:
+            begin
+              location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,true);
+              location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,true);
+
+              if nodetype in [equaln,unequaln] then
+                op:=A_VCMP
+              else
+                op:=A_VCMPE;
+
+              current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,
+                left.location.register,right.location.register));
+              cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
+              current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg(A_VMRS, NR_APSR_nzcv, NR_FPSCR));
+            end;
           fpu_soft:
             { this case should be handled already by pass1 }
             internalerror(2009112404);
@@ -464,6 +510,83 @@ interface
           end;
       end;
 
+    function tarmaddnode.first_addfloat: tnode;
+      var
+        procname: string[31];
+        { do we need to reverse the result ? }
+        notnode : boolean;
+        fdef : tdef;
+      begin
+        result := nil;
+        notnode := false;
+
+        if current_settings.fputype = fpu_fpv4_s16 then
+          begin
+            case tfloatdef(left.resultdef).floattype of
+              s32real:
+                begin
+                  result:=nil;
+                  notnode:=false;
+                end;
+              s64real:
+                begin
+                  fdef:=search_system_type('FLOAT64').typedef;
+                  procname:='float64';
+
+                  case nodetype of
+                    addn:
+                      procname:=procname+'_add';
+                    muln:
+                      procname:=procname+'_mul';
+                    subn:
+                      procname:=procname+'_sub';
+                    slashn:
+                      procname:=procname+'_div';
+                    ltn:
+                      procname:=procname+'_lt';
+                    lten:
+                      procname:=procname+'_le';
+                    gtn:
+                      begin
+                        procname:=procname+'_le';
+                        notnode:=true;
+                      end;
+                    gten:
+                      begin
+                        procname:=procname+'_lt';
+                        notnode:=true;
+                      end;
+                    equaln:
+                      procname:=procname+'_eq';
+                    unequaln:
+                      begin
+                        procname:=procname+'_eq';
+                        notnode:=true;
+                      end;
+                    else
+                      CGMessage3(type_e_operator_not_supported_for_types,node2opstr(nodetype),left.resultdef.typename,right.resultdef.typename);
+                  end;
+
+                  if nodetype in [ltn,lten,gtn,gten,equaln,unequaln] then
+                    resultdef:=pasbool8type;
+                  result:=ctypeconvnode.create_internal(ccallnode.createintern(procname,ccallparanode.create(
+                      ctypeconvnode.create_internal(right,fdef),
+                      ccallparanode.create(
+                        ctypeconvnode.create_internal(left,fdef),nil))),resultdef);
+
+                  left:=nil;
+                  right:=nil;
+
+                  { do we need to reverse the result }
+                  if notnode then
+                    result:=cnotnode.create(result);
+                end;
+            end;
+          end
+        else
+          result:=inherited first_addfloat;
+      end;
+
 
     procedure tarmaddnode.second_cmpordinal;
       var

compiler/arm/narmcal.pas

@@ -49,7 +49,7 @@ implementation
       if (realresdef.typ=floatdef) and 
          (target_info.abi <> abi_eabihf) and
          ((cs_fp_emulation in current_settings.moduleswitches) or
-          (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16])) then
+          (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16,fpu_fpv4_s16])) then
         begin
           { keep the fpu values in integer registers for now, the code
             generator will move them to memory or an mmregister when necessary

compiler/arm/narmcnv.pas

@@ -32,6 +32,7 @@ interface
        tarmtypeconvnode = class(tcgtypeconvnode)
          protected
            function first_int_to_real: tnode;override;
+           function first_real_to_real: tnode; override;
          { procedure second_int_to_int;override; }
          { procedure second_string_to_string;override; }
          { procedure second_cstring_to_pchar;override; }
@@ -58,7 +59,7 @@ implementation
 
    uses
       verbose,globtype,globals,systems,
-      symconst,symdef,aasmbase,aasmtai,aasmdata,
+      symconst,symdef,aasmbase,aasmtai,aasmdata,symtable,
       defutil,
       cgbase,cgutils,
       pass_1,pass_2,procinfo,
@@ -76,7 +77,8 @@ implementation
       var
         fname: string[19];
       begin
-        if cs_fp_emulation in current_settings.moduleswitches then
+        if (cs_fp_emulation in current_settings.moduleswitches) or
+          (current_settings.fputype=fpu_fpv4_s16) then
           result:=inherited first_int_to_real
         else
           begin
@@ -117,7 +119,8 @@ implementation
                 expectloc:=LOC_FPUREGISTER;
               fpu_vfpv2,
               fpu_vfpv3,
-              fpu_vfpv3_d16:
+              fpu_vfpv3_d16,
+              fpu_fpv4_s16:
                 expectloc:=LOC_MMREGISTER;
               else
                 internalerror(2009112702);
@@ -125,6 +128,48 @@ implementation
           end;
       end;
 
+    function tarmtypeconvnode.first_real_to_real: tnode;
+      begin
+        if (current_settings.fputype=fpu_fpv4_s16) then
+          begin
+            case tfloatdef(left.resultdef).floattype of
+              s32real:
+                case tfloatdef(resultdef).floattype of
+                  s64real:
+                    result:=ctypeconvnode.create_explicit(ccallnode.createintern('float32_to_float64',ccallparanode.create(
+                      ctypeconvnode.create_internal(left,search_system_type('FLOAT32REC').typedef),nil)),resultdef);
+                  s32real:
+                    begin
+                      result:=left;
+                      left:=nil;
+                    end;
+                  else
+                    internalerror(200610151);
+                end;
+              s64real:
+                case tfloatdef(resultdef).floattype of
+                  s32real:
+                    result:=ctypeconvnode.create_explicit(ccallnode.createintern('float64_to_float32',ccallparanode.create(
+                      ctypeconvnode.create_internal(left,search_system_type('FLOAT64').typedef),nil)),resultdef);
+                  s64real:
+                    begin
+                      result:=left;
+                      left:=nil;
+                    end;
+                  else
+                    internalerror(200610152);
+                end;
+              else
+                internalerror(200610153);
+            end;
+            left:=nil;
+            firstpass(result);
+            exit;
+          end
+        else
+          Result := inherited first_real_to_real;
+      end;
+
 
     procedure tarmtypeconvnode.second_int_to_real;
       const
@@ -214,6 +259,22 @@ implementation
               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(
                 signedprec2vfpop[signed,location.size],location.register,left.location.register));
             end;
+          fpu_fpv4_s16:
+            begin
+              location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
+              signed:=left.location.size=OS_S32;
+              location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,false);
+              if (left.location.size<>OS_F32) then
+                internalerror(2009112703);
+              if left.location.size<>location.size then
+                location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size)
+              else
+                location.register:=left.location.register;
+              if signed then
+                current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VCVT,location.register,left.location.register), PF_F32S32))
+              else
+                current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VCVT,location.register,left.location.register), PF_F32U32));
+            end;
         end;
       end;
 

compiler/arm/narminl.pas

@@ -91,7 +91,8 @@ implementation
             end;
           fpu_vfpv2,
           fpu_vfpv3,
-          fpu_vfpv3_d16:
+          fpu_vfpv3_d16,
+          fpu_fpv4_s16:
             begin
               location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,true);
               location_copy(location,left.location);
@@ -123,6 +124,13 @@ implementation
               fpu_vfpv3,
               fpu_vfpv3_d16:
                 expectloc:=LOC_MMREGISTER;
+              fpu_fpv4_s16:
+                begin
+                  if tfloatdef(left.resultdef).floattype=s32real then
+                    expectloc:=LOC_MMREGISTER
+                  else
+                    exit(inherited first_abs_real);
+                end;
               else
                 internalerror(2009112401);
             end;
@@ -146,6 +154,13 @@ implementation
               fpu_vfpv3,
               fpu_vfpv3_d16:
                 expectloc:=LOC_MMREGISTER;
+              fpu_fpv4_s16:
+                begin
+                  if tfloatdef(left.resultdef).floattype=s32real then
+                    expectloc:=LOC_MMREGISTER
+                  else
+                    exit(inherited first_sqr_real);
+                end;
               else
                 internalerror(2009112402);
             end;
@@ -169,6 +184,13 @@ implementation
               fpu_vfpv3,
               fpu_vfpv3_d16:
                 expectloc:=LOC_MMREGISTER;
+              fpu_fpv4_s16:
+                begin
+                  if tfloatdef(left.resultdef).floattype=s32real then
+                    expectloc:=LOC_MMREGISTER
+                  else
+                    exit(inherited first_sqrt_real);
+                end;
               else
                 internalerror(2009112403);
             end;
@@ -227,6 +249,8 @@ implementation
                 op:=A_FABSD;
               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,location.register,left.location.register));
             end;
+          fpu_fpv4_s16:
+            current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register), PF_F32));
         else
           internalerror(2009111402);
         end;
@@ -254,6 +278,8 @@ implementation
                 op:=A_FMULD;
               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,left.location.register));
             end;
+          fpu_fpv4_s16:
+            current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register), PF_F32));
         else
           internalerror(2009111403);
         end;
@@ -281,6 +307,8 @@ implementation
                 op:=A_FSQRTD;
               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,location.register,left.location.register));
             end;
+          fpu_fpv4_s16:
+            current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VSQRT,location.register,left.location.register));
         else
           internalerror(2009111402);
         end;

compiler/arm/narmmat.pas

@@ -39,6 +39,7 @@ interface
       end;
 
       tarmunaryminusnode = class(tcgunaryminusnode)
+        function pass_1: tnode; override;
         procedure second_float;override;
       end;
 
@@ -54,9 +55,10 @@ implementation
       cutils,verbose,globals,constexp,
       aasmbase,aasmcpu,aasmtai,aasmdata,
       defutil,
+      symtype,symconst,symtable,
       cgbase,cgobj,hlcgobj,cgutils,
       pass_2,procinfo,
-      ncon,
+      ncon,ncnv,ncal,
       cpubase,cpuinfo,
       ncgutil,cgcpu,
       nadd,pass_1,symdef;
@@ -326,6 +328,46 @@ implementation
                                TARMUNARYMINUSNODE
 *****************************************************************************}
 
+    function tarmunaryminusnode.pass_1: tnode;
+      var
+        procname: string[31];
+        fdef : tdef;
+      begin
+        if (current_settings.fputype<>fpu_fpv4_s16) or
+          (tfloatdef(resultdef).floattype=s32real) then
+          exit(inherited pass_1);
+
+        result:=nil;
+        firstpass(left);
+        if codegenerror then
+          exit;
+
+        if (left.resultdef.typ=floatdef) then
+          begin
+            case tfloatdef(resultdef).floattype of
+              s64real:
+                begin
+                  procname:='float64_sub';
+                  fdef:=search_system_type('FLOAT64').typedef;
+                end;
+              else
+                internalerror(2005082801);
+            end;
+            result:=ctypeconvnode.create_internal(ccallnode.createintern(procname,ccallparanode.create(
+              ctypeconvnode.create_internal(left,fDef),
+              ccallparanode.create(ctypeconvnode.create_internal(crealconstnode.create(0,resultdef),fdef),nil))),resultdef);
+
+            left:=nil;
+          end
+        else
+          begin
+            if (left.resultdef.typ=floatdef) then
+              expectloc:=LOC_FPUREGISTER
+             else if (left.resultdef.typ=orddef) then
+               expectloc:=LOC_REGISTER;
+          end;
+      end;
+
     procedure tarmunaryminusnode.second_float;
       var
         op: tasmop;
@@ -357,6 +399,15 @@ implementation
               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,
                 location.register,left.location.register));
             end;
+          fpu_fpv4_s16:
+            begin
+              location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,true);
+              location:=left.location;
+              if (left.location.loc=LOC_CMMREGISTER) then
+                location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
+              current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VNEG,
+                location.register,left.location.register), PF_F32));
+            end
           else
             internalerror(2009112602);
         end;

compiler/arm/raarmgas.pas

@@ -35,6 +35,7 @@ Unit raarmgas;
         actwideformat : boolean;
         function is_asmopcode(const s: string):boolean;override;
         function is_register(const s:string):boolean;override;
+        function is_targetdirective(const s: string): boolean; override;
         procedure handleopcode;override;
         procedure BuildReference(oper : tarmoperand);
         procedure BuildOperand(oper : tarmoperand);
@@ -43,6 +44,7 @@ Unit raarmgas;
         procedure BuildOpCode(instr : tarminstruction);
         procedure ReadSym(oper : tarmoperand);
         procedure ConvertCalljmp(instr : tarminstruction);
+        procedure HandleTargetDirective; override;
       end;
 
 
@@ -119,6 +121,16 @@ Unit raarmgas;
           end;
       end;
 
+    function tarmattreader.is_targetdirective(const s: string): boolean;
+      begin
+        if s = '.thumb_func' then
+          result:=true
+        else if s='.thumb_set' then
+          result:=true
+        else
+          Result:=inherited is_targetdirective(s);
+      end;
+
 
     procedure tarmattreader.ReadSym(oper : tarmoperand);
       var
@@ -1049,7 +1061,7 @@ Unit raarmgas;
             AS_COMMA: { Operand delimiter }
               Begin
                 if ((instr.opcode in [A_MOV, A_MVN, A_CMP, A_CMN, A_TST, A_TEQ]) and (operandnum=2)) or
-                  ((operandnum=3) and not(instr.opcode in [A_UMLAL,A_UMULL,A_SMLAL,A_SMULL,A_MLA])) then
+                  ((operandnum=3) and not(instr.opcode in [A_UMLAL,A_UMULL,A_SMLAL,A_SMULL,A_MLA,A_MRC,A_MCR,A_MCRR,A_MRRC])) then
                   begin
                     Consume(AS_COMMA);
                     if not(TryBuildShifterOp(instr.Operands[operandnum+1] as tarmoperand)) then
@@ -1205,6 +1217,31 @@ Unit raarmgas;
           end;
       end;
 
+    procedure tarmattreader.HandleTargetDirective;
+      var
+        symname,
+        symval  : String;
+        val     : aint;
+        symtyp  : TAsmsymtype;
+      begin
+        if actasmpattern='.thumb_set' then
+          begin
+            consume(AS_TARGET_DIRECTIVE);
+            BuildConstSymbolExpression(true,false,false, val,symname,symtyp);
+            Consume(AS_COMMA);
+            BuildConstSymbolExpression(true,false,false, val,symval,symtyp);
+
+            curList.concat(tai_thumb_set.create(symname,symval));
+          end
+        else if actasmpattern='.thumb_func' then
+          begin
+            consume(AS_TARGET_DIRECTIVE);
+            curList.concat(tai_thumb_func.create);
+          end
+        else
+          inherited HandleTargetDirective;
+      end;
+
 
     procedure tarmattreader.handleopcode;
       var

compiler/arm/rarmcon.inc

@@ -91,3 +91,21 @@ NR_D31 = tregister($0407001F);
 NR_CPSR = tregister($05000000);
 NR_FPSCR = tregister($05000001);
 NR_SPSR = tregister($05000002);
+NR_APSR_nzcv = tregister($05000003);
+NR_CR0 = tregister($05000004);
+NR_CR1 = tregister($05000005);
+NR_CR2 = tregister($05000006);
+NR_CR3 = tregister($05000007);
+NR_CR4 = tregister($05000008);
+NR_CR5 = tregister($05000009);
+NR_CR6 = tregister($0500000A);
+NR_CR7 = tregister($0500000B);
+NR_CR8 = tregister($0500000C);
+NR_CR9 = tregister($0500000D);
+NR_CR10 = tregister($0500000E);
+NR_CR11 = tregister($0500000F);
+NR_CR12 = tregister($05000010);
+NR_CR13 = tregister($05000011);
+NR_CR14 = tregister($05000012);
+NR_CR15 = tregister($05000013);
+NR_p15 = tregister($05000014);

compiler/arm/rarmdwa.inc

@@ -90,4 +90,22 @@
 0,
 0,
 0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
 0

compiler/arm/rarmnor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armreg.dat }
-92
+110

compiler/arm/rarmnum.inc

@@ -90,4 +90,22 @@ tregister($0407001E),
 tregister($0407001F),
 tregister($05000000),
 tregister($05000001),
-tregister($05000002)
+tregister($05000002),
+tregister($05000003),
+tregister($05000004),
+tregister($05000005),
+tregister($05000006),
+tregister($05000007),
+tregister($05000008),
+tregister($05000009),
+tregister($0500000A),
+tregister($0500000B),
+tregister($0500000C),
+tregister($0500000D),
+tregister($0500000E),
+tregister($0500000F),
+tregister($05000010),
+tregister($05000011),
+tregister($05000012),
+tregister($05000013),
+tregister($05000014)

compiler/arm/rarmrni.inc

@@ -90,4 +90,22 @@
 88,
 89,
 90,
-91
+91,
+92,
+93,
+94,
+95,
+96,
+97,
+98,
+99,
+100,
+101,
+102,
+103,
+104,
+105,
+106,
+107,
+108,
+109

compiler/arm/rarmsri.inc

@@ -1,6 +1,23 @@
 { don't edit, this file is generated from armreg.dat }
 0,
+92,
 89,
+93,
+94,
+103,
+104,
+105,
+106,
+107,
+108,
+95,
+96,
+97,
+98,
+99,
+100,
+101,
+102,
 27,
 30,
 57,
@@ -42,6 +59,7 @@
 23,
 24,
 90,
+109,
 1,
 2,
 11,

compiler/arm/rarmsta.inc

@@ -90,4 +90,22 @@
 0,
 0,
 0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
 0

compiler/arm/rarmstd.inc

@@ -90,4 +90,22 @@
 'd31',
 'cpsr',
 'fpscr',
-'spsr'
+'spsr',
+'apsr_nzcv',
+'cr0',
+'cr1',
+'cr2',
+'cr3',
+'cr4',
+'cr5',
+'cr6',
+'cr7',
+'cr8',
+'cr9',
+'cr10',
+'cr11',
+'cr12',
+'cr13',
+'cr14',
+'cr15',
+'p15'

compiler/arm/rarmsup.inc

@@ -91,3 +91,21 @@ RS_D31 = $1F;
 RS_CPSR = $00;
 RS_FPSCR = $01;
 RS_SPSR = $02;
+RS_APSR_nzcv = $03;
+RS_CR0 = $04;
+RS_CR1 = $05;
+RS_CR2 = $06;
+RS_CR3 = $07;
+RS_CR4 = $08;
+RS_CR5 = $09;
+RS_CR6 = $0A;
+RS_CR7 = $0B;
+RS_CR8 = $0C;
+RS_CR9 = $0D;
+RS_CR10 = $0E;
+RS_CR11 = $0F;
+RS_CR12 = $10;
+RS_CR13 = $11;
+RS_CR14 = $12;
+RS_CR15 = $13;
+RS_p15 = $14;

compiler/arm/rgcpu.pas

@@ -45,6 +45,9 @@ unit rgcpu;
        end;
 
        trgcputhumb2 = class(trgobj)
+       private
+         procedure SplitITBlock(list:TAsmList;pos:tai);
+       public
          procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
          procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
        end;
@@ -67,10 +70,17 @@ unit rgcpu;
     procedure trgintcputhumb2.add_cpu_interferences(p: tai);
       var
         r : tregister;
+        hr : longint;
       begin
         if p.typ=ait_instruction then
           begin
             case taicpu(p).opcode of
+              A_CBNZ,
+              A_CBZ:
+                begin
+                  for hr := RS_R8 to RS_R15 do
+                    add_edge(getsupreg(taicpu(p).oper[0]^.reg), hr);
+                end;
               A_ADD:
                 begin
                   if taicpu(p).ops = 3 then
@@ -245,6 +255,69 @@ unit rgcpu;
           result:=getsubreg(r);
       end;
 
+    function GetITRemainderOp(originalOp:TAsmOp;remLevels:longint;var newOp: TAsmOp;var NeedsCondSwap:boolean) : TAsmOp;
+      const
+        remOps : array[1..3] of array[A_ITE..A_ITTTT] of TAsmOp = (
+          (A_IT,A_IT,       A_IT,A_IT,A_IT,A_IT,            A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT),
+          (A_NONE,A_NONE,   A_ITT,A_ITE,A_ITE,A_ITT,        A_ITT,A_ITT,A_ITE,A_ITE,A_ITE,A_ITE,A_ITT,A_ITT),
+          (A_NONE,A_NONE,   A_NONE,A_NONE,A_NONE,A_NONE,    A_ITTT,A_ITEE,A_ITET,A_ITTE,A_ITTE,A_ITET,A_ITEE,A_ITTT));
+        newOps : array[1..3] of array[A_ITE..A_ITTTT] of TAsmOp = (
+          (A_IT,A_IT,       A_ITE,A_ITT,A_ITE,A_ITT,        A_ITEE,A_ITTE,A_ITET,A_ITTT,A_ITEE,A_ITTE,A_ITET,A_ITTT),
+          (A_NONE,A_NONE,   A_IT,A_IT,A_IT,A_IT,            A_ITE,A_ITT,A_ITE,A_ITT,A_ITE,A_ITT,A_ITE,A_ITT),
+          (A_NONE,A_NONE,   A_NONE,A_NONE,A_NONE,A_NONE,    A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT));
+        needsSwap: array[1..3] of array[A_ITE..A_ITTTT] of Boolean = (
+          (true ,false,     true ,true ,false,false,        true ,true ,true ,true ,false,false,false,false),
+          (false,false,     true ,false,true ,false,        true ,true ,false,false,true ,true ,false,false),
+          (false,false,     false,false,false,false,        true ,false,true ,false,true ,false,true ,false));
+      begin
+        result:=remOps[remLevels][originalOp];
+        newOp:=newOps[remLevels][originalOp];
+        NeedsCondSwap:=needsSwap[remLevels][originalOp];
+      end;
+
+    procedure trgcputhumb2.SplitITBlock(list: TAsmList; pos: tai);
+      var
+        hp : tai;
+        level,itLevel : LongInt;
+        remOp,newOp : TAsmOp;
+        needsSwap : boolean;
+      begin
+        hp:=pos;
+        level := 0;
+        while assigned(hp) do
+          begin
+            if IsIT(taicpu(hp).opcode) then
+              break
+            else if hp.typ=ait_instruction then
+              inc(level);
+
+            hp:=tai(hp.Previous);
+          end;
+
+        if not assigned(hp) then
+          internalerror(2012100801); // We are supposed to have found the ITxxx instruction here
+
+        if (hp.typ<>ait_instruction) or
+          (not IsIT(taicpu(hp).opcode)) then
+          internalerror(2012100802); // Sanity check
+
+        itLevel := GetITLevels(taicpu(hp).opcode);
+        if level=itLevel then
+          exit; // pos was the last instruction in the IT block anyway
+
+        remOp:=GetITRemainderOp(taicpu(hp).opcode,itLevel-level,newOp,needsSwap);
+
+        if (remOp=A_NONE) or
+          (newOp=A_NONE) then
+          Internalerror(2012100803);
+
+        taicpu(hp).opcode:=newOp;
+
+        if needsSwap then
+          list.InsertAfter(taicpu.op_cond(remOp,inverse_cond(taicpu(hp).oper[0]^.cc)), pos)
+        else
+          list.InsertAfter(taicpu.op_cond(remOp,taicpu(hp).oper[0]^.cc), pos);
+      end;
 
     procedure trgcputhumb2.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
       var
@@ -267,6 +340,18 @@ unit rgcpu;
           (taicpu(pos).oper[1]^.reg=NR_PC) then
           pos:=tai(pos.previous);
 
+        if (pos.typ=ait_instruction) and
+          (taicpu(pos).condition<>C_None) and
+          (taicpu(pos).opcode<>A_B) then
+          SplitITBlock(list, pos)
+        else if (pos.typ=ait_instruction) and
+          IsIT(taicpu(pos).opcode) then
+          begin
+            if not assigned(pos.Previous) then
+              list.InsertBefore(tai_comment.Create('Dummy'), pos);
+            pos:=tai(pos.Previous);
+          end;
+
         if (spilltemp.offset>4095) or (spilltemp.offset<-255) then
           begin
             helplist:=TAsmList.create;
@@ -313,6 +398,18 @@ unit rgcpu;
         l : tasmlabel;
         hreg : tregister;
       begin
+        if (pos.typ=ait_instruction) and
+          (taicpu(pos).condition<>C_None) and
+          (taicpu(pos).opcode<>A_B) then
+          SplitITBlock(list, pos)
+        else if (pos.typ=ait_instruction) and
+          IsIT(taicpu(pos).opcode) then
+          begin
+            if not assigned(pos.Previous) then
+              list.InsertBefore(tai_comment.Create('Dummy'), pos);
+            pos:=tai(pos.Previous);
+          end;
+
         if (spilltemp.offset>4095) or (spilltemp.offset<-255) then
           begin
             helplist:=TAsmList.create;

compiler/avr/cpubase.pas

@@ -326,7 +326,7 @@ unit cpubase;
 
 
     const
-      std_regname_table : array[tregisterindex] of string[7] = (
+      std_regname_table : array[tregisterindex] of string[10] = (
         {$i ravrstd.inc}
       );
 

compiler/avr/cpuinfo.pas

@@ -104,7 +104,6 @@ Const
    ((
    	controllertypestr:'';
         controllerunitstr:'';
-        interruptvectors:0;
         flashbase:0;
         flashsize:0;
         srambase:0;
@@ -115,7 +114,6 @@ Const
         (
    	controllertypestr:'ATMEGA16';
         controllerunitstr:'ATMEGA16';
-        interruptvectors:0;
         flashbase:0;
         flashsize:$4000;
         srambase:0;
@@ -126,7 +124,6 @@ Const
         (
    	controllertypestr:'ATMEGA32';
         controllerunitstr:'ATMEGA32';
-        interruptvectors:0;
         flashbase:0;
         flashsize:$8000;
         srambase:0;
@@ -137,7 +134,6 @@ Const
    	(
         controllertypestr:'ATMEGA48';
         controllerunitstr:'ATMEGA48';
-        interruptvectors:0;
         flashbase:0;
         flashsize:$1000;
         srambase:0;
@@ -148,7 +144,6 @@ Const
    	(
         controllertypestr:'ATMEGA64';
         controllerunitstr:'ATMEGA64';
-        interruptvectors:0;
         flashbase:0;
         flashsize:$10000;
         srambase:0;
@@ -159,7 +154,6 @@ Const
    	(
         controllertypestr:'ATMEGA128';
         controllerunitstr:'ATMEGA128';
-        interruptvectors:0;
         flashbase:0;
         flashsize:$20000;
         srambase:0;

compiler/fpcdefs.inc

@@ -28,13 +28,6 @@
 
 {$define USEEXCEPT}
 
-{ If anyone wants to use interrupt for
-  a specific target, add a
-  $define FPC_HAS_SYSTEMS_INTERRUPT_TABLE
-  to fpcdefs.inc to reactivate
-  the corresponding code }
-{$undef FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-
 { This fake CPU is used to allow incorporation of globtype unit
   into utils/ppudump without any CPU specific code PM }
 {$ifdef generic_cpu}

compiler/globtype.pas

@@ -267,7 +267,6 @@ interface
        { Used by ARM / AVR to differentiate between specific microcontrollers }
        tcontrollerdatatype = record
           controllertypestr, controllerunitstr: string[20];
-          interruptvectors:integer;
           flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize: dword;
        end;
 

compiler/m68k/cpubase.pas

@@ -353,7 +353,7 @@ implementation
 
 
     const
-      std_regname_table : array[tregisterindex] of string[7] = (
+      std_regname_table : array[tregisterindex] of string[10] = (
         {$i r68kstd.inc}
       );
 

compiler/mips/cpubase.pas

@@ -295,7 +295,7 @@ unit cpubase;
 
 
     const
-      std_regname_table : array[tregisterindex] of string[7] = (
+      std_regname_table : array[tregisterindex] of string[10] = (
         {$i rmipsstd.inc}
       );
 

compiler/nadd.pas

@@ -2608,7 +2608,11 @@ implementation
         { In non-emulation mode, real opcodes are
           emitted for floating point values.
         }
-        if not (cs_fp_emulation in current_settings.moduleswitches) then
+        if not ((cs_fp_emulation in current_settings.moduleswitches)
+{$ifdef cpufpemu}
+                or (current_settings.fputype=fpu_soft)
+{$endif cpufpemu}
+                ) then
           exit;
 
         if not(target_info.system in systems_wince) then
@@ -2768,12 +2772,9 @@ implementation
          if nodetype=slashn then
            begin
 {$ifdef cpufpemu}
-             if (current_settings.fputype=fpu_soft) or (cs_fp_emulation in current_settings.moduleswitches) then
-               begin
-                 result:=first_addfloat;
-                 if assigned(result) then
-                   exit;
-               end;
+             result:=first_addfloat;
+             if assigned(result) then
+               exit;
 {$endif cpufpemu}
              expectloc:=LOC_FPUREGISTER;
            end
@@ -2984,12 +2985,9 @@ implementation
          else if (rd.typ=floatdef) or (ld.typ=floatdef) then
             begin
 {$ifdef cpufpemu}
-             if (current_settings.fputype=fpu_soft) or (cs_fp_emulation in current_settings.moduleswitches) then
-               begin
-                 result:=first_addfloat;
-                 if assigned(result) then
-                   exit;
-               end;
+             result:=first_addfloat;
+             if assigned(result) then
+               exit;
 {$endif cpufpemu}
               if nodetype in [addn,subn,muln,andn,orn,xorn] then
                 expectloc:=LOC_FPUREGISTER

compiler/ncgutil.pas

@@ -146,8 +146,6 @@ interface
 
     procedure gen_fpc_dummy(list : TAsmList);
 
-    procedure InsertInterruptTable;
-
 implementation
 
   uses
@@ -2154,89 +2152,4 @@ implementation
       end;
 
 
-    procedure InsertInterruptTable;
-
-      procedure WriteVector(const name: string);
-{$IFDEF arm}
-        var
-          ai: taicpu;
-{$ENDIF arm}
-        begin
-{$IFDEF arm}
-          if current_settings.cputype in [cpu_armv7m] then
-            current_asmdata.asmlists[al_globals].concat(tai_const.Createname(name,0))
-          else
-            begin
-              ai:=taicpu.op_sym(A_B,current_asmdata.RefAsmSymbol(name));
-              ai.is_jmp:=true;
-              current_asmdata.asmlists[al_globals].concat(ai);
-            end;
-{$ENDIF arm}
-        end;
-
-      function GetInterruptTableLength: longint;
-        begin
-{$if defined(ARM)}
-          result:=embedded_controllers[current_settings.controllertype].interruptvectors;
-{$else}
-          result:=0;
-{$endif}
-        end;
-
-      var
-        hp: tused_unit;
-        sym: tsym;
-        i, i2: longint;
-        interruptTable: array of tprocdef;
-        pd: tprocdef;
-      begin
-        SetLength(interruptTable, GetInterruptTableLength);
-        FillChar(interruptTable[0], length(interruptTable)*sizeof(pointer), 0);
-
-        hp:=tused_unit(usedunits.first);
-        while assigned(hp) do
-          begin
-            for i := 0 to hp.u.symlist.Count-1 do
-              begin
-                sym:=tsym(hp.u.symlist[i]);
-                if not assigned(sym) then
-                  continue;
-                if sym.typ = procsym then
-                  begin
-                    for i2 := 0 to tprocsym(sym).ProcdefList.Count-1 do
-                      begin
-                        pd:=tprocdef(tprocsym(sym).ProcdefList[i2]);
-                        if pd.interruptvector >= 0 then
-                          begin
-                            if pd.interruptvector > high(interruptTable) then
-                              Internalerror(2011030602);
-                            if interruptTable[pd.interruptvector] <> nil then
-                              internalerror(2011030601);
-
-                            interruptTable[pd.interruptvector]:=pd;
-                            break;
-                          end;
-                      end;
-                  end;
-              end;
-            hp:=tused_unit(hp.next);
-          end;
-
-        new_section(current_asmdata.asmlists[al_globals],sec_init,'VECTORS',sizeof(pint));
-        current_asmdata.asmlists[al_globals].concat(Tai_symbol.Createname_global('VECTORS',AT_DATA,0));
-{$IFDEF arm}
-        if current_settings.cputype in [cpu_armv7m] then
-          current_asmdata.asmlists[al_globals].concat(tai_const.Createname('_stack_top',0)); { ARMv7-M processors have the initial stack value at address 0 }
-{$ENDIF arm}
-
-        for i:=0 to high(interruptTable) do
-          begin
-            if interruptTable[i]<>nil then
-              writeVector(interruptTable[i].mangledname)
-            else
-              writeVector('DefaultHandler'); { Default handler name }
-          end;
-      end;
-
-
 end.

compiler/pdecsub.pas

@@ -1484,26 +1484,9 @@ begin
 end;
 
 procedure pd_interrupt(pd:tabstractprocdef);
-
-{$ifdef FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-var v: Tconstexprint;
-{$endif FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-
 begin
   if pd.parast.symtablelevel>normal_function_level then
     Message(parser_e_dont_nest_interrupt);
-
-{$ifdef FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-  if target_info.system in systems_interrupt_table then
-    begin
-      if token<>_SEMICOLON then
-        begin
-          pd.proccalloption:=pocall_interrupt;
-          v:=get_intconst;
-          Tprocdef(pd).interruptvector:=v.uvalue;
-        end;
-    end;
-{$endif FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
 end;
 
 procedure pd_abstract(pd:tabstractprocdef);

compiler/pmodules.pas

@@ -2225,11 +2225,6 @@ type
          cnodeutils.InsertResStrTablesTable;
          cnodeutils.InsertMemorySizes;
 
-{$ifdef FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-         if target_info.system in systems_interrupt_table then
-           InsertInterruptTable;
-{$endif FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-
          { Insert symbol to resource info }
          cnodeutils.InsertResourceInfo(resources_used);
 

compiler/powerpc/cpubase.pas

@@ -422,7 +422,7 @@ implementation
       rgbase,verbose;
 
     const
-      std_regname_table : array[tregisterindex] of string[7] = (
+      std_regname_table : array[tregisterindex] of string[10] = (
         {$i rppcstd.inc}
       );
 

compiler/powerpc64/cpubase.pas

@@ -424,7 +424,7 @@ uses
   rgBase, verbose, itcpugas;
 
 const
-  std_regname_table: array[tregisterindex] of string[7] = (
+  std_regname_table: array[tregisterindex] of string[10] = (
 {$I rppcstd.inc}
     );
 

compiler/psystem.pas

@@ -629,14 +629,19 @@ implementation
 {$endif SPARC}
 {$ifdef arm}
         aiclass[ait_thumb_func]:=tai_thumb_func;
+        aiclass[ait_thumb_set]:=tai_thumb_set;
 {$endif arm}
+        aiclass[ait_set]:=tai_set;
+        aiclass[ait_weak]:=tai_weak;
         aiclass[ait_cutobject]:=tai_cutobject;
         aiclass[ait_regalloc]:=tai_regalloc;
         aiclass[ait_tempalloc]:=tai_tempalloc;
         aiclass[ait_marker]:=tai_marker;
         aiclass[ait_seh_directive]:=tai_seh_directive;
+{$ifdef JVM}
         aiclass[ait_jvar]:=tai_jvar;
         aiclass[ait_jcatch]:=tai_jcatch;
+{$endif JVM}
       end;
 
 end.

compiler/raatt.pas

@@ -53,6 +53,7 @@ unit raatt;
         AS_ALIGN,AS_BALIGN,AS_P2ALIGN,AS_ASCII,
         AS_ASCIIZ,AS_LCOMM,AS_COMM,AS_SINGLE,AS_DOUBLE,AS_EXTENDED,AS_CEXTENDED,
         AS_DATA,AS_TEXT,AS_INIT,AS_FINI,AS_RVA,AS_END,
+        AS_SET,AS_WEAK,AS_SECTION,
         {------------------ Assembler Operators  --------------------}
         AS_TYPE,AS_SIZEOF,AS_VMTOFFSET,AS_MOD,AS_SHL,AS_SHR,AS_NOT,AS_AND,AS_OR,AS_XOR,AS_NOR,AS_AT,
         AS_LO,AS_HI,
@@ -66,7 +67,7 @@ unit raatt;
       { These tokens should be modified accordingly to the modifications }
       { in the different enumerations.                                   }
       firstdirective = AS_DB;
-      lastdirective  = AS_END;
+      lastdirective  = AS_SECTION;
 
       token2str : array[tasmtoken] of tasmkeyword=(
         '','Label','LLabel','string','integer',
@@ -78,6 +79,7 @@ unit raatt;
         '.align','.balign','.p2align','.ascii',
         '.asciz','.lcomm','.comm','.single','.double','.tfloat','.tcfloat',
         '.data','.text','.init','.fini','.rva','END',
+        '.set','.weak','.section',
         'TYPE','SIZEOF','VMTOFFSET','%','<<','>>','!','&','|','^','~','@','lo','hi',
         'directive');
 
@@ -972,9 +974,13 @@ unit raatt;
    Function tattreader.Assemble: tlinkedlist;
      Var
        hl         : tasmlabel;
-       commname   : string;
+       commname,
+       symname,
+       symval     : string;
        lasTSec    : TAsmSectiontype;
        l1,l2      : longint;
+       symofs     : aint;
+       symtyp     : TAsmsymtype;
      Begin
        Message1(asmr_d_start_reading,'GNU AS');
        firsttoken:=TRUE;
@@ -1200,6 +1206,31 @@ unit raatt;
                BuildRva;
              end;
 
+           AS_SET:
+             begin
+               Consume(AS_SET);
+               BuildConstSymbolExpression(true,false,false, symofs,symname,symtyp);
+               Consume(AS_COMMA);
+               BuildConstSymbolExpression(true,false,false, symofs,symval,symtyp);
+
+               curList.concat(tai_set.create(symname,symval));
+             end;
+
+           AS_WEAK:
+             begin
+               Consume(AS_WEAK);
+               BuildConstSymbolExpression(true,false,false, l1,symname,symtyp);
+               curList.concat(tai_weak.create(symname));
+             end;
+
+           AS_SECTION:
+             begin
+               Consume(AS_SECTION);
+               new_section(curlist, sec_user, actasmpattern, 0);
+               //curList.concat(tai_section.create(sec_user, actasmpattern, 0));
+               consume(AS_STRING);
+             end;
+
            AS_TARGET_DIRECTIVE:
              HandleTargetDirective;
 

compiler/rgbase.pas

@@ -29,7 +29,7 @@ interface
       cpuBase,cgBase;
 
     type
-      TRegNameTable = array[tregisterindex] of string[7];
+      TRegNameTable = array[tregisterindex] of string[10];
       TRegisterIndexTable = array[tregisterindex] of tregisterindex;
 
     function findreg_by_number_table(r:Tregister;const regnumber_index:TRegisterIndexTable):tregisterindex;

compiler/symdef.pas

@@ -638,8 +638,6 @@ interface
 {$ifdef oldregvars}
           regvarinfo: pregvarinfo;
 {$endif oldregvars}
-          { interrupt vector }
-          interruptvector : longint;
           { First/last assembler symbol/instruction in aasmoutput list.
             Note: initialised after compiling the code for the procdef, but
               not saved to/restored from ppu. Used when inserting debug info }
@@ -4079,7 +4077,6 @@ implementation
 {$ifdef i386}
           fpu_used:=maxfpuregs;
 {$endif i386}
-         interruptvector:=-1;
       end;
 
 
@@ -4125,10 +4122,6 @@ implementation
          else
            import_name:=nil;
          import_nr:=ppufile.getword;
-{$ifdef FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-         if target_info.system in systems_interrupt_table then
-           interruptvector:=ppufile.getlongint;
-{$endif FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
          if (po_msgint in procoptions) then
            messageinf.i:=ppufile.getlongint;
          if (po_msgstr in procoptions) then
@@ -4275,10 +4268,6 @@ implementation
          if po_has_importname in procoptions then
            ppufile.putstring(import_name^);
          ppufile.putword(import_nr);
-{$ifdef FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-         if target_info.system in systems_interrupt_table then
-           ppufile.putlongint(interruptvector);
-{$endif FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
          if (po_msgint in procoptions) then
            ppufile.putlongint(messageinf.i);
          if (po_msgstr in procoptions) then

compiler/systems.pas

@@ -303,15 +303,6 @@ interface
 
        systems_internal_sysinit = [system_i386_linux,system_i386_win32];
 
-       {$ifdef FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-       { If anyone wants to use interrupt for
-         a specific target, add a
-         $define FPC_HAS_SYSTEMS_INTERRUPT_TABLE
-         to fpcdefs.inc to reactivate
-         the corresponding code }
-       systems_interrupt_table = [{system_arm_embedded}];
-       {$endif FPC_HAS_SYSTEMS_INTERRUPT_TABLE}
-
        { all systems that use garbage collection for reference-counted types }
        systems_garbage_collected_managed_types = [
          system_jvm_java32,

compiler/systems/t_embed.pas

@@ -232,9 +232,38 @@ begin
       ct_at91sam7x256,
       ct_at91sam7xc256,
 
-      ct_stm32f103rb,
-      ct_stm32f103re,
-      ct_stm32f103c4t,
+      ct_stm32f100x4,
+      ct_stm32f100x6,
+      ct_stm32f100x8,
+      ct_stm32f100xB,
+      ct_stm32f100xC,
+      ct_stm32f100xD,
+      ct_stm32f100xE,
+      ct_stm32f101x4,
+      ct_stm32f101x6,
+      ct_stm32f101x8,
+      ct_stm32f101xB,
+      ct_stm32f101xC,
+      ct_stm32f101xD,
+      ct_stm32f101xE,
+      ct_stm32f101xF,
+      ct_stm32f101xG,
+      ct_stm32f102x4,
+      ct_stm32f102x6,
+      ct_stm32f102x8,
+      ct_stm32f102xB,
+      ct_stm32f103x4,
+      ct_stm32f103x6,
+      ct_stm32f103x8,
+      ct_stm32f103xB,
+      ct_stm32f103xC,
+      ct_stm32f103xD,
+      ct_stm32f103xE,
+      ct_stm32f103xF,
+      ct_stm32f103xG,
+      ct_stm32f107x8,
+      ct_stm32f107xB,
+      ct_stm32f107xC,
 
       { TI - 64 K Flash, 16 K SRAM Devices }
       ct_lm3s1110,

compiler/x86/cpubase.pas

@@ -268,7 +268,7 @@ implementation
 
     const
     {$ifdef x86_64}
-      std_regname_table : array[tregisterindex] of string[7] = (
+      std_regname_table : array[tregisterindex] of string[10] = (
         {$i r8664std.inc}
       );
 
@@ -279,7 +279,7 @@ implementation
         {$i r8664sri.inc}
       );
     {$else x86_64}
-      std_regname_table : array[tregisterindex] of string[7] = (
+      std_regname_table : array[tregisterindex] of string[10] = (
         {$i r386std.inc}
       );
 

rtl/arm/thumb2.inc

@@ -33,10 +33,19 @@ Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
 begin
   { Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
   asm
+    {$IFDEF FPUFPV4_S16}
+    movw r0, #(0xed88)
+    movt r0, #(0xe000)
+    ldr r1, [r0]
+    orr r1, r1, #(0xF << 20)
+    str r1, [r0]
+    bx lr
+    {$ELSE FPUFPV4_S16}
     rfs r0
     and r0,r0,#0xffe0ffff
     orr r0,r0,#0x00070000
     wfs r0
+    {$endif FPUFPV4_S16}
   end;
 end;
 {$endif}

rtl/embedded/Makefile

@@ -1,5 +1,5 @@
 #
-# Don't edit, this file is generated by FPCMake Version 2.0.0 [2012/04/25]
+# Don't edit, this file is generated by FPCMake Version 2.0.0 [2012/09/26]
 #
 default: all
 MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-qnx i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim m68k-linux m68k-freebsd m68k-netbsd m68k-amiga m68k-atari m68k-openbsd m68k-palmos m68k-embedded powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macos powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded arm-linux arm-palmos arm-darwin arm-wince arm-gba arm-nds arm-embedded arm-symbian powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux jvm-java jvm-android
@@ -210,6 +210,14 @@ endif
 ifeq ($(OS_TARGET),linux)
 linuxHier=1
 endif
+ifndef CROSSCOMPILE
+BUILDFULLNATIVE=1
+export BUILDFULLNATIVE
+endif
+ifdef BUILDFULLNATIVE
+BUILDNATIVE=1
+export BUILDNATIVE
+endif
 export OS_TARGET OS_SOURCE ARCH CPU_TARGET CPU_SOURCE FULL_TARGET FULL_SOURCE TARGETSUFFIX SOURCESUFFIX CROSSCOMPILE
 ifdef FPCDIR
 override FPCDIR:=$(subst \,/,$(FPCDIR))
@@ -311,7 +319,7 @@ CPU_UNITS=
 SYSINIT_UNITS=
 ifeq ($(ARCH),arm)
 ifeq ($(SUBARCH),armv7m)
-CPU_UNITS=lm3fury lm3tempest stm32f103 lpc1768 # thumb2_bare
+CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 # thumb2_bare
 endif
 ifeq ($(SUBARCH),armv4t)
 CPU_UNITS=lpc21x4 at91sam7x256 sc32442b
@@ -1681,17 +1689,12 @@ endif
 endif
 ifdef CREATESHARED
 override FPCOPT+=-Cg
-ifeq ($(CPU_TARGET),i386)
-override FPCOPT+=-Aas
 endif
-endif
-ifeq ($(findstring 2.0.,$(FPC_VERSION)),)
 ifneq ($(findstring $(OS_TARGET),freebsd openbsd netbsd linux solaris),)
 ifeq ($(CPU_TARGET),x86_64)
 override FPCOPT+=-Cg
 endif
 endif
-endif
 ifdef LINKSHARED
 endif
 ifdef OPT
@@ -2066,6 +2069,96 @@ endif
 fpc_makefile_sub2: $(addsuffix _makefile_dirs,$(TARGET_DIRS) $(TARGET_EXAMPLEDIRS))
 fpc_makefile_dirs: fpc_makefile_sub1 fpc_makefile_sub2
 fpc_makefiles: fpc_makefile fpc_makefile_dirs
+ifdef TARGET_DIRS_TARGET_DIRS
+TARGET_DIRS_all:
+	$(MAKE) -C TARGET_DIRS all
+TARGET_DIRS_debug:
+	$(MAKE) -C TARGET_DIRS debug
+TARGET_DIRS_smart:
+	$(MAKE) -C TARGET_DIRS smart
+TARGET_DIRS_release:
+	$(MAKE) -C TARGET_DIRS release
+TARGET_DIRS_units:
+	$(MAKE) -C TARGET_DIRS units
+TARGET_DIRS_examples:
+	$(MAKE) -C TARGET_DIRS examples
+TARGET_DIRS_shared:
+	$(MAKE) -C TARGET_DIRS shared
+TARGET_DIRS_install:
+	$(MAKE) -C TARGET_DIRS install
+TARGET_DIRS_sourceinstall:
+	$(MAKE) -C TARGET_DIRS sourceinstall
+TARGET_DIRS_exampleinstall:
+	$(MAKE) -C TARGET_DIRS exampleinstall
+TARGET_DIRS_distinstall:
+	$(MAKE) -C TARGET_DIRS distinstall
+TARGET_DIRS_zipinstall:
+	$(MAKE) -C TARGET_DIRS zipinstall
+TARGET_DIRS_zipsourceinstall:
+	$(MAKE) -C TARGET_DIRS zipsourceinstall
+TARGET_DIRS_zipexampleinstall:
+	$(MAKE) -C TARGET_DIRS zipexampleinstall
+TARGET_DIRS_zipdistinstall:
+	$(MAKE) -C TARGET_DIRS zipdistinstall
+TARGET_DIRS_clean:
+	$(MAKE) -C TARGET_DIRS clean
+TARGET_DIRS_distclean:
+	$(MAKE) -C TARGET_DIRS distclean
+TARGET_DIRS_cleanall:
+	$(MAKE) -C TARGET_DIRS cleanall
+TARGET_DIRS_info:
+	$(MAKE) -C TARGET_DIRS info
+TARGET_DIRS_makefiles:
+	$(MAKE) -C TARGET_DIRS makefiles
+TARGET_DIRS:
+	$(MAKE) -C TARGET_DIRS all
+.PHONY: TARGET_DIRS_all TARGET_DIRS_debug TARGET_DIRS_smart TARGET_DIRS_release TARGET_DIRS_units TARGET_DIRS_examples TARGET_DIRS_shared TARGET_DIRS_install TARGET_DIRS_sourceinstall TARGET_DIRS_exampleinstall TARGET_DIRS_distinstall TARGET_DIRS_zipinstall TARGET_DIRS_zipsourceinstall TARGET_DIRS_zipexampleinstall TARGET_DIRS_zipdistinstall TARGET_DIRS_clean TARGET_DIRS_distclean TARGET_DIRS_cleanall TARGET_DIRS_info TARGET_DIRS_makefiles TARGET_DIRS
+endif
+ifdef TARGET_EXAMPLEDIRS_TARGET_EXAMPLEDIRS
+TARGET_EXAMPLEDIRS_all:
+	$(MAKE) -C TARGET_EXAMPLEDIRS all
+TARGET_EXAMPLEDIRS_debug:
+	$(MAKE) -C TARGET_EXAMPLEDIRS debug
+TARGET_EXAMPLEDIRS_smart:
+	$(MAKE) -C TARGET_EXAMPLEDIRS smart
+TARGET_EXAMPLEDIRS_release:
+	$(MAKE) -C TARGET_EXAMPLEDIRS release
+TARGET_EXAMPLEDIRS_units:
+	$(MAKE) -C TARGET_EXAMPLEDIRS units
+TARGET_EXAMPLEDIRS_examples:
+	$(MAKE) -C TARGET_EXAMPLEDIRS examples
+TARGET_EXAMPLEDIRS_shared:
+	$(MAKE) -C TARGET_EXAMPLEDIRS shared
+TARGET_EXAMPLEDIRS_install:
+	$(MAKE) -C TARGET_EXAMPLEDIRS install
+TARGET_EXAMPLEDIRS_sourceinstall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS sourceinstall
+TARGET_EXAMPLEDIRS_exampleinstall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS exampleinstall
+TARGET_EXAMPLEDIRS_distinstall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS distinstall
+TARGET_EXAMPLEDIRS_zipinstall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS zipinstall
+TARGET_EXAMPLEDIRS_zipsourceinstall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS zipsourceinstall
+TARGET_EXAMPLEDIRS_zipexampleinstall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS zipexampleinstall
+TARGET_EXAMPLEDIRS_zipdistinstall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS zipdistinstall
+TARGET_EXAMPLEDIRS_clean:
+	$(MAKE) -C TARGET_EXAMPLEDIRS clean
+TARGET_EXAMPLEDIRS_distclean:
+	$(MAKE) -C TARGET_EXAMPLEDIRS distclean
+TARGET_EXAMPLEDIRS_cleanall:
+	$(MAKE) -C TARGET_EXAMPLEDIRS cleanall
+TARGET_EXAMPLEDIRS_info:
+	$(MAKE) -C TARGET_EXAMPLEDIRS info
+TARGET_EXAMPLEDIRS_makefiles:
+	$(MAKE) -C TARGET_EXAMPLEDIRS makefiles
+TARGET_EXAMPLEDIRS:
+	$(MAKE) -C TARGET_EXAMPLEDIRS all
+.PHONY: TARGET_EXAMPLEDIRS_all TARGET_EXAMPLEDIRS_debug TARGET_EXAMPLEDIRS_smart TARGET_EXAMPLEDIRS_release TARGET_EXAMPLEDIRS_units TARGET_EXAMPLEDIRS_examples TARGET_EXAMPLEDIRS_shared TARGET_EXAMPLEDIRS_install TARGET_EXAMPLEDIRS_sourceinstall TARGET_EXAMPLEDIRS_exampleinstall TARGET_EXAMPLEDIRS_distinstall TARGET_EXAMPLEDIRS_zipinstall TARGET_EXAMPLEDIRS_zipsourceinstall TARGET_EXAMPLEDIRS_zipexampleinstall TARGET_EXAMPLEDIRS_zipdistinstall TARGET_EXAMPLEDIRS_clean TARGET_EXAMPLEDIRS_distclean TARGET_EXAMPLEDIRS_cleanall TARGET_EXAMPLEDIRS_info TARGET_EXAMPLEDIRS_makefiles TARGET_EXAMPLEDIRS
+endif
 all: fpc_all
 debug: fpc_debug
 smart: fpc_smart

rtl/embedded/Makefile.fpc

@@ -49,7 +49,7 @@ SYSINIT_UNITS=
 
 ifeq ($(ARCH),arm)
 ifeq ($(SUBARCH),armv7m)
-CPU_UNITS=lm3fury lm3tempest stm32f103 lpc1768 # thumb2_bare
+CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 # thumb2_bare
 endif
 ifeq ($(SUBARCH),armv4t)
 CPU_UNITS=lpc21x4 at91sam7x256 sc32442b

rtl/embedded/arm/cortexm3_start.inc

@@ -0,0 +1,52 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+   b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+  ldr r1,.L_etext
+  ldr r2,.L_data
+  ldr r3,.L_edata
+.Lcopyloop:
+  cmp r2,r3
+  ittt ls
+  ldrls r0,[r1],#4
+  strls r0,[r2],#4
+  bls .Lcopyloop
+
+  // clear onboard ram
+  ldr r1,.L_bss_start
+  ldr r2,.L_bss_end
+  mov r0,#0
+.Lzeroloop:
+  cmp r1,r2
+  itt ls
+  strls r0,[r1],#4
+  bls .Lzeroloop
+
+  bl PASCALMAIN
+  b HaltProc
+
+.L_bss_start:
+  .long _bss_start
+.L_bss_end:
+  .long _bss_end
+.L_etext:
+  .long _etext
+.L_data:
+  .long _data
+.L_edata:
+  .long _edata
+end;

rtl/embedded/arm/lm3fury.pp

@@ -61,234 +61,211 @@ unit lm3fury;
       rcgc1			:dword absolute (sysconoffset+$104);
       rcgc2			:dword absolute (sysconoffset+$108);
 
-
-    var
-      NMI_Handler,
-      HardFault_Handler,
-      MemManage_Handler,
-      BusFault_Handler,
-      UsageFault_Handler,
-      SWI_Handler,
-      DebugMonitor_Handler,
-      PendingSV_Handler,
-      Systick_Handler,UART0intvector: pointer;
-	
   implementation
 
-    var
-      _data: record end; external name '_data';
-      _edata: record end; external name '_edata';
-      _etext: record end; external name '_etext';
-      _bss_start: record end; external name '_bss_start';
-      _bss_end: record end; external name '_bss_end';
-      _stack_top: record end; external name '_stack_top';
-
-    procedure PASCALMAIN; external name 'PASCALMAIN';
-
-    procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
-      asm
-        .Lhalt:
-	  b .Lhalt
-      end;
-
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure GPIO_Port_A_Interrupt; external name 'GPIO_Port_A_Interrupt';
+procedure GPIO_Port_B_Interrupt; external name 'GPIO_Port_B_Interrupt';
+procedure GPIO_Port_C_Interrupt; external name 'GPIO_Port_C_Interrupt';
+procedure GPIO_Port_D_Interrupt; external name 'GPIO_Port_D_Interrupt';
+procedure GPIO_Port_E_Interrupt; external name 'GPIO_Port_E_Interrupt';
+procedure UART0_Interrupt; external name 'UART0_Interrupt';
+procedure UART1_Interrupt; external name 'UART1_Interrupt';
+procedure SSI0_Interrupt; external name 'SSI0_Interrupt';
+procedure I2C0_Interrupt; external name 'I2C0_Interrupt';
+procedure ADC0_Sequence_0_Interrupt; external name 'ADC0_Sequence_0_Interrupt';
+procedure ADC0_Sequence_1_Interrupt; external name 'ADC0_Sequence_1_Interrupt';
+procedure ADC0_Sequence_2_Interrupt; external name 'ADC0_Sequence_2_Interrupt';
+procedure ADC0_Sequence_3_Interrupt; external name 'ADC0_Sequence_3_Interrupt';
+procedure Watchdog_Timer_0_Interrupt; external name 'Watchdog_Timer_0_Interrupt';
+procedure Timer_0A_Interrupt; external name 'Timer_0A_Interrupt';
+procedure Timer_0B_Interrupt; external name 'Timer_0B_Interrupt';
+procedure Timer_1A_Interrupt; external name 'Timer_1A_Interrupt';
+procedure Timer_1B_Interrupt; external name 'Timer_1B_Interrupt';
+procedure Timer_2A_Interrupt; external name 'Timer_2A_Interrupt';
+procedure Timer_2B_Interrupt; external name 'Timer_2B_Interrupt';
+procedure Analog_Comparator_0_Interrupt; external name 'Analog_Comparator_0_Interrupt';
+procedure Analog_Comparator_1_Interrupt; external name 'Analog_Comparator_1_Interrupt';
+procedure Analog_Comparator_2_Interrupt; external name 'Analog_Comparator_2_Interrupt';
+procedure System_Control_Interrupt; external name 'System_Control_Interrupt';
+procedure Flash_Memory_Control_Interrupt; external name 'Flash_Memory_Control_Interrupt';
+procedure GPIO_Port_F_Interrupt; external name 'GPIO_Port_F_Interrupt';
+procedure GPIO_Port_G_Interrupt; external name 'GPIO_Port_G_Interrupt';
+procedure GPIO_Port_H_Interrupt; external name 'GPIO_Port_H_Interrupt';
+procedure UART2_Interrupt; external name 'UART2_Interrupt';
+procedure SSI1_Interrupt; external name 'SSI1_Interrupt';
+procedure Timer_3A_Interrupt; external name 'Timer_3A_Interrupt';
+procedure Timer_3B_Interrupt; external name 'Timer_3B_Interrupt';
+procedure I2C1_Interrupt; external name 'I2C1_Interrupt';
+procedure Hibernation_Module_Interrupt; external name 'Hibernation_Module_Interrupt';
 
-    procedure _FPC_start; assembler; nostackframe;
-      label
-        _start;
-      asm
-	.init
-	.align 16
-	
-	.long _stack_top	 			// First entry in NVIC table is the new stack pointer
-	.long _start+1         //gjb changed from stm32f version to avoid invstate error when interrupt fires
-	//b   _start					// Reset
-	.long _start+1
-	//b	 .LNMI_Addr				// Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
-	.long _start+1
-	//b	 .LHardFault_Addr		// All class of fault
-	.long _start+1
-	//b	 .LMemManage_Addr		// Memory management
-	.long _start+1
-	//b	 .LBusFault_Addr		// Pre-fetch fault, memory access fault
-	.long _start+1
-	//b	 .LUsageFault_Addr	// Undefined instruction or illegal state
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//b	 .LSWI_Addr				// Software Interrupt vector now SVC
-	.long _start+1
-	//b	 .LDebugMonitor_Addr	// Debug Monitor
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//b	 .LPendingSV_Addr		//	Pendable request for system service
-	.long _start+1
-	//b	 .LSystick_Addr		// System tick timer
-	//16
-	.long .LDefaultHandler+1     //GPIOA  #0
-	.long .LDefaultHandler+1     //GPIOB
-	.long .LDefaultHandler+1     //GPIOC
-	.long .LDefaultHandler+1     //GPIOD
-	.long .LDefaultHandler+1     //GPIOE
-	.long .LUART0handler+1       //.LDefaultHandler+1     //UART0
-	.long .LDefaultHandler+1     //UART1
-	.long .LDefaultHandler+1     //SSI0
-	//24
-	.long .LDefaultHandler+1     //I2C0   #8
-	.long .LDefaultHandler+1     //PWMF
-	.long .LDefaultHandler+1     //PWMG0
-	.long .LDefaultHandler+1     //PWMG1
-	.long .LDefaultHandler+1     //PWMG2
-	.long .LDefaultHandler+1     //QEI0
-	.long .LDefaultHandler+1     //ADC0S0
-	.long .LDefaultHandler+1     //ADC0S1
-	//32
-	.long .LDefaultHandler+1     //ADC0S2 #16
-	.long .LDefaultHandler+1     //ADC0S3
-	.long .LDefaultHandler+1     //WDGTimer01
-	.long .LDefaultHandler+1     //T0A
-	.long .LDefaultHandler+1     //T0B
-	.long .LDefaultHandler+1     //T1A
-	.long .LDefaultHandler+1     //T1B
-	.long .LDefaultHandler+1     //T2A
-	//40
-	.long .LDefaultHandler+1     //T2B    #24
-	.long .LDefaultHandler+1     //COMP0
-	.long .LDefaultHandler+1     //COMP1
-	.long .LDefaultHandler+1     //COMP2
-	.long .LDefaultHandler+1     //SYSCON
-	.long .LDefaultHandler+1     //FLASH
-	.long .LDefaultHandler+1     //GPIOF
-	.long .LDefaultHandler+1     //GPIOG
-	//48
-	.long .LDefaultHandler+1     //GPIOH  #32
-	.long .LDefaultHandler+1     //UART2
-	.long .LDefaultHandler+1     //SSI1
-	.long .LDefaultHandler+1     //T3A
-	.long .LDefaultHandler+1     //T3B
-	.long .LDefaultHandler+1     //I2C1
-	.long .LDefaultHandler+1     //QEI1
-	.long .LDefaultHandler+1     //CAN0
-	//56
-	.long .LDefaultHandler+1     //CAN1   #40
-	.long .LDefaultHandler+1     //res
-	.long .LDefaultHandler+1     //ETH
-	.long .LDefaultHandler+1     //res
-	.long .LDefaultHandler+1     //USB
-	.long .LDefaultHandler+1     //PWMG3
-	.long .LDefaultHandler+1     //UDMAS
-	.long .LDefaultHandler+1     //UDMAE
-	//64
-	.long .LDefaultHandler+1     //ADC1S0 #48
-	.long .LDefaultHandler+1     //ADC1S1
-	.long .LDefaultHandler+1     //ADC1S2
-	.long .LDefaultHandler+1     //ADC1S3
-	.long .LDefaultHandler+1     //I2S0
-	.long .LDefaultHandler+1     //EPI
-	.long .LDefaultHandler+1     //GPIOJ
-	.long .LDefaultHandler+1     //res    #55
+{$i cortexm3_start.inc}
 
-.LNMI_Addr:
-	ldr r0,.L1
-	ldr pc,[r0]
-.LHardFault_Addr:
-	ldr r0,.L2
-	ldr pc,[r0]
-.LMemManage_Addr:
-	ldr r0,.L3
-	ldr pc,[r0]
-.LBusFault_Addr:
-	ldr r0,.L4
-	ldr pc,[r0]
-.LUsageFault_Addr:
-	ldr r0,.L5
-	ldr pc,[r0]
-.LSWI_Addr:
-	ldr r0,.L6
-	ldr pc,[r0]
-.LDebugMonitor_Addr:
-	ldr r0,.L7
-	ldr pc,[r0]
-.LPendingSV_Addr:
-	ldr r0,.L8
-	ldr pc,[r0]
-.LSystick_Addr:
-	ldr r0,.L9
-	ldr pc,[r0]
-.LUART0handler:
-  ldr r0,.L10
-  ldr pc,[r0]
-.L1:
-	.long NMI_Handler
-.L2:
-	.long HardFault_Handler
-.L3:
-	.long MemManage_Handler
-.L4:
-	.long BusFault_Handler
-.L5:
-	.long UsageFault_Handler
-.L6:
-	.long SWI_Handler
-.L7:
-	.long DebugMonitor_Handler
-.L8:
-	.long PendingSV_Handler
-.L9:
-	.long Systick_Handler   
-.L10:
-  .long UART0IntVector
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+  .section ".init.interrupt_vectors"
+interrupt_vectors:
+	.long _stack_top
+  .long Startup
+  .long NMI_interrupt
+  .long Hardfault_interrupt
+  .long MemManage_interrupt
+  .long BusFault_interrupt
+  .long UsageFault_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long SWI_interrupt
+  .long DebugMonitor_interrupt
+  .long 0
+  .long PendingSV_interrupt
+  .long SysTick_interrupt
   
-	.globl _start
-	.text
-_start:
-	
-	// Copy initialized data to ram
-	ldr r1,.L_etext
-	ldr r2,.L_data
-	ldr r3,.L_edata
-.Lcopyloop:
-	cmp r2,r3
-	ittt ls
-	ldrls r0,[r1],#4
-	strls r0,[r2],#4
-	bls .Lcopyloop
-
-	// clear onboard ram
-	ldr r1,.L_bss_start
-	ldr r2,.L_bss_end
-	mov r0,#0
-.Lzeroloop:
-	cmp r1,r2
-	itt ls
-	strls r0,[r1],#4
-	bls .Lzeroloop
-
-	b PASCALMAIN
-	b _FPC_haltproc
-
-.L_bss_start:
-	.long _bss_start
-.L_bss_end:
-	.long _bss_end
-.L_etext:
-	.long _etext
-.L_data:
-	.long _data
-.L_edata:
-	.long _edata
-.LDefaultHandlerAddr:
-	.long .LDefaultHandler
-	// default irq handler just returns
-.LDefaultHandler:
-	mov pc,r14
-    end;
+  .long GPIO_Port_A_Interrupt
+  .long GPIO_Port_B_Interrupt
+  .long GPIO_Port_C_Interrupt
+  .long GPIO_Port_D_Interrupt
+  .long GPIO_Port_E_Interrupt
+  .long UART0_Interrupt
+  .long UART1_Interrupt
+  .long SSI0_Interrupt
+  .long I2C0_Interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long ADC0_Sequence_0_Interrupt
+  .long ADC0_Sequence_1_Interrupt
+  .long ADC0_Sequence_2_Interrupt
+  .long ADC0_Sequence_3_Interrupt
+  .long Watchdog_Timer_0_Interrupt
+  .long Timer_0A_Interrupt
+  .long Timer_0B_Interrupt
+  .long Timer_1A_Interrupt
+  .long Timer_1B_Interrupt
+  .long Timer_2A_Interrupt
+  .long Timer_2B_Interrupt
+  .long Analog_Comparator_0_Interrupt
+  .long Analog_Comparator_1_Interrupt
+  .long Analog_Comparator_2_Interrupt
+  .long System_Control_Interrupt
+  .long Flash_Memory_Control_Interrupt
+  .long GPIO_Port_F_Interrupt
+  .long GPIO_Port_G_Interrupt
+  .long GPIO_Port_H_Interrupt
+  .long UART2_Interrupt
+  .long SSI1_Interrupt
+  .long Timer_3A_Interrupt
+  .long Timer_3B_Interrupt
+  .long I2C1_Interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long Hibernation_Module_Interrupt
+  
+  .weak NMI_interrupt
+  .weak Hardfault_interrupt
+  .weak MemManage_interrupt
+  .weak BusFault_interrupt
+  .weak UsageFault_interrupt
+  .weak SWI_interrupt
+  .weak DebugMonitor_interrupt
+  .weak PendingSV_interrupt
+  .weak SysTick_interrupt
+  .weak GPIO_Port_A_Interrupt
+  .weak GPIO_Port_B_Interrupt
+  .weak GPIO_Port_C_Interrupt
+  .weak GPIO_Port_D_Interrupt
+  .weak GPIO_Port_E_Interrupt
+  .weak UART0_Interrupt
+  .weak UART1_Interrupt
+  .weak SSI0_Interrupt
+  .weak I2C0_Interrupt
+  .weak ADC0_Sequence_0_Interrupt
+  .weak ADC0_Sequence_1_Interrupt
+  .weak ADC0_Sequence_2_Interrupt
+  .weak ADC0_Sequence_3_Interrupt
+  .weak Watchdog_Timer_0_Interrupt
+  .weak Timer_0A_Interrupt
+  .weak Timer_0B_Interrupt
+  .weak Timer_1A_Interrupt
+  .weak Timer_1B_Interrupt
+  .weak Timer_2A_Interrupt
+  .weak Timer_2B_Interrupt
+  .weak Analog_Comparator_0_Interrupt
+  .weak Analog_Comparator_1_Interrupt
+  .weak Analog_Comparator_2_Interrupt
+  .weak System_Control_Interrupt
+  .weak Flash_Memory_Control_Interrupt
+  .weak GPIO_Port_F_Interrupt
+  .weak GPIO_Port_G_Interrupt
+  .weak GPIO_Port_H_Interrupt
+  .weak UART2_Interrupt
+  .weak SSI1_Interrupt
+  .weak Timer_3A_Interrupt
+  .weak Timer_3B_Interrupt
+  .weak I2C1_Interrupt
+  .weak Hibernation_Module_Interrupt
+  
+  .set NMI_interrupt, Startup
+  .set Hardfault_interrupt, Startup
+  .set MemManage_interrupt, Startup
+  .set BusFault_interrupt, Startup
+  .set UsageFault_interrupt, Startup
+  .set SWI_interrupt, Startup
+  .set DebugMonitor_interrupt, Startup
+  .set PendingSV_interrupt, Startup
+  .set SysTick_interrupt, Startup
+  .set GPIO_Port_A_Interrupt, Startup
+  .set GPIO_Port_B_Interrupt, Startup
+  .set GPIO_Port_C_Interrupt, Startup
+  .set GPIO_Port_D_Interrupt, Startup
+  .set GPIO_Port_E_Interrupt, Startup
+  .set UART0_Interrupt, Startup
+  .set UART1_Interrupt, Startup
+  .set SSI0_Interrupt, Startup
+  .set I2C0_Interrupt, Startup
+  .set ADC0_Sequence_0_Interrupt, Startup
+  .set ADC0_Sequence_1_Interrupt, Startup
+  .set ADC0_Sequence_2_Interrupt, Startup
+  .set ADC0_Sequence_3_Interrupt, Startup
+  .set Watchdog_Timer_0_Interrupt, Startup
+  .set Timer_0A_Interrupt, Startup
+  .set Timer_0B_Interrupt, Startup
+  .set Timer_1A_Interrupt, Startup
+  .set Timer_1B_Interrupt, Startup
+  .set Timer_2A_Interrupt, Startup
+  .set Timer_2B_Interrupt, Startup
+  .set Analog_Comparator_0_Interrupt, Startup
+  .set Analog_Comparator_1_Interrupt, Startup
+  .set Analog_Comparator_2_Interrupt, Startup
+  .set System_Control_Interrupt, Startup
+  .set Flash_Memory_Control_Interrupt, Startup
+  .set GPIO_Port_F_Interrupt, Startup
+  .set GPIO_Port_G_Interrupt, Startup
+  .set GPIO_Port_H_Interrupt, Startup
+  .set UART2_Interrupt, Startup
+  .set SSI1_Interrupt, Startup
+  .set Timer_3A_Interrupt, Startup
+  .set Timer_3B_Interrupt, Startup
+  .set I2C1_Interrupt, Startup
+  .set Hibernation_Module_Interrupt, Startup
+  
+  .text
+end;
 
 end.
 

rtl/embedded/arm/lm3tempest.pp

@@ -60,238 +60,273 @@ unit lm3tempest;
       rcgc0			:dword absolute (sysconoffset+$100);
       rcgc1			:dword absolute (sysconoffset+$104);
       rcgc2			:dword absolute (sysconoffset+$108);
-
-
-    var
-      NMI_Handler,
-      HardFault_Handler,
-      MemManage_Handler,
-      BusFault_Handler,
-      UsageFault_Handler,
-      SWI_Handler,
-      DebugMonitor_Handler,
-      PendingSV_Handler,
-      Systick_Handler,UART0intvector: pointer;
 	
   implementation
 
-    var
-      _data: record end; external name '_data';
-      _edata: record end; external name '_edata';
-      _etext: record end; external name '_etext';
-      _bss_start: record end; external name '_bss_start';
-      _bss_end: record end; external name '_bss_end';
-      _stack_top: record end; external name '_stack_top';
-
-    procedure PASCALMAIN; external name 'PASCALMAIN';
-
-    procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
-      asm
-        .Lhalt:
-	  b .Lhalt
-      end;
-
-
-    procedure _FPC_start; assembler; nostackframe;
-      label
-        _start;
-      asm
-	.init
-	.align 16
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure GPIO_Port_A_Interrupt; external name 'GPIO_Port_A_Interrupt';
+procedure GPIO_Port_B_Interrupt; external name 'GPIO_Port_B_Interrupt';
+procedure GPIO_Port_C_Interrupt; external name 'GPIO_Port_C_Interrupt';
+procedure GPIO_Port_D_Interrupt; external name 'GPIO_Port_D_Interrupt';
+procedure GPIO_Port_E_Interrupt; external name 'GPIO_Port_E_Interrupt';
+procedure UART0_Interrupt; external name 'UART0_Interrupt';
+procedure UART1_Interrupt; external name 'UART1_Interrupt';
+procedure SSI0_Interrupt; external name 'SSI0_Interrupt';
+procedure I2C0_Interrupt; external name 'I2C0_Interrupt';
+procedure PWM_Fault_Interrupt; external name 'PWM_Fault_Interrupt';
+procedure PWM_Generator_0_Interrupt; external name 'PWM_Generator_0_Interrupt';
+procedure PWM_Generator_1_Interrupt; external name 'PWM_Generator_1_Interrupt';
+procedure PWM_Generator_2_Interrupt; external name 'PWM_Generator_2_Interrupt';
+procedure QEI0_Interrupt; external name 'QEI0_Interrupt';
+procedure ADC0_Sequence_0_Interrupt; external name 'ADC0_Sequence_0_Interrupt';
+procedure ADC0_Sequence_1_Interrupt; external name 'ADC0_Sequence_1_Interrupt';
+procedure ADC0_Sequence_2_Interrupt; external name 'ADC0_Sequence_2_Interrupt';
+procedure ADC0_Sequence_3_Interrupt; external name 'ADC0_Sequence_3_Interrupt';
+procedure Watchdog_Timers_0_and_1_Interrupt; external name 'Watchdog_Timers_0_and_1_Interrupt';
+procedure Timer_0A_Interrupt; external name 'Timer_0A_Interrupt';
+procedure Timer_0B_Interrupt; external name 'Timer_0B_Interrupt';
+procedure Timer_1A_Interrupt; external name 'Timer_1A_Interrupt';
+procedure Timer_1B_Interrupt; external name 'Timer_1B_Interrupt';
+procedure Timer_2A_Interrupt; external name 'Timer_2A_Interrupt';
+procedure Timer_2B_Interrupt; external name 'Timer_2B_Interrupt';
+procedure Analog_Comparator_0_Interrupt; external name 'Analog_Comparator_0_Interrupt';
+procedure Analog_Comparator_1_Interrupt; external name 'Analog_Comparator_1_Interrupt';
+procedure System_Control_Interrupt; external name 'System_Control_Interrupt';
+procedure Flash_Memory_Control_Interrupt; external name 'Flash_Memory_Control_Interrupt';
+procedure GPIO_Port_F_Interrupt; external name 'GPIO_Port_F_Interrupt';
+procedure GPIO_Port_G_Interrupt; external name 'GPIO_Port_G_Interrupt';
+procedure GPIO_Port_H_Interrupt; external name 'GPIO_Port_H_Interrupt';
+procedure UART2_Interrupt; external name 'UART2_Interrupt';
+procedure SSI1_Interrupt; external name 'SSI1_Interrupt';
+procedure Timer_3A_Interrupt; external name 'Timer_3A_Interrupt';
+procedure Timer_3B_Interrupt; external name 'Timer_3B_Interrupt';
+procedure I2C1_Interrupt; external name 'I2C1_Interrupt';
+procedure QEI1_Interrupt; external name 'QEI1_Interrupt';
+procedure CAN0_Interrupt; external name 'CAN0_Interrupt';
+procedure CAN1_Interrupt; external name 'CAN1_Interrupt';
+procedure Hibernation_Module_Interrupt; external name 'Hibernation_Module_Interrupt';
+procedure USB_Interrupt; external name 'USB_Interrupt';
+procedure uDMA_Software_Interrupt; external name 'uDMA_Software_Interrupt';
+procedure uDMA_Error_Interrupt; external name 'uDMA_Error_Interrupt';
+procedure ADC1_Sequence_0_Interrupt; external name 'ADC1_Sequence_0_Interrupt';
+procedure ADC1_Sequence_1_Interrupt; external name 'ADC1_Sequence_1_Interrupt';
+procedure ADC1_Sequence_2_Interrupt; external name 'ADC1_Sequence_2_Interrupt';
+procedure ADC1_Sequence_3_Interrupt; external name 'ADC1_Sequence_3_Interrupt';
+procedure I2S0_Interrupt; external name 'I2S0_Interrupt';
+procedure GPIO_Port_J_Interrupt; external name 'GPIO_Port_J_Interrupt';
 
-	// JEC NOTE: CONFIRMED AUG 2011 - address must manually have offset
-	//        the assembler / linker will NOT automatically add the LSB
-        //	  failure to have the LSB prevents coming up in Thumb2 mode
-	.long _stack_top	 			// First entry in NVIC table is the new stack pointer
-	.long _start+1         //gjb changed from stm32f version to avoid invstate error when interrupt fires
-	//b   _start					// Reset
-	.long _start+1
-	//b	 .LNMI_Addr				// Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
-	.long _start+1
-	//b	 .LHardFault_Addr		// All class of fault
-	.long _start+1
-	//b	 .LMemManage_Addr		// Memory management
-	.long _start+1
-	//b	 .LBusFault_Addr		// Pre-fetch fault, memory access fault
-	.long _start+1
-	//b	 .LUsageFault_Addr	// Undefined instruction or illegal state
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//b	 .LSWI_Addr				// Software Interrupt vector now SVC
-	.long _start+1
-	//b	 .LDebugMonitor_Addr	// Debug Monitor
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//b	 .LPendingSV_Addr		//	Pendable request for system service
-	.long _start+1
-	//b	 .LSystick_Addr		// System tick timer
-	//16
-	.long .LDefaultHandler+1     //GPIOA  #0
-	.long .LDefaultHandler+1     //GPIOB
-	.long .LDefaultHandler+1     //GPIOC
-	.long .LDefaultHandler+1     //GPIOD
-	.long .LDefaultHandler+1     //GPIOE
-	.long .LUART0handler+1       //.LDefaultHandler+1     //UART0
-	.long .LDefaultHandler+1     //UART1
-	.long .LDefaultHandler+1     //SSI0
-	//24
-	.long .LDefaultHandler+1     //I2C0   #8
-	.long .LDefaultHandler+1     //PWMF
-	.long .LDefaultHandler+1     //PWMG0
-	.long .LDefaultHandler+1     //PWMG1
-	.long .LDefaultHandler+1     //PWMG2
-	.long .LDefaultHandler+1     //QEI0
-	.long .LDefaultHandler+1     //ADC0S0
-	.long .LDefaultHandler+1     //ADC0S1
-	//32
-	.long .LDefaultHandler+1     //ADC0S2 #16
-	.long .LDefaultHandler+1     //ADC0S3
-	.long .LDefaultHandler+1     //WDGTimer01
-	.long .LDefaultHandler+1     //T0A
-	.long .LDefaultHandler+1     //T0B
-	.long .LDefaultHandler+1     //T1A
-	.long .LDefaultHandler+1     //T1B
-	.long .LDefaultHandler+1     //T2A
-	//40
-	.long .LDefaultHandler+1     //T2B    #24
-	.long .LDefaultHandler+1     //COMP0
-	.long .LDefaultHandler+1     //COMP1
-	.long .LDefaultHandler+1     //COMP2
-	.long .LDefaultHandler+1     //SYSCON
-	.long .LDefaultHandler+1     //FLASH
-	.long .LDefaultHandler+1     //GPIOF
-	.long .LDefaultHandler+1     //GPIOG
-	//48
-	.long .LDefaultHandler+1     //GPIOH  #32
-	.long .LDefaultHandler+1     //UART2
-	.long .LDefaultHandler+1     //SSI1
-	.long .LDefaultHandler+1     //T3A
-	.long .LDefaultHandler+1     //T3B
-	.long .LDefaultHandler+1     //I2C1
-	.long .LDefaultHandler+1     //QEI1
-	.long .LDefaultHandler+1     //CAN0
-	//56
-	.long .LDefaultHandler+1     //CAN1   #40
-	.long .LDefaultHandler+1     //res
-	.long .LDefaultHandler+1     //ETH
-	.long .LDefaultHandler+1     //res
-	.long .LDefaultHandler+1     //USB
-	.long .LDefaultHandler+1     //PWMG3
-	.long .LDefaultHandler+1     //UDMAS
-	.long .LDefaultHandler+1     //UDMAE
-	//64
-	.long .LDefaultHandler+1     //ADC1S0 #48
-	.long .LDefaultHandler+1     //ADC1S1
-	.long .LDefaultHandler+1     //ADC1S2
-	.long .LDefaultHandler+1     //ADC1S3
-	.long .LDefaultHandler+1     //I2S0
-	.long .LDefaultHandler+1     //EPI
-	.long .LDefaultHandler+1     //GPIOJ
-	.long .LDefaultHandler+1     //res    #55
+{$i cortexm3_start.inc}
 
-.LNMI_Addr:
-	ldr r0,.L1
-	ldr pc,[r0]
-.LHardFault_Addr:
-	ldr r0,.L2
-	ldr pc,[r0]
-.LMemManage_Addr:
-	ldr r0,.L3
-	ldr pc,[r0]
-.LBusFault_Addr:
-	ldr r0,.L4
-	ldr pc,[r0]
-.LUsageFault_Addr:
-	ldr r0,.L5
-	ldr pc,[r0]
-.LSWI_Addr:
-	ldr r0,.L6
-	ldr pc,[r0]
-.LDebugMonitor_Addr:
-	ldr r0,.L7
-	ldr pc,[r0]
-.LPendingSV_Addr:
-	ldr r0,.L8
-	ldr pc,[r0]
-.LSystick_Addr:
-	ldr r0,.L9
-	ldr pc,[r0]
-.LUART0handler:
-  ldr r0,.L10
-  ldr pc,[r0]
-.L1:
-	.long NMI_Handler
-.L2:
-	.long HardFault_Handler
-.L3:
-	.long MemManage_Handler
-.L4:
-	.long BusFault_Handler
-.L5:
-	.long UsageFault_Handler
-.L6:
-	.long SWI_Handler
-.L7:
-	.long DebugMonitor_Handler
-.L8:
-	.long PendingSV_Handler
-.L9:
-	.long Systick_Handler   
-.L10:
-  .long UART0IntVector
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+  .section ".init.interrupt_vectors"
+interrupt_vectors:
+	.long _stack_top
+  .long Startup
+  .long NMI_interrupt
+  .long Hardfault_interrupt
+  .long MemManage_interrupt
+  .long BusFault_interrupt
+  .long UsageFault_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long SWI_interrupt
+  .long DebugMonitor_interrupt
+  .long 0
+  .long PendingSV_interrupt
+  .long SysTick_interrupt
   
-	.globl _start
-	.text
-_start:
-	
-	// Copy initialized data to ram
-	ldr r1,.L_etext
-	ldr r2,.L_data
-	ldr r3,.L_edata
-.Lcopyloop:
-	cmp r2,r3
-	ittt ls
-	ldrls r0,[r1],#4
-	strls r0,[r2],#4
-	bls .Lcopyloop
-
-	// clear onboard ram
-	ldr r1,.L_bss_start
-	ldr r2,.L_bss_end
-	mov r0,#0
-.Lzeroloop:
-	cmp r1,r2
-	itt ls
-	strls r0,[r1],#4
-	bls .Lzeroloop
+  .long GPIO_Port_A_Interrupt
+  .long GPIO_Port_B_Interrupt
+  .long GPIO_Port_C_Interrupt
+  .long GPIO_Port_D_Interrupt
+  .long GPIO_Port_E_Interrupt
+  .long UART0_Interrupt
+  .long UART1_Interrupt
+  .long SSI0_Interrupt
+  .long I2C0_Interrupt
+  .long PWM_Fault_Interrupt
+  .long PWM_Generator_0_Interrupt
+  .long PWM_Generator_1_Interrupt
+  .long PWM_Generator_2_Interrupt
+  .long QEI0_Interrupt
+  .long ADC0_Sequence_0_Interrupt
+  .long ADC0_Sequence_1_Interrupt
+  .long ADC0_Sequence_2_Interrupt
+  .long ADC0_Sequence_3_Interrupt
+  .long Watchdog_Timers_0_and_1_Interrupt
+  .long Timer_0A_Interrupt
+  .long Timer_0B_Interrupt
+  .long Timer_1A_Interrupt
+  .long Timer_1B_Interrupt
+  .long Timer_2A_Interrupt
+  .long Timer_2B_Interrupt
+  .long Analog_Comparator_0_Interrupt
+  .long Analog_Comparator_1_Interrupt
+  .long 0
+  .long System_Control_Interrupt
+  .long Flash_Memory_Control_Interrupt
+  .long GPIO_Port_F_Interrupt
+  .long GPIO_Port_G_Interrupt
+  .long GPIO_Port_H_Interrupt
+  .long UART2_Interrupt
+  .long SSI1_Interrupt
+  .long Timer_3A_Interrupt
+  .long Timer_3B_Interrupt
+  .long I2C1_Interrupt
+  .long QEI1_Interrupt
+  .long CAN0_Interrupt
+  .long CAN1_Interrupt
+  .long 0
+  .long 0
+  .long Hibernation_Module_Interrupt
+  .long USB_Interrupt
+  .long 0
+  .long uDMA_Software_Interrupt
+  .long uDMA_Error_Interrupt
+  .long ADC1_Sequence_0_Interrupt
+  .long ADC1_Sequence_1_Interrupt
+  .long ADC1_Sequence_2_Interrupt
+  .long ADC1_Sequence_3_Interrupt
+  .long I2S0_Interrupt
+  .long 0
+  .long GPIO_Port_J_Interrupt
+  
+  .weak NMI_interrupt
+  .weak Hardfault_interrupt
+  .weak MemManage_interrupt
+  .weak BusFault_interrupt
+  .weak UsageFault_interrupt
+  .weak SWI_interrupt
+  .weak DebugMonitor_interrupt
+  .weak PendingSV_interrupt
+  .weak SysTick_interrupt
 
-	b PASCALMAIN
-	b _FPC_haltproc
+  .weak GPIO_Port_A_Interrupt
+  .weak GPIO_Port_B_Interrupt
+  .weak GPIO_Port_C_Interrupt
+  .weak GPIO_Port_D_Interrupt
+  .weak GPIO_Port_E_Interrupt
+  .weak UART0_Interrupt
+  .weak UART1_Interrupt
+  .weak SSI0_Interrupt
+  .weak I2C0_Interrupt
+  .weak PWM_Fault_Interrupt
+  .weak PWM_Generator_0_Interrupt
+  .weak PWM_Generator_1_Interrupt
+  .weak PWM_Generator_2_Interrupt
+  .weak QEI0_Interrupt
+  .weak ADC0_Sequence_0_Interrupt
+  .weak ADC0_Sequence_1_Interrupt
+  .weak ADC0_Sequence_2_Interrupt
+  .weak ADC0_Sequence_3_Interrupt
+  .weak Watchdog_Timers_0_and_1_Interrupt
+  .weak Timer_0A_Interrupt
+  .weak Timer_0B_Interrupt
+  .weak Timer_1A_Interrupt
+  .weak Timer_1B_Interrupt
+  .weak Timer_2A_Interrupt
+  .weak Timer_2B_Interrupt
+  .weak Analog_Comparator_0_Interrupt
+  .weak Analog_Comparator_1_Interrupt
+  .weak System_Control_Interrupt
+  .weak Flash_Memory_Control_Interrupt
+  .weak GPIO_Port_F_Interrupt
+  .weak GPIO_Port_G_Interrupt
+  .weak GPIO_Port_H_Interrupt
+  .weak UART2_Interrupt
+  .weak SSI1_Interrupt
+  .weak Timer_3A_Interrupt
+  .weak Timer_3B_Interrupt
+  .weak I2C1_Interrupt
+  .weak QEI1_Interrupt
+  .weak CAN0_Interrupt
+  .weak CAN1_Interrupt
+  .weak Hibernation_Module_Interrupt
+  .weak USB_Interrupt
+  .weak uDMA_Software_Interrupt
+  .weak uDMA_Error_Interrupt
+  .weak ADC1_Sequence_0_Interrupt
+  .weak ADC1_Sequence_1_Interrupt
+  .weak ADC1_Sequence_2_Interrupt
+  .weak ADC1_Sequence_3_Interrupt
+  .weak I2S0_Interrupt
+  .weak GPIO_Port_J_Interrupt
+  
+  .set NMI_interrupt, Startup
+  .set Hardfault_interrupt, Startup
+  .set MemManage_interrupt, Startup
+  .set BusFault_interrupt, Startup
+  .set UsageFault_interrupt, Startup
+  .set SWI_interrupt, Startup
+  .set DebugMonitor_interrupt, Startup
+  .set PendingSV_interrupt, Startup
+  .set SysTick_interrupt, Startup
 
-.L_bss_start:
-	.long _bss_start
-.L_bss_end:
-	.long _bss_end
-.L_etext:
-	.long _etext
-.L_data:
-	.long _data
-.L_edata:
-	.long _edata
-.LDefaultHandlerAddr:
-	.long .LDefaultHandler
-	// default irq handler just returns
-.LDefaultHandler:
-	mov pc,r14
-    end;
+  .set GPIO_Port_A_Interrupt, Startup
+  .set GPIO_Port_B_Interrupt, Startup
+  .set GPIO_Port_C_Interrupt, Startup
+  .set GPIO_Port_D_Interrupt, Startup
+  .set GPIO_Port_E_Interrupt, Startup
+  .set UART0_Interrupt, Startup
+  .set UART1_Interrupt, Startup
+  .set SSI0_Interrupt, Startup
+  .set I2C0_Interrupt, Startup
+  .set PWM_Fault_Interrupt, Startup
+  .set PWM_Generator_0_Interrupt, Startup
+  .set PWM_Generator_1_Interrupt, Startup
+  .set PWM_Generator_2_Interrupt, Startup
+  .set QEI0_Interrupt, Startup
+  .set ADC0_Sequence_0_Interrupt, Startup
+  .set ADC0_Sequence_1_Interrupt, Startup
+  .set ADC0_Sequence_2_Interrupt, Startup
+  .set ADC0_Sequence_3_Interrupt, Startup
+  .set Watchdog_Timers_0_and_1_Interrupt, Startup
+  .set Timer_0A_Interrupt, Startup
+  .set Timer_0B_Interrupt, Startup
+  .set Timer_1A_Interrupt, Startup
+  .set Timer_1B_Interrupt, Startup
+  .set Timer_2A_Interrupt, Startup
+  .set Timer_2B_Interrupt, Startup
+  .set Analog_Comparator_0_Interrupt, Startup
+  .set Analog_Comparator_1_Interrupt, Startup
+  .set System_Control_Interrupt, Startup
+  .set Flash_Memory_Control_Interrupt, Startup
+  .set GPIO_Port_F_Interrupt, Startup
+  .set GPIO_Port_G_Interrupt, Startup
+  .set GPIO_Port_H_Interrupt, Startup
+  .set UART2_Interrupt, Startup
+  .set SSI1_Interrupt, Startup
+  .set Timer_3A_Interrupt, Startup
+  .set Timer_3B_Interrupt, Startup
+  .set I2C1_Interrupt, Startup
+  .set QEI1_Interrupt, Startup
+  .set CAN0_Interrupt, Startup
+  .set CAN1_Interrupt, Startup
+  .set Hibernation_Module_Interrupt, Startup
+  .set USB_Interrupt, Startup
+  .set uDMA_Software_Interrupt, Startup
+  .set uDMA_Error_Interrupt, Startup
+  .set ADC1_Sequence_0_Interrupt, Startup
+  .set ADC1_Sequence_1_Interrupt, Startup
+  .set ADC1_Sequence_2_Interrupt, Startup
+  .set ADC1_Sequence_3_Interrupt, Startup
+  .set I2S0_Interrupt, Startup
+  .set GPIO_Port_J_Interrupt, Startup
+  
+  .text
+end;
 
 end.
 

rtl/embedded/arm/lpc1768.pp

@@ -6,153 +6,1220 @@ unit lpc1768;
 
 interface
 
-var
-    STCTRL   : DWord absolute $E000E010;
-    STRELOAD : DWord absolute $E000E014;
-    STCURR   : DWord absolute $E000E018;
-
-    FIO1DIR2 : Byte  absolute $2009C022;
-    FIO1SET2 : Byte  absolute $2009C03A;
-    FIO1CLR2 : Byte  absolute $2009C03E;
-
-    SCS      : DWord absolute $400FC1A0;
-    CLKSRCSEL: DWord absolute $400FC10C;
-    PLL0FEED : DWord absolute $400FC08C;
-    PLL0CON  : DWord absolute $400FC080;
-    PLL0CFG  : DWord absolute $400FC084;
-    PLL0STAT : DWord absolute $400FC088;
-    CCLKCFG  : DWord absolute $400FC104;
+{$PACKRECORDS 2}
 
-implementation
+//
+//    STCTRL   : DWord absolute $E000E010;
+//    STRELOAD : DWord absolute $E000E014;
+//    STCURR   : DWord absolute $E000E018;
+//
+//    FIO1DIR2 : Byte  absolute $2009C022;
+//    FIO1SET2 : Byte  absolute $2009C03A;
+//    FIO1CLR2 : Byte  absolute $2009C03E;
+//
+//    SCS      : DWord absolute $400FC1A0;
+//    CLKSRCSEL: DWord absolute $400FC10C;
+//    PLL0FEED : DWord absolute $400FC08C;
+//    PLL0CON  : DWord absolute $400FC080;
+//    PLL0CFG  : DWord absolute $400FC084;
+//    PLL0STAT : DWord absolute $400FC088;
+//    CCLKCFG  : DWord absolute $400FC104;
+//
 
-var
-    _data: record end; external name '_data';
-    _edata: record end; external name '_edata';
-    _etext: record end; external name '_etext';
-    _bss_start: record end; external name '_bss_start';
-    _bss_end: record end; external name '_bss_end';
-    _stack_top: record end; external name '_stack_top';
+Const
+  NonMaskableInt_IRQn        = -14; //  2 Non Maskable // interrupt
+  HardFault_IRQn          	 = -13;  //  4 Cortex-M3 Memory Management // interrupt
+  MemoryManagement_IRQn      = -12; //  4 Cortex-M3 Memory Management // interrupt
+  BusFault_IRQn              = -11; //  5 Cortex-M3 Bus Fault // interrupt
+  UsageFault_IRQn            = -10; //  6 Cortex-M3 Usage Fault // interrupt
+  SVCall_IRQn                = -5;   // 11 Cortex-M3 SV Call // interrupt
+  DebugMonitor_IRQn          = -4;   // 12 Cortex-M3 Debug Monitor // interrupt
+  PendSV_IRQn                = -2;   // 14 Cortex-M3 Pend SV // interrupt
+  SysTick_IRQn               = -1;  // 15 Cortex-M3 System Tick // interrupt
+  WWDG_IRQn                  = 0;   //  Window WatchDog // interrupt
+  PVD_IRQn                   = 1;    //  PVD through EXTI Line detection // interrupt
+  TAMPER_IRQn                = 2;   //  Tamper // interrupt
+  RTC_IRQn                   = 3;    //  RTC global // interrupt
+  FLASH_IRQn                 = 4;    //  FLASH global // interrupt
+  RCC_IRQn                   = 5;    //  RCC global // interrupt
+  EXTI0_IRQn                 = 6;    //  EXTI Line0 // interrupt
+  EXTI1_IRQn                 = 7;    //  EXTI Line1 // interrupt
+  EXTI2_IRQn                 = 8;    //  EXTI Line2 // interrupt
+  EXTI3_IRQn                 = 9;    //  EXTI Line3 // interrupt
+  EXTI4_IRQn                 = 10;  // EXTI Line4 // interrupt
+  DMA1_Channel1_IRQn         = 11;  // DMA1 Channel 1 global // interrupt
+  DMA1_Channel2_IRQn         = 12;  // DMA1 Channel 2 global // interrupt
+  DMA1_Channel3_IRQn         = 13;  // DMA1 Channel 3 global // interrupt
+  DMA1_Channel4_IRQn         = 14;  // DMA1 Channel 4 global // interrupt
+  DMA1_Channel5_IRQn         = 15;  // DMA1 Channel 5 global // interrupt
+  DMA1_Channel6_IRQn         = 16;  // DMA1 Channel 6 global // interrupt
+  DMA1_Channel7_IRQn         = 17;  // DMA1 Channel 7 global // interrupt
+  ADC1_2_IRQn                = 18;   // ADC1 et ADC2 global // interrupt
+  USB_HP_CAN1_TX_IRQn        = 19;   // USB High Priority or CAN1 TX Interrupts
+  USB_LP_CAN1_RX0_IRQn       = 20;  // USB Low Priority or CAN1 RX0 Interrupts
+  CAN1_RX1_IRQn              = 21;   // CAN1 RX1 // interrupt
+  CAN1_SCE_IRQn              = 22;   // CAN1 SCE // interrupt
+  EXTI9_5_IRQn               = 23;  // External Line[9:5] Interrupts
+  TIM1_BRK_IRQn              = 24;   // TIM1 Break // interrupt
+  TIM1_UP_IRQn               = 25;  // TIM1 Update // interrupt
+  TIM1_TRG_COM_IRQn          = 26;   // TIM1 Trigger and Commutation // interrupt
+  TIM1_CC_IRQn               = 27;  // TIM1 Capture Compare // interrupt
+  TIM2_IRQn                  = 28;   // TIM2 global // interrupt
+  TIM3_IRQn                  = 29;   // TIM3 global // interrupt
+  TIM4_IRQn                  = 30;   // TIM4 global // interrupt
+  I2C1_EV_IRQn               = 31;  // I2C1 Event // interrupt
+  I2C1_ER_IRQn               = 32;  // I2C1 Error // interrupt
+  I2C2_EV_IRQn               = 33;  // I2C2 Event // interrupt
+  I2C2_ER_IRQn               = 34;  // I2C2 Error // interrupt
+  SPI1_IRQn                  = 35;   // SPI1 global // interrupt
+  SPI2_IRQn                  = 36;   // SPI2 global // interrupt
+  USART1_IRQn                = 37;   // USART1 global // interrupt
+  USART2_IRQn                = 38;   // USART2 global // interrupt
+  USART3_IRQn                = 39;   // USART3 global // interrupt
+  EXTI15_10_IRQn             = 40;  // External Line[15:10] Interrupts
+  RTCAlarm_IRQn              = 41;   // RTC Alarm through EXTI Line // interrupt
+  USBWakeUp_IRQn             = 42;  // USB WakeUp from suspend through EXTI Line // interrupt
+  TIM8_BRK_IRQn              = 43;   // TIM8 Break // interrupt
+  TIM8_UP_IRQn               = 44;  // TIM8 Update // interrupt
+  TIM8_TRG_COM_IRQn          = 45;   // TIM8 Trigger and Commutation // interrupt
+  TIM8_CC_IRQn               = 46;  // TIM8 Capture Compare // interrupt
+  ADC3_IRQn                  = 47;   // ADC3 global // interrupt
+  FSMC_IRQn                  = 48;   // FSMC global // interrupt
+  SDIO_IRQn                  = 49;   // SDIO global // interrupt
+  TIM5_IRQn                  = 50;   // TIM5 global // interrupt
+  SPI3_IRQn                  = 51;   // SPI3 global // interrupt
+  UART4_IRQn                 = 52;  // UART4 global // interrupt
+  UART5_IRQn                 = 53;  // UART5 global // interrupt
+  TIM6_IRQn                  = 54;   // TIM6 global // interrupt
+  TIM7_IRQn                  = 55;   // TIM7 global // interrupt
+  DMA2_Channel1_IRQn         = 56;  // DMA2 Channel 1 global // interrupt
+  DMA2_Channel2_IRQn         = 57;  // DMA2 Channel 2 global // interrupt
+  DMA2_Channel3_IRQn         = 58;  // DMA2 Channel 3 global // interrupt
+  DMA2_Channel4_5_IRQn       = 59;  // DMA2 Channel 4 and Channel 5 global // interrupt
 
-procedure PASCALMAIN; external name 'PASCALMAIN';
+Type
 
-procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
-asm
-.Lhalt:
-    b .Lhalt
-end;
+//*------------- System Control (SC) ------------------------------------------*/
+
+TSCRegisters = Record
+  FLASHCFG		: DWord;               // Flash Accelerator Module           */
+  RESERVED0		: Array [1..31] Of DWord;
+  PLL0CON		: DWord;                // Clocking and Power Control         */
+  PLL0CFG		: DWord;
+  PLL0STAT		: DWord;
+  PLL0FEED		: DWord;
+  RESERVED1		: Array [1..4] Of DWord;
+  PLL1CON		: DWord;
+  PLL1CFG		: DWord;
+  PLL1STAT		: DWord;
+  PLL1FEED		: DWord;
+  RESERVED2		: Array [1..4] Of DWord;
+  PCON			: DWord;
+  PCONP			: DWord;
+  RESERVED3		: Array [1..15] Of DWord;
+  CCLKCFG		: DWord;
+  USBCLKCFG		: DWord;
+  CLKSRCSEL		: DWord;
+  RESERVED4		: Array [1..12] Of DWord;
+  EXTINT		: DWord;                 // External Interrupts                */
+  RESERVED5		: DWord;
+  EXTMODE		: DWord;
+  EXTPOLAR		: DWord;
+  RESERVED		: Array [1..12] Of DWord;
+  RSID			: DWord;                   // Reset                              */
+  RESERVED7		: Array [1..7] Of DWord;
+  SCS			: DWord;                    // Syscon Miscellaneous Registers     */
+  IRCTRIM		: DWord;                // Clock Dividers                     */
+  PCLKSEL0		: DWord;
+  PCLKSEL1		: DWord;
+  RESERVED8		: Array [1..4] Of DWord;
+  USBIntSt		: DWord;               // USB Device/OTG Interrupt Register  */
+  DMAREQSEL		: DWord;
+  CLKOUTCFG		: DWord;              // Clock Output Configuration         */
+End;
+
+//*------------- Pin Connect Block (PINCON) -----------------------------------*/
+
+TPINCONRegisters = Record
+   PINSEL0		: DWord;
+   PINSEL1		: DWord;
+   PINSEL2		: DWord;
+   PINSEL3		: DWord;
+   PINSEL4		: DWord;
+   PINSEL5		: DWord;
+   PINSEL6		: DWord;
+   PINSEL7		: DWord;
+   PINSEL8		: DWord;
+   PINSEL9		: DWord;
+   PINSEL10		: DWord;
+   RESERVED0	: Array [1..5] Of DWord;
+   PINMODE0		: DWord;
+   PINMODE1		: DWord;
+   PINMODE2		: DWord;
+   PINMODE3		: DWord;
+   PINMODE4		: DWord;
+   PINMODE5		: DWord;
+   PINMODE6		: DWord;
+   PINMODE7		: DWord;
+   PINMODE8		: DWord;
+   PINMODE9		: DWord;
+   PINMODE_OD0	: DWord;
+   PINMODE_OD1	: DWord;
+   PINMODE_OD2	: DWord;
+   PINMODE_OD3	: DWord;
+   PINMODE_OD4	: DWord;
+   I2CPADCFG	: DWord;
+End;
+
+//------------- General Purpose Input/Output (GPIO) --------------------------*/
+
+{
+TGPIORegisters = Record
+  Case Byte Of
+    0: (FIODIR: DWord);
+    1: (FIORIRL, FIODIRH: Word);
+    2: (FIODIR0, FIODIR1, FIODIR2, FIODIR3: Byte);
+  End;
+  RESERVED0: Array [1..3] Of DWord;;
+  Case Byte Of
+    0: (FIOMASK: DWord);
+    1: (FIOMASKL, FIOMASKH: Word);
+    2: (FIOMASK0, FIOMASK1, FIOMASK2, FIOMASK3: Byte);
+  End;
+  Case Byte Of
+    0: (FIOPIN: DWord);
+    1: (FIOPINL, FIOPINH: Word);
+    2: (FIOPIN0, FIOPIN1, FIOPIN2, FIOPIN3: Byte);
+  End;
+  Case Byte Of
+    0: (FIOSET: DWord);
+    1: (FIOSETL, FIOSETH: Word);
+    2: (FIOSET0, FIOSET1, FIOSET2, FIOSET3: Byte);
+  End;
+  Case Byte Of
+    0: (FIOCLR: DWord);
+    1: (FIOCLRL, FIOSETH: Word);
+    2: (FIOCLR0, FIOCLR1, FIOCLR2, FIOCLR3: Byte);
+  End;
+End;
+}
+  TGPIORegisters = Record
+    FIODIR: DWord;
+    RESERVED0: Array [1..3] Of DWord;
+    FIOMASK: DWord;
+    FIOPIN: DWord;
+    FIOSET: DWord;
+    FIOCLR: DWord;
+  End;
+
+TGPIOINTRegisters = Record
+  IntStatus: DWord;
+  IO0IntStatR: DWord;
+  IO0IntStatF: DWord;
+  IO0IntClr: DWord;
+  IO0IntEnR: DWord;
+  IO0IntEnF: DWord;
+  RESERVED0: Array [1..2] Of DWord;
+  IO2IntStatR: DWord;
+  IO2IntStatF: DWord;
+  IO2IntClr: DWord;
+  IO2IntEnR: DWord;
+  IO2IntEnF: DWord;
+End;
+
+//*------------- Timer (TIM) --------------------------------------------------*/
+TTIMRegisters = Record
+  IR: DWord;
+  TCR: DWord;
+  TC: DWord;
+  PR: DWord;
+  PC: DWord;
+  MCR: DWord;
+  MR0: DWord;
+  MR1: DWord;
+  MR2: DWord;
+  MR3: DWord;
+  CCR: DWord;
+  CR0: DWord;
+  CR1: DWord;
+  RESERVED0: Array [1..2] Of DWord;
+  EMR: DWord;
+  RESERVED1: Array [1..12] Of DWord;
+  CTCR: DWord;
+End;
+
+//*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+TPWMRegisters = Record
+  IR: DWord;
+  TCR: DWord;
+  TC: DWord;
+  PR: DWord;
+  PC: DWord;
+  MCR: DWord;
+  MR0: DWord;
+  MR1: DWord;
+  MR2: DWord;
+  MR3: DWord;
+  CCR: DWord;
+  CR0: DWord;
+  CR1: DWord;
+  CR2: DWord;
+  CR3: DWord;
+  RESERVED0: DWord;
+  MR4: DWord;
+  MR5: DWord;
+  MR6: DWord;
+  PCR: DWord;
+  LER: DWord;
+  RESERVED1: Array [1..7] Of DWord;
+  CTCR: DWord;
+End;
+
+//*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+{
+TUARTRegisters = Record
+  Case Byte Of
+    0: (RBR: Byte);
+    1: (THR: Byte);
+    2: (DLL: Byte);
+    3: (RESERVED: DWord);
+  End;
+  Case Byte Of
+    0: (DLM: Byte);
+    1: (IER: DWord);
+  End;
+  Case Byte Of
+    0: (IIR: DWord);
+    1: (FCR: Byte);
+  End;
+  LCR: Byte;
+  RESERVED1: Array [1..7] Of Byte;
+  LSR: Byte;
+  RESERVED2: Array [1..7] Of Byte;
+  SCR: Byte;
+  RESERVED3: Array [1..3] Of Byte;
+  ACR: DWord;
+  ICR: Byte;
+  RESERVED4: Array [1..3] Of Byte;
+  FDR: Byte;
+  RESERVED5: Array [1..7] Of Byte;
+  TER: Byte;
+  RESERVED6: Array [1..39] Of Byte;
+  FIFOLVL: Byte;
+End;
+
+TUART0Registers = Record
+  Case Byte Of
+    0: (RBR: Byte);
+    1: (THR: Byte);
+    2: (DLL: Byte);
+    3: (RESERVED: DWord);
+  End;
+  Case Byte Of
+    0: (DLM: Byte);
+    1: (IER: DWord);
+  End;
+  Case Byte Of
+    0: (IIR: DWord);
+    1: (FCR: Byte);
+  End;
+  LCR: Byte;
+  RESERVED1: Array [1..7] Of Byte;
+  LSR: Byte;
+  RESERVED2: Array [1..7] Of Byte;
+  SCR: Byte;
+  RESERVED3: Array [1..3] Of Byte;
+  ACR: DWord;
+  ICR: Byte;
+  RESERVED4: Array [1..3] Of Byte;
+  FDR: Byte;
+  RESERVED5: Array [1..7] Of Byte;
+  TER: Byte;
+  RESERVED6: Array [1..39] Of Byte;
+  FIFOLVL: Byte;
+End;
+
+
+TUART1Registers = Record
+  Case Byte Of
+    0: (RBR: Byte);
+    1: (THR: Byte);
+    2: (DLL: Byte);
+    3: (RESERVED: DWord);
+  End;
+  Case Byte Of
+    0: (DLM: Byte);
+    1: (IER: DWord);
+  End;
+  Case Byte Of
+    0: (IIR: DWord);
+    1: (FCR: Byte);
+  End;
+  LCR: Byte;
+  RESERVED1: Array [1..3] Of Byte;
+  MCR: Byte;
+  RESERVED2: Array [1..3] Of Byte;
+  LSR: Byte;
+  RESERVED3: Array [1..3] Of Byte;
+  MSR: Byte;
+  RESERVED4: Array [1..3] Of Byte;
+  SCR: Byte;
+  RESERVED5: Array [1..3] Of Byte;
+  ACR: DWord;
+  RESERVED6: DWord;
+  FDR: DWord;
+  RESERVED7: DWord;
+  TER: Byte;
+  RESERVED8: Array [1..27] Of Byte;
+  RS485CTRL: Byte;
+  RESERVED9: Array [1..3] Of Byte;
+  ADRMATCH: Byte;
+  RESERVED10: Array [1..3] Of Byte;
+  RS485DLY: Byte;
+  RESERVED11: Array [1..3] Of Byte;
+  FIFOLVL: Byte
+End;
+}
+//*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+
+TSPIRegisters = Record
+  SPCR			: DWord;
+  SPSR			: DWord;
+  SPDR			: DWord;
+  RESERVED0		: Array [1..3] Of DWord;
+  SPINT			: DWord;
+End;
+
+//*------------- Synchronous Serial Communication (SSP) -----------------------*/
+
+TSSPRegisters = Record
+  CR0,
+  CR1,
+  DR,
+  SR,
+  CPSR,
+  IMSC,
+  RIS,
+  MIS,
+  ICR,
+  DMACR			: DWord;
+End;
+
+//*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+
+TI2CRegisters = Record
+  I2CONSET		: DWord;
+  I2STAT		: DWord;
+  I2DAT			: DWord;
+  I2ADR0		: DWord;
+  I2SCLH		: DWord;
+  I2SCLL		: DWord;
+  I2CONCLR		: DWord;
+  MMCTRL		: DWord;
+  I2ADR1		: DWord;
+  I2ADR2		: DWord;
+  I2ADR3		: DWord;
+  I2DATA_BUFFER	: DWord;
+  I2MASK0		: DWord;
+  I2MASK1		: DWord;
+  I2MASK2		: DWord;
+  I2MASK3		: DWord;
+End;
+
+//*------------- Inter IC Sound (I2S) -----------------------------------------*/
+
+TI2SRegisters = Record
+  I2SDAO		: DWord;
+  I2SDAI		: DWord;
+  I2STXFIFO		: DWord;
+  I2SRXFIFO		: DWord;
+  I2SSTATE		: DWord;
+  I2SDMA1		: DWord;
+  I2SDMA2		: DWord;
+  I2SIRQ		: DWord;
+  I2STXRATE		: DWord;
+  I2SRXRATE		: DWord;
+  I2STXBITRATE	: DWord;
+  I2SRXBITRATE	: DWord;
+  I2STXMODE		: DWord;
+  I2SRXMODE		: DWord;
+End;
+
+//*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+
+TRITRegisters = Record
+  RICOMPVAL		: DWord;
+  RIMASK			: DWord;
+  RICTRL			: Byte;
+  RESERVED0		: Array [1..3] Of Byte;
+  RICOUNTER		: DWord;
+End;
+
+//*------------- Real-Time Clock (RTC) ----------------------------------------*/
+TRTCRegisters = Record
+   ILR			: Byte;
+   RESERVED0		: Array [1..7] Of Byte;
+   CCR			: Byte;
+   RESERVED1		: Array [1..3] Of Byte;
+   CIIR			: Byte;
+   RESERVED2		: Array [1..3] Of Byte;
+   AMR			: Byte;
+   RESERVED3		: Array [1..3] Of Byte;
+   CTIME0		: DWord;
+   CTIME1		: DWord;
+   CTIME2		: DWord;
+   SEC			: Byte;
+   RESERVED4		: Array [1..3] Of Byte;
+   MIN			: Byte;
+   RESERVED5		: Array [1..3] Of Byte;
+   HOUR			: Byte;
+   RESERVED6		: Array [1..3] Of Byte;
+   DOM			: Byte;
+   RESERVED7		: Array [1..3] Of Byte;
+   DOW			: Byte;
+   RESERVED8		: Array [1..3] Of Byte;
+   DOY			: Word;
+   RESERVED9		: Word;
+   MONTH			: Byte;
+   RESERVED10		: Array [1..3] Of Byte;
+   YEAR			: Word;
+   RESERVED11		: Word;
+   CALIBRATION	: DWord;
+   GPREG0		: DWord;
+   GPREG1		: DWord;
+   GPREG2		: DWord;
+   GPREG3		: DWord;
+   GPREG4		: DWord;
+   RTC_AUXEN		: Byte;
+   RESERVED12		: Array [1..3] Of Byte;
+   RTC_AUX		: Byte;
+   RESERVED13		: Array [1..3] Of Byte;
+   ALSEC			: Byte;
+   RESERVED14		: Array [1..3] Of Byte;
+   ALMIN			: Byte;
+   RESERVED15		: Array [1..3] Of Byte;
+   ALHOUR		: Byte;
+   RESERVED16		: Array [1..3] Of Byte;
+   ALDOM			: Byte;
+   RESERVED17		: Array [1..3] Of Byte;
+   ALDOW			: Byte;
+   RESERVED18		: Array [1..3] Of Byte;
+   ALDOY			: Word;
+   RESERVED19		: Word;
+   ALMON			: Byte;
+   RESERVED20		: Array [1..3] Of Byte;
+   ALYEAR		: Word;
+   RESERVED21		: Word;
+End;
+
+//*------------- Watchdog Timer (WDT) -----------------------------------------*/
+
+TWDTRegisters = Record
+  WDMOD			: Byte;
+  RESERVED0		: Array [1..3] Of Byte;
+  WDTC			: DWord;
+  WDFEED			: Byte;
+  RESERVED1		: Array [1..3] Of Byte;
+  WDTV			: DWord;
+  WDCLKSEL		: DWord;
+End;
+
+//*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+TADCRegisters = Record
+  ADCR			: DWord;
+  ADGDR			: DWord;
+  RESERVED0		: DWord;
+  ADINTEN		: DWord;
+  ADDR0			: DWord;
+  ADDR1			: DWord;
+  ADDR2			: DWord;
+  ADDR3			: DWord;
+  ADDR4			: DWord;
+  ADDR5			: DWord;
+  ADDR6			: DWord;
+  ADDR7			: DWord;
+  ADSTAT			: DWord;
+  ADTRM			: DWord;
+End;
+
+//*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+TDACRegisters = Record
+  DACR			: DWord;
+  DACCTRL		: DWord;
+  DACCNTVAL		: Word;
+End;
+
+//*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+TMCPWMRegisters = Record
+  MCCON		: DWord;
+  MCCON_SET	: DWord;
+  MCCON_CLR	: DWord;
+  MCCAPCON		: DWord;
+  MCCAPCON_SET	: DWord;
+  MCCAPCON_CLR	: DWord;
+  MCTIM0		: DWord;
+  MCTIM1		: DWord;
+  MCTIM2		: DWord;
+  MCPER0		: DWord;
+  MCPER1		: DWord;
+  MCPER2		: DWord;
+  MCPW0		: DWord;
+  MCPW1		: DWord;
+  MCPW2		: DWord;
+  MCDEADTIME	: DWord;
+  MCCCP		: DWord;
+  MCCR0		: DWord;
+  MCCR1		: DWord;
+  MCCR2		: DWord;
+  MCINTEN		: DWord;
+  MCINTEN_SET	: DWord;
+  MCINTEN_CLR	: DWord;
+  MCCNTCON		: DWord;
+  MCCNTCON_SET	: DWord;
+  MCCNTCON_CLR	: DWord;
+  MCINTFLAG	: DWord;
+  MCINTFLAG_SET: DWord;
+  MCINTFLAG_CLR: DWord;
+  MCCAP_CLR	: DWord;
+End;
+//*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+TQEIRegisters = Record
+  QEICON: DWord;
+  QEISTAT: DWord;
+  QEICONF: DWord;
+  QEIPOS: DWord;
+  QEIMAXPOS: DWord;
+  CMPOS0: DWord;
+  CMPOS1: DWord;
+  CMPOS2: DWord;
+  INXCNT: DWord;
+  INXCMP: DWord;
+  QEILOAD: DWord;
+  QEITIME: DWord;
+  QEIVEL: DWord;
+  QEICAP: DWord;
+  VELCOMP: DWord;
+  FILTER: DWord;
+  RESERVED0: Array [1..998] Of DWord;
+  QEIIEC: DWord;
+  QEIIES: DWord;
+  QEIINTSTAT: DWord;
+  QEIIE: DWord;
+  QEICLR: DWord;
+  QEISET: DWord;
+End;
+
+//*------------- Controller Area Network (CAN) --------------------------------*/
+TCANAF_RAMRegisters = Record
+  MASK: Array [1..512] Of DWord;              //* ID Masks                           */
+End;
+
+TCANAF = Record                          //* Acceptance Filter Registers        */
+  AFMR: DWord;
+  SFF_sa: DWord;
+  SFF_GRP_sa: DWord;
+  EFF_sa: DWord;
+  EFF_GRP_sa: DWord;
+  ENDofTable: DWord;
+  LUTerrAd: DWord;
+  LUTerr: DWord;
+  FCANIE: DWord;
+  FCANIC0: DWord;
+  FCANIC1: DWord;
+End;
+
+TCANCRRegisters = Record                     //* Central Registers                  */
+     CANTxSR: DWord;
+     CANRxSR: DWord;
+     CANMSR: DWord;
+End;
+
+TCANRegisters = Record                     //* Controller Registers               */
+    _MOD: DWord;
+     CMR: DWord;
+    GSR: DWord;
+     ICR: DWord;
+    IER: DWord;
+    BTR: DWord;
+    EWL: DWord;
+     SR: DWord;
+    RFS: DWord;
+    RID: DWord;
+    RDA: DWord;
+    RDB: DWord;
+    TFI1: DWord;
+    TID1: DWord;
+    TDA1: DWord;
+    TDB1: DWord;
+    TFI2: DWord;
+    TID2: DWord;
+    TDA2: DWord;
+    TDB2: DWord;
+    TFI3: DWord;
+    TID3: DWord;
+    TDA3: DWord;
+    TDB3: DWord;
+End;
+
+//*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+
+TGPDMARegisters = Record              //* Common Registers                   */
+     DMACIntStat: DWord;
+     DMACIntTCStat: DWord;
+     DMACIntTCClear: DWord;
+     DMACIntErrStat: DWord;
+     DMACIntErrClr: DWord;
+     DMACRawIntTCStat: DWord;
+     DMACRawIntErrStat: DWord;
+     DMACEnbldChns: DWord;
+    DMACSoftBReq: DWord;
+    DMACSoftSReq: DWord;
+    DMACSoftLBReq: DWord;
+    DMACSoftLSReq: DWord;
+    DMACConfig: DWord;
+    DMACSync: DWord;
+End;
+
+TGPDMACHRegisters = Record              //* Channel Registers                  */
+  DMACCSrcAddr	: DWord;
+  DMACCDestAddr	: DWord;
+  DMACCLLI		: DWord;
+  DMACCControl	: DWord;
+  DMACCConfig		: DWord;
+End;
+
+//*------------- Universal Serial Bus (USB) -----------------------------------*/
+TUSBRegisters = Record
+  HcRevision: DWord;             //* USB Host Registers                 */
+  HcControl: DWord;
+    HcCommandStatus: DWord;
+    HcInterruptStatus: DWord;
+    HcInterruptEnable: DWord;
+    HcInterruptDisable: DWord;
+    HcHCCA: DWord;
+     HcPeriodCurrentED: DWord;
+    HcControlHeadED: DWord;
+    HcControlCurrentED: DWord;
+    HcBulkHeadED: DWord;
+    HcBulkCurrentED: DWord;
+     HcDoneHead: DWord;
+    HcFmInterval: DWord;
+     HcFmRemaining: DWord;
+     HcFmNumber: DWord;
+    HcPeriodicStart: DWord;
+    HcLSTreshold: DWord;
+    HcRhDescriptorA: DWord;
+    HcRhDescriptorB: DWord;
+    HcRhStatus: DWord;
+    HcRhPortStatus1: DWord;
+    HcRhPortStatus2: DWord;
+    RESERVED0: Array [1..40] Of DWord;
+     Module_ID: DWord;
+
+     OTGIntSt: DWord;               //* USB On-The-Go Registers            */
+    OTGIntEn: DWord;
+     OTGIntSet: DWord;
+     OTGIntClr: DWord;
+    OTGStCtrl: DWord;
+    OTGTmr: DWord;
+        RESERVED1: Array [1..58] Of DWord;
+
+     USBDevIntSt: DWord;            // USB Device Interrupt Registers     */
+    USBDevIntEn: DWord;
+     USBDevIntClr: DWord;
+     USBDevIntSet: DWord;
+
+     USBCmdCode: DWord;             // USB Device SIE Command Registers   */
+     USBCmdData: DWord;
+
+     USBRxData: DWord;              // USB Device Transfer Registers      */
+     USBTxData: DWord;
+     USBRxPLen: DWord;
+     USBTxPLen: DWord;
+    USBCtrl: DWord;
+     USBDevIntPri: DWord;
+
+     USBEpIntSt: DWord;             // USB Device Endpoint Interrupt Regs */
+    USBEpIntEn: DWord;
+     USBEpIntClr: DWord;
+     USBEpIntSet: DWord;
+     USBEpIntPri: DWord;
+
+    USBReEp: DWord;                // USB Device Endpoint Realization Reg*/
+     USBEpInd: DWord;
+    USBMaxPSize: DWord;
+
+     USBDMARSt: DWord;              // USB Device DMA Registers           */
+     USBDMARClr: DWord;
+     USBDMARSet: DWord;
+        RESERVED2:Array [1..9] Of DWord;
+    USBUDCAH: DWord;
+     USBEpDMASt: DWord;
+     USBEpDMAEn: DWord;
+     USBEpDMADis: DWord;
+     USBDMAIntSt: DWord;
+    USBDMAIntEn: DWord;
+        RESERVED3:Array [1..2] Of DWord;
+     USBEoTIntSt: DWord;
+     USBEoTIntClr: DWord;
+     USBEoTIntSet: DWord;
+     USBNDDRIntSt: DWord;
+     USBNDDRIntClr: DWord;
+     USBNDDRIntSet: DWord;
+     USBSysErrIntSt: DWord;
+     USBSysErrIntClr: DWord;
+     USBSysErrIntSet: DWord;
+        RESERVED4: Array [1..15] Of DWord;
+
+     I2C_RX: DWord;                 // USB OTG I2C Registers              */
+     I2C_WO: DWord;
+     I2C_STS: DWord;
+    I2C_CTL: DWord;
+    I2C_CLKHI: DWord;
+     I2C_CLKLO: DWord;
+        RESERVED5:Array [1..823] Of DWord;
+    USBClkCtrl: Byte;		// USB Clock Control Registers        */
+  End;
+///------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+TEMACRegisters = Record
+    MAC1: DWord;                   // MAC Registers                      */
+    MAC2: DWord;
+    IPGT: DWord;
+    IPGR: DWord;
+    CLRT: DWord;
+    MAXF: DWord;
+    SUPP: DWord;
+    TEST: DWord;
+    MCFG: DWord;
+    MCMD: DWord;
+    MADR: DWord;
+     MWTD: DWord;
+     MRDD: DWord;
+     MIND: DWord;
+        RESERVED0:Array [1..2] Of DWord;
+    SA0: DWord;
+    SA1: DWord;
+    SA2: DWord;
+        RESERVED1:Array [1..45] Of DWord;
+    Command: DWord;                // Control Registers                  */
+     Status: DWord;
+    RxDescriptor: DWord;
+    RxStatus: DWord;
+    RxDescriptorNumber: DWord;
+     RxProduceIndex: DWord;
+    RxConsumeIndex: DWord;
+    TxDescriptor: DWord;
+    TxStatus: DWord;
+    TxDescriptorNumber: DWord;
+    TxProduceIndex: DWord;
+     TxConsumeIndex: DWord;
+        RESERVED2:Array [1..10] Of DWord;
+     TSV0: DWord;
+     TSV1: DWord;
+     RSV: DWord;
+        RESERVED3: Array [1..3] Of DWord;
+    FlowControlCounter: DWord;
+     FlowControlStatus: DWord;
+        RESERVED4: Array [1..34] Of DWord;
+    RxFilterCtrl: DWord;           // Rx Filter Registers                */
+    RxFilterWoLStatus: DWord;
+    RxFilterWoLClear: DWord;
+        RESERVED5: DWord;
+    HashFilterL: DWord;
+    HashFilterH: DWord;
+        RESERVED6:Array [1..882] Of DWord;
+     IntStatus: DWord;              // Module Control Registers           */
+    IntEnable: DWord;
+     IntClear: DWord;
+     IntSet: DWord;
+        RESERVED7: DWord;
+    PowerDown: DWord;
+        RESERVED8: DWord;
+    Module_ID: DWord;
+End;
+
+ TNVICRegisters = packed record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of longword;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ End;
+
+ TSCBRegisters = packed record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                            {!< Interrupt Control State Register                        }
+  VTOR,                            {!< Vector Table Offset Register                            }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                 }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)   }
+  SHCSR,                            {!< System Handler Control and State Register               }
+  CFSR,                            {!< Configurable Fault Status Register                      }
+  HFSR,                            {!< Hard Fault Status Register                              }
+  DFSR,                            {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                             }
+  BFAR,                            {!< Bus Fault Address Register                              }
+  AFSR: longword;                  {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;    {!< Processor Feature Register                              }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                           }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+TSysTickRegisters = Packed Record
+  CTRL,
+  RELOAD,
+  VAL,
+  CALIB: LongWord;
+End;
+
+// Based on CORE_CM3.H
+
+///*****************************************************************************/
+///                         Peripheral memory map                              */
+///*****************************************************************************/
+
+Const
+ LPC_SCS_BASE        		= $E000E000;
+ LPC_SCB_BASE          = (LPC_SCS_BASE + $0D00);      // System Control Block Base Address
+
+/// Base addresses                                                             */
+
+ LPC_FLASH_BASE        = ($00000000);
+ LPC_RAM_BASE          = ($10000000);
+ LPC_GPIO_BASE         = ($2009C000);
+ LPC_APB0_BASE         = ($40000000);
+ LPC_APB1_BASE         = ($40080000);
+ LPC_AHB_BASE          = ($50000000);
+ LPC_CM3_BASE          = ($E0000000);
+
+/// APB0 peripherals                                                           */
+ LPC_WDT_BASE          = (LPC_APB0_BASE + $00000);
+ LPC_TIM0_BASE         = (LPC_APB0_BASE + $04000);
+ LPC_TIM1_BASE         = (LPC_APB0_BASE + $08000);
+ LPC_UART0_BASE        = (LPC_APB0_BASE + $0C000);
+ LPC_UART1_BASE        = (LPC_APB0_BASE + $10000);
+ LPC_PWM1_BASE         = (LPC_APB0_BASE + $18000);
+ LPC_I2C0_BASE         = (LPC_APB0_BASE + $1C000);
+ LPC_SPI_BASE          = (LPC_APB0_BASE + $20000);
+ LPC_RTC_BASE          = (LPC_APB0_BASE + $24000);
+ LPC_GPIOINT_BASE      = (LPC_APB0_BASE + $28080);
+ LPC_PINCON_BASE       = (LPC_APB0_BASE + $2C000);
+ LPC_SSP1_BASE         = (LPC_APB0_BASE + $30000);
+ LPC_ADC_BASE          = (LPC_APB0_BASE + $34000);
+ LPC_CANAF_RAM_BASE    = (LPC_APB0_BASE + $38000);
+ LPC_CANAF_BASE        = (LPC_APB0_BASE + $3C000);
+ LPC_CANCR_BASE        = (LPC_APB0_BASE + $40000);
+ LPC_CAN1_BASE         = (LPC_APB0_BASE + $44000);
+ LPC_CAN2_BASE         = (LPC_APB0_BASE + $48000);
+ LPC_I2C1_BASE         = (LPC_APB0_BASE + $5C000);
+
+/// APB1 peripherals                                                           */
+ LPC_SSP0_BASE         = (LPC_APB1_BASE + $08000);
+ LPC_DAC_BASE          = (LPC_APB1_BASE + $0C000);
+ LPC_TIM2_BASE         = (LPC_APB1_BASE + $10000);
+ LPC_TIM3_BASE         = (LPC_APB1_BASE + $14000);
+ LPC_UART2_BASE        = (LPC_APB1_BASE + $18000);
+ LPC_UART3_BASE        = (LPC_APB1_BASE + $1C000);
+ LPC_I2C2_BASE         = (LPC_APB1_BASE + $20000);
+ LPC_I2S_BASE          = (LPC_APB1_BASE + $28000);
+ LPC_RIT_BASE          = (LPC_APB1_BASE + $30000);
+ LPC_MCPWM_BASE        = (LPC_APB1_BASE + $38000);
+ LPC_QEI_BASE          = (LPC_APB1_BASE + $3C000);
+ LPC_SC_BASE           = (LPC_APB1_BASE + $7C000);
+
+/// AHB peripherals                                                            */
+ LPC_EMAC_BASE         = (LPC_AHB_BASE  + $00000);
+ LPC_GPDMA_BASE        = (LPC_AHB_BASE  + $04000);
+ LPC_GPDMACH0_BASE     = (LPC_AHB_BASE  + $04100);
+ LPC_GPDMACH1_BASE     = (LPC_AHB_BASE  + $04120);
+ LPC_GPDMACH2_BASE     = (LPC_AHB_BASE  + $04140);
+ LPC_GPDMACH3_BASE     = (LPC_AHB_BASE  + $04160);
+ LPC_GPDMACH4_BASE     = (LPC_AHB_BASE  + $04180);
+ LPC_GPDMACH5_BASE     = (LPC_AHB_BASE  + $041A0);
+ LPC_GPDMACH6_BASE     = (LPC_AHB_BASE  + $041C0);
+ LPC_GPDMACH7_BASE     = (LPC_AHB_BASE  + $041E0);
+ LPC_USB_BASE          = (LPC_AHB_BASE  + $0C000);
+
+/// GPIOs                                                                      */
+ LPC_GPIO0_BASE        = (LPC_GPIO_BASE + $00000);
+ LPC_GPIO1_BASE        = (LPC_GPIO_BASE + $00020);
+ LPC_GPIO2_BASE        = (LPC_GPIO_BASE + $00040);
+ LPC_GPIO3_BASE        = (LPC_GPIO_BASE + $00060);
+ LPC_GPIO4_BASE        = (LPC_GPIO_BASE + $00080);
+
+///*****************************************************************************/
+///                         Peripheral declaration                             */
+///*****************************************************************************/
+
+{$ALIGN 2}
+
+Var
+ LPC_SC                : TSCRegisters  Absolute (LPC_SC_BASE);
+  LPC_SCB    : TSCBRegisters Absolute (LPC_SCB_BASE);
+ 
+ LPC_GPIO0             : TGPIORegisters Absolute (LPC_GPIO0_BASE);
+ LPC_GPIO1             : TGPIORegisters Absolute (LPC_GPIO1_BASE);
+ LPC_GPIO2             : TGPIORegisters Absolute (LPC_GPIO2_BASE);
+ LPC_GPIO3             : TGPIORegisters Absolute (LPC_GPIO3_BASE);
+ LPC_GPIO4             : TGPIORegisters Absolute (LPC_GPIO4_BASE);
+ LPC_WDT               : TWDTRegisters Absolute  (LPC_WDT_BASE);
+ LPC_TIM0              : TTIMRegisters Absolute (LPC_TIM0_BASE);
+ LPC_TIM1              : TTIMRegisters Absolute (LPC_TIM1_BASE);
+ LPC_TIM2              : TTIMRegisters Absolute (LPC_TIM2_BASE);
+ LPC_TIM3              : TTIMRegisters Absolute (LPC_TIM3_BASE);
+ LPC_RIT               : TRITRegisters Absolute (LPC_RIT_BASE);
+{
+ LPC_UART0             : TUART0Registers Absolute (LPC_UART0_BASE);
+ LPC_UART1             : TUART1Registers Absolute (LPC_UART1_BASE);
+ LPC_UART2             : TUARTRegisters Absolute (LPC_UART2_BASE);
+ LPC_UART3             : TUARTRegisters Absolute (LPC_UART3_BASE);
+}
+ LPC_SYSTICK		   : TSysTickRegisters  Absolute (LPC_SCS_BASE+$0010);
+ LPC_NVIC: TNVICRegisters Absolute (LPC_SCS_BASE+$0100);
+
+ LPC_PWM1              : TPWMRegisters Absolute (LPC_PWM1_BASE);
+ LPC_I2C0              : TI2CRegisters Absolute (LPC_I2C0_BASE);
+ LPC_I2C1              : TI2CRegisters Absolute (LPC_I2C1_BASE);
+ LPC_I2C2              : TI2CRegisters Absolute (LPC_I2C2_BASE);
+ LPC_I2S               : TI2SRegisters Absolute (LPC_I2S_BASE);
+ LPC_SPI               : TSPIRegisters Absolute (LPC_SPI_BASE);
+ LPC_RTC               : TRTCRegisters Absolute (LPC_RTC_BASE);
+ LPC_GPIOINT           : TGPIOINTRegisters Absolute (LPC_GPIOINT_BASE);
+ LPC_PINCON            : TPINCONRegisters Absolute (LPC_PINCON_BASE);
+ LPC_SSP0              : TSSPRegisters Absolute (LPC_SSP0_BASE);
+ LPC_SSP1              : TSSPRegisters Absolute (LPC_SSP1_BASE);
+ LPC_ADC               : TADCRegisters Absolute  (LPC_ADC_BASE);
+ LPC_DAC               : TDACRegisters Absolute  (LPC_DAC_BASE);
+{
+ LPC_CANAF_RAM         : TCANAF_RAMRegisters Absolute  (LPC_CANAF_RAM_BASE);
+ LPC_CANAF             : TCANAFRegisters Absolute  (LPC_CANAF_BASE);
+ LPC_CANCR             : TCANCR_RAMRegisters Absolute  (LPC_CANCR_BASE);
+}
+ LPC_CAN1              : TCANRegisters Absolute  (LPC_CAN1_BASE);
+ LPC_CAN2              : TCANRegisters Absolute  (LPC_CAN2_BASE);
+ LPC_MCPWM             : TMCPWMRegisters Absolute  (LPC_MCPWM_BASE);
+ LPC_QEI               : TQEIRegisters Absolute  (LPC_QEI_BASE);
+ LPC_EMAC              : TEMACRegisters Absolute  (LPC_EMAC_BASE);
+ LPC_GPDMA             : TGPDMARegisters Absolute  (LPC_GPDMA_BASE);
+ LPC_GPDMACH0          : TGPDMACHRegisters Absolute  (LPC_GPDMACH0_BASE);
+ LPC_GPDMACH1          : TGPDMACHRegisters Absolute  (LPC_GPDMACH1_BASE);
+ LPC_GPDMACH2          : TGPDMACHRegisters Absolute  (LPC_GPDMACH2_BASE);
+ LPC_GPDMACH3          : TGPDMACHRegisters Absolute  (LPC_GPDMACH3_BASE);
+ LPC_GPDMACH4          : TGPDMACHRegisters Absolute  (LPC_GPDMACH4_BASE);
+ LPC_GPDMACH5          : TGPDMACHRegisters Absolute  (LPC_GPDMACH5_BASE);
+ LPC_GPDMACH6          : TGPDMACHRegisters Absolute  (LPC_GPDMACH6_BASE);
+ LPC_GPDMACH7          : TGPDMACHRegisters Absolute  (LPC_GPDMACH7_BASE);
+ LPC_USB               : TUSBRegisters Absolute  (LPC_USB_BASE);
+
+implementation
+
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure Watchdog_Interrupt; external name 'Watchdog_Interrupt';
+procedure Timer0_Interrupt; external name 'Timer0_Interrupt';
+procedure Timer1_Interrupt; external name 'Timer1_Interrupt';
+procedure Timer2_Interrupt; external name 'Timer2_Interrupt';
+procedure Timer3_Interrupt; external name 'Timer3_Interrupt';
+procedure UART0_Interrupt; external name 'UART0_Interrupt';
+procedure UART1_Interrupt; external name 'UART1_Interrupt';
+procedure UART2_Interrupt; external name 'UART2_Interrupt';
+procedure UART3_Interrupt; external name 'UART3_Interrupt';
+procedure PWM1_Interrupt; external name 'PWM1_Interrupt';
+procedure I2C0_Interrupt; external name 'I2C0_Interrupt';
+procedure I2C1_Interrupt; external name 'I2C1_Interrupt';
+procedure I2C2_Interrupt; external name 'I2C2_Interrupt';
+procedure SPI_Interrupt; external name 'SPI_Interrupt';
+procedure SSP0_Interrupt; external name 'SSP0_Interrupt';
+procedure SSP1_Interrupt; external name 'SSP1_Interrupt';
+procedure PLL0_Interrupt; external name 'PLL0_Interrupt';
+procedure RTC_Interrupt; external name 'RTC_Interrupt';
+procedure EINT0_Interrupt; external name 'EINT0_Interrupt';
+procedure EINT1_Interrupt; external name 'EINT1_Interrupt';
+procedure EINT2_Interrupt; external name 'EINT2_Interrupt';
+procedure EINT3_Interrupt; external name 'EINT3_Interrupt';
+procedure ADC_Interrupt; external name 'ADC_Interrupt';
+procedure BOD_Interrupt; external name 'BOD_Interrupt';
+procedure USB_Interrupt; external name 'USB_Interrupt';
+procedure CAN_Interrupt; external name 'CAN_Interrupt';
+procedure HPDMA_Interrupt; external name 'HPDMA_Interrupt';
+procedure I2C_Interrupt; external name 'I2C_Interrupt';
+procedure Ethernet_Interrupt; external name 'Ethernet_Interrupt';
+procedure RITINT_Interrupt; external name 'RITINT_Interrupt';
+procedure MotorControlPWM_Interrupt; external name 'MotorControlPWM_Interrupt';
+procedure QuadratureEncoder_Interrupt; external name 'QuadratureEncoder_Interrupt';
+procedure PLL1_Interrupt; external name 'PLL1_Interrupt';
+procedure USBActivity_Interrupt; external name 'USBActivity_Interrupt';
+procedure CanActivity_Interrupt; external name 'CanActivity_Interrupt';
+
+{$i cortexm3_start.inc}
 
-procedure _FPC_start; assembler; nostackframe;
-label _start;
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
 asm
-    .init
-    .balign 16
-
-    .long _stack_top            // stack top address
-    .long _start+1              // 1 Reset
-    .long .LDefaultHandler+1    // 2 NMI
-    .long .LDefaultHandler+1    // 3 HardFault
-    .long .LDefaultHandler+1    // 4 MemManage
-    .long .LDefaultHandler+1    // 5 BusFault
-    .long .LDefaultHandler+1    // 6 UsageFault
-    .long .LDefaultHandler+1    // 7 RESERVED
-    .long .LDefaultHandler+1    // 8 RESERVED
-    .long .LDefaultHandler+1    // 9 RESERVED
-    .long .LDefaultHandler+1    // 10 RESERVED
-    .long .LDefaultHandler+1    // 11 SVCall
-    .long .LDefaultHandler+1    // 12 Debug Monitor
-    .long .LDefaultHandler+1    // 13 RESERVED
-    .long .LDefaultHandler+1    // 14 PendSV
-    .long .LDefaultHandler+1    // 15 SysTick
-    .long .LDefaultHandler+1    // 16 External Interrupt(0)
-    .long .LDefaultHandler+1    // 17 External Interrupt(1)
-    .long .LDefaultHandler+1    // 18 External Interrupt(2)
-    .long .LDefaultHandler+1    // 19 ...
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-    .long .LDefaultHandler+1
-
-    .globl _start
-    .text
-_start:
-
-    // Copy initialized data to ram
-    ldr r1,.L_etext
-    ldr r2,.L_data
-    ldr r3,.L_edata
-.Lcopyloop:
-    cmp r2,r3
-    ittt ls
-    ldrls r0,[r1],#4
-    strls r0,[r2],#4
-    bls .Lcopyloop
-
-    // clear onboard ram
-    ldr r1,.L_bss_start
-    ldr r2,.L_bss_end
-    mov r0,#0
-.Lzeroloop:
-    cmp r1,r2
-    itt ls
-    strls r0,[r1],#4
-    bls .Lzeroloop
-
-    b PASCALMAIN
-    b _FPC_haltproc
-
-.L_bss_start:
-    .long _bss_start
-.L_bss_end:
-    .long _bss_end
-.L_etext:
-    .long _etext
-.L_data:
-    .long _data
-.L_edata:
-    .long _edata
-.LDefaultHandlerAddr:
-    .long .LDefaultHandler
-    // default irq handler just returns
-.LDefaultHandler:
-    mov pc,r14
+  .section ".init.interrupt_vectors"
+interrupt_vectors:
+  .long _stack_top            // stack top address
+  .long Startup
+  .long NMI_interrupt
+  .long Hardfault_interrupt
+  .long MemManage_interrupt
+  .long BusFault_interrupt
+  .long UsageFault_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long SWI_interrupt
+  .long DebugMonitor_interrupt
+  .long 0
+  .long PendingSV_interrupt
+  .long SysTick_interrupt
+  
+  .long Watchdog_Interrupt
+  .long Timer0_Interrupt
+  .long Timer1_Interrupt
+  .long Timer2_Interrupt
+  .long Timer3_Interrupt
+  .long UART0_Interrupt
+  .long UART1_Interrupt
+  .long UART2_Interrupt
+  .long UART3_Interrupt
+  .long PWM1_Interrupt
+  .long I2C0_Interrupt
+  .long I2C1_Interrupt
+  .long I2C2_Interrupt
+  .long SPI_Interrupt
+  .long SSP0_Interrupt
+  .long SSP1_Interrupt
+  .long PLL0_Interrupt
+  .long RTC_Interrupt
+  .long EINT0_Interrupt
+  .long EINT1_Interrupt
+  .long EINT2_Interrupt
+  .long EINT3_Interrupt
+  .long ADC_Interrupt
+  .long BOD_Interrupt
+  .long USB_Interrupt
+  .long CAN_Interrupt
+  .long HPDMA_Interrupt
+  .long I2C_Interrupt
+  .long Ethernet_Interrupt
+  .long RITINT_Interrupt
+  .long MotorControlPWM_Interrupt
+  .long QuadratureEncoder_Interrupt
+  .long PLL1_Interrupt
+  .long USBActivity_Interrupt
+  .long CanActivity_Interrupt
+  
+  .weak NMI_interrupt
+  .weak Hardfault_interrupt
+  .weak MemManage_interrupt
+  .weak BusFault_interrupt
+  .weak UsageFault_interrupt
+  .weak SWI_interrupt
+  .weak DebugMonitor_interrupt
+  .weak PendingSV_interrupt
+  .weak SysTick_interrupt
+  .weak Watchdog_Interrupt
+  .weak Timer0_Interrupt
+  .weak Timer1_Interrupt
+  .weak Timer2_Interrupt
+  .weak Timer3_Interrupt
+  .weak UART0_Interrupt
+  .weak UART1_Interrupt
+  .weak UART2_Interrupt
+  .weak UART3_Interrupt
+  .weak PWM1_Interrupt
+  .weak I2C0_Interrupt
+  .weak I2C1_Interrupt
+  .weak I2C2_Interrupt
+  .weak SPI_Interrupt
+  .weak SSP0_Interrupt
+  .weak SSP1_Interrupt
+  .weak PLL0_Interrupt
+  .weak RTC_Interrupt
+  .weak EINT0_Interrupt
+  .weak EINT1_Interrupt
+  .weak EINT2_Interrupt
+  .weak EINT3_Interrupt
+  .weak ADC_Interrupt
+  .weak BOD_Interrupt
+  .weak USB_Interrupt
+  .weak CAN_Interrupt
+  .weak HPDMA_Interrupt
+  .weak I2C_Interrupt
+  .weak Ethernet_Interrupt
+  .weak RITINT_Interrupt
+  .weak MotorControlPWM_Interrupt
+  .weak QuadratureEncoder_Interrupt
+  .weak PLL1_Interrupt
+  .weak USBActivity_Interrupt
+  .weak CanActivity_Interrupt
+  
+    .set NMI_interrupt, Startup
+  .set Hardfault_interrupt, Startup
+  .set MemManage_interrupt, Startup
+  .set BusFault_interrupt, Startup
+  .set UsageFault_interrupt, Startup
+  .set SWI_interrupt, Startup
+  .set DebugMonitor_interrupt, Startup
+  .set PendingSV_interrupt, Startup
+  .set SysTick_interrupt, Startup
+  .set Watchdog_Interrupt, Startup
+  .set Timer0_Interrupt, Startup
+  .set Timer1_Interrupt, Startup
+  .set Timer2_Interrupt, Startup
+  .set Timer3_Interrupt, Startup
+  .set UART0_Interrupt, Startup
+  .set UART1_Interrupt, Startup
+  .set UART2_Interrupt, Startup
+  .set UART3_Interrupt, Startup
+  .set PWM1_Interrupt, Startup
+  .set I2C0_Interrupt, Startup
+  .set I2C1_Interrupt, Startup
+  .set I2C2_Interrupt, Startup
+  .set SPI_Interrupt, Startup
+  .set SSP0_Interrupt, Startup
+  .set SSP1_Interrupt, Startup
+  .set PLL0_Interrupt, Startup
+  .set RTC_Interrupt, Startup
+  .set EINT0_Interrupt, Startup
+  .set EINT1_Interrupt, Startup
+  .set EINT2_Interrupt, Startup
+  .set EINT3_Interrupt, Startup
+  .set ADC_Interrupt, Startup
+  .set BOD_Interrupt, Startup
+  .set USB_Interrupt, Startup
+  .set CAN_Interrupt, Startup
+  .set HPDMA_Interrupt, Startup
+  .set I2C_Interrupt, Startup
+  .set Ethernet_Interrupt, Startup
+  .set RITINT_Interrupt, Startup
+  .set MotorControlPWM_Interrupt, Startup
+  .set QuadratureEncoder_Interrupt, Startup
+  .set PLL1_Interrupt, Startup
+  .set USBActivity_Interrupt, Startup
+  .set CanActivity_Interrupt, Startup
+  
+  .text
 end;
 
 end.

rtl/embedded/arm/sc32442b.pp

@@ -8,7 +8,7 @@ unit sc32442b;
   interface
 
     var
-	   { Memory Controller }
+     { Memory Controller }
       BWSCON: longword 		absolute $48000000;
       BANKCON0: longword 	absolute $48000004;
       BANKCON1: longword 	absolute $48000008;
@@ -21,8 +21,8 @@ unit sc32442b;
       REFRESH: longword 	absolute $48000024;
       BANKSIZE: longword 	absolute $48000028;
       MRSRB6: longword 		absolute $4800002C;
-		
-		{ USB Host Controller }
+    
+    { USB Host Controller }
       HcRevision: longword 			absolute $49000000;
       HcControl: longword 				absolute $49000004;
       HcCommonStatus: longword 		absolute $49000008;
@@ -46,8 +46,8 @@ unit sc32442b;
       HcRhStatus: longword				absolute $49000050;
       HcRhPortStatus1: longword		absolute $49000054;
       HcRhPortStatus2: longword		absolute $49000058;
-		
-		{ Interrupt controller }
+    
+    { Interrupt controller }
       SRCPND: longword			absolute $4A000000;
       INTMOD: longword			absolute $4A000004;
       INTMSK: longword			absolute $4A000008;
@@ -56,291 +56,278 @@ unit sc32442b;
       INTOFFSET: longword		absolute $4A000014;
       SUBSRCPND: longword		absolute $4A000018;
       INTSUBMSK: longword		absolute $4A00001C;
-		
+    
     type
-	   TDMA = packed record
-		  DISRC,
-		  DISRCC,
-		  DIDST,
-		  DIDSTC,
-		  DCON,
-		  DSTAT,
-		  DCSRC,
-		  DCDST,
-		  DMASKTRIG: longword;
-		end;
-		
-	 var
-		{ DMA }
-		DMA0: TDMA	absolute $4B000000;
-		DMA1: TDMA	absolute $4B000040;
-		DMA2: TDMA	absolute $4B000080;
-		DMA3: TDMA	absolute $4B0000C0;
-		
-		{ Clock and power }
-		LOCKTIME: longword	absolute $4C000000;
-		MPLLCON: longword		absolute $4C000004;
-		UPLLCON: longword		absolute $4C000008;
-		CLKCON: longword		absolute $4C00000C;
-		CLKSLOW: longword		absolute $4C000010;
-		CLKDIVN: longword		absolute $4C000014;
-		CAMDIVN: longword		absolute $4C000018;
-		
-		{ LCD Controller }
-		LCDCON1: longword		absolute $4D000000;
-		LCDCON2: longword		absolute $4D000004;
-		LCDCON3: longword		absolute $4D000008;
-		LCDCON4: longword		absolute $4D00000C;
-		LCDCON5: longword		absolute $4D000010;
-		LCDSADDR1: longword	absolute $4D000014;
-		LCDSADDR2: longword	absolute $4D000018;
-		LCDSADDR3: longword	absolute $4D00001C;
-		REDLUT: longword		absolute $4D000020;
-		GREENLUT: longword	absolute $4D000024;
-		BLUELUT: longword		absolute $4D000028;
-		DITHMODE: longword	absolute $4D00004C;
-		TPAL: longword			absolute $4D000050;
-		LCDINTPND: longword	absolute $4D000054;
-		LCDSRCPND: longword	absolute $4D000058;
-		LCDINTMSK: longword	absolute $4D00005C;
-		TCONSEL: longword		absolute $4D000060;
-		
-		{ NAND Flash }
-		NFCONF: longword		absolute $4E000000;
-		NFCONT: longword		absolute $4E000004;
-		NFCMD: longword		absolute $4E000008;
-		NFADDR: longword		absolute $4E00000C;
-		NFDATA: longword		absolute $4E000010;
-		NFECC0: longword		absolute $4E000014;
-		NFECC1: longword		absolute $4E000018;
-		NFSECC: longword		absolute $4E00001C;
-		NFSTAT: longword		absolute $4E000020;
-		NFESTAT0: longword	absolute $4E000024;
-		NFESTAT1: longword	absolute $4E000028;
-		NFMECC0: longword		absolute $4E00002C;
-		NFMECC1: longword		absolute $4E000030;
-		NFSECC2: longword		absolute $4E000034;
-		NFSBLK: longword		absolute $4E000038;
-		NFEBLK: longword		absolute $4E00003C;
-		
+     TDMA = packed record
+      DISRC,
+      DISRCC,
+      DIDST,
+      DIDSTC,
+      DCON,
+      DSTAT,
+      DCSRC,
+      DCDST,
+      DMASKTRIG: longword;
+    end;
+    
+   var
+    { DMA }
+    DMA0: TDMA	absolute $4B000000;
+    DMA1: TDMA	absolute $4B000040;
+    DMA2: TDMA	absolute $4B000080;
+    DMA3: TDMA	absolute $4B0000C0;
+    
+    { Clock and power }
+    LOCKTIME: longword	absolute $4C000000;
+    MPLLCON: longword		absolute $4C000004;
+    UPLLCON: longword		absolute $4C000008;
+    CLKCON: longword		absolute $4C00000C;
+    CLKSLOW: longword		absolute $4C000010;
+    CLKDIVN: longword		absolute $4C000014;
+    CAMDIVN: longword		absolute $4C000018;
+    
+    { LCD Controller }
+    LCDCON1: longword		absolute $4D000000;
+    LCDCON2: longword		absolute $4D000004;
+    LCDCON3: longword		absolute $4D000008;
+    LCDCON4: longword		absolute $4D00000C;
+    LCDCON5: longword		absolute $4D000010;
+    LCDSADDR1: longword	absolute $4D000014;
+    LCDSADDR2: longword	absolute $4D000018;
+    LCDSADDR3: longword	absolute $4D00001C;
+    REDLUT: longword		absolute $4D000020;
+    GREENLUT: longword	absolute $4D000024;
+    BLUELUT: longword		absolute $4D000028;
+    DITHMODE: longword	absolute $4D00004C;
+    TPAL: longword			absolute $4D000050;
+    LCDINTPND: longword	absolute $4D000054;
+    LCDSRCPND: longword	absolute $4D000058;
+    LCDINTMSK: longword	absolute $4D00005C;
+    TCONSEL: longword		absolute $4D000060;
+    
+    { NAND Flash }
+    NFCONF: longword		absolute $4E000000;
+    NFCONT: longword		absolute $4E000004;
+    NFCMD: longword		absolute $4E000008;
+    NFADDR: longword		absolute $4E00000C;
+    NFDATA: longword		absolute $4E000010;
+    NFECC0: longword		absolute $4E000014;
+    NFECC1: longword		absolute $4E000018;
+    NFSECC: longword		absolute $4E00001C;
+    NFSTAT: longword		absolute $4E000020;
+    NFESTAT0: longword	absolute $4E000024;
+    NFESTAT1: longword	absolute $4E000028;
+    NFMECC0: longword		absolute $4E00002C;
+    NFMECC1: longword		absolute $4E000030;
+    NFSECC2: longword		absolute $4E000034;
+    NFSBLK: longword		absolute $4E000038;
+    NFEBLK: longword		absolute $4E00003C;
+    
     type
-	   TUART = packed record
-		  ULCON,
-		  UCON,
-		  UFCON,
-		  UMCON,
-		  UTRSTAT,
-		  UERSTAT,
-		  UFSTAT,
-		  UMSTAT,
-		  UTXH,
-		  URXH,
-		  UBRDIV: longword;
-		end;
-	 var
-		{ UART }
-		UART0: TUART		absolute $50000000;
-		UART1: TUART		absolute $50004000;
-		UART2: TUART		absolute $50008000;
-		
-	 type
-	   TPWMTimer = packed record
-		  TCNTB,
-		  TCMPB,
-		  TCNTO: longword;
-		end;
-	 var
-		{ PWM Timer }
-		TCFG0: longword		absolute $51000000;
-		TCFG1: longword 		absolute $51000004;
-		TCON: longword 		absolute $51000008;
-		PWMTimer: array[0..4] of TPWMTimer absolute $5100000C;
-		
-		{ USB Device }
-		FUNC_ADDR_REG: byte		absolute $52000140;
-		PWR_REG: byte				absolute $52000144;
-		EP_INT_REG: byte			absolute $52000148;
-		USB_INT_REG: byte			absolute $52000158;
-		EP_INT_EN_REG: byte		absolute $5200015C;
-		USB_INT_EN_REG: byte		absolute $5200016C;
-		FRAME_NUM1_REG: byte		absolute $52000170;
-		FRAME_NUM2_REG: byte		absolute $52000174;
-		INDEX_REG: byte			absolute $52000178;
-		EP0_CSR: byte				absolute $52000184;
-		IN_CSR1_REG: byte			absolute $52000184;
-		IN_CSR2_REG: byte			absolute $52000188;
-		MAXP_REG: byte				absolute $52000180;
-		OUT_CSR1_REG: byte		absolute $52000190;
-		OUT_CSR2_REG: byte		absolute $52000194;
-		OUT_FIFO_CNT1_REG: byte	absolute $52000198;
-		OUT_FIFO_CNT2_REG: byte	absolute $5200019C;
-		EP0_FIFO: byte				absolute $520001C0;
-		EP1_FIFO: byte				absolute $520001C4;
-		EP2_FIFO: byte				absolute $520001C8;
-		EP3_FIFO: byte				absolute $520001CC;
-		EP4_FIFO: byte				absolute $520001D0;
-		EP1_DMA_CON: byte			absolute $52000200;
-		EP1_DMA_UNIT: byte		absolute $52000204;
-		EP1_DMA_FIFO: byte		absolute $52000208;
-		EP1_DMA_TTC_L: byte		absolute $5200020C;
-		EP1_DMA_TTC_M: byte		absolute $52000210;
-		EP1_DMA_TTC_H: byte		absolute $52000214;
-		EP2_DMA_CON: byte			absolute $52000218;
-		EP2_DMA_UNIT: byte		absolute $5200021C;
-		EP2_DMA_FIFO: byte		absolute $52000220;
-		EP2_DMA_TTC_L: byte		absolute $52000224;
-		EP2_DMA_TTC_M: byte		absolute $52000228;
-		EP2_DMA_TTC_H: byte		absolute $5200022C;
-		EP3_DMA_CON: byte			absolute $52000240;
-		EP3_DMA_UNIT: byte		absolute $52000244;
-		EP3_DMA_FIFO: byte		absolute $52000248;
-		EP3_DMA_TTC_L: byte		absolute $5200024C;
-		EP3_DMA_TTC_M: byte		absolute $52000250;
-		EP3_DMA_TTC_H: byte		absolute $52000254;
-		EP4_DMA_CON: byte			absolute $52000258;
-		EP4_DMA_UNIT: byte		absolute $5200025C;
-		EP4_DMA_FIFO: byte		absolute $52000260;
-		EP4_DMA_TTC_L: byte		absolute $52000264;
-		EP4_DMA_TTC_M: byte		absolute $52000268;
-		EP4_DMA_TTC_H: byte		absolute $5200026C;
-		
-		{ Watchdog timer }
-		WTCON: longword		absolute $53000000;
-		WTDAT: longword		absolute $53000004;
-		WTCNT: longword		absolute $53000008;
-		
-		{ I2C }
-		IICCON: longword		absolute $54000000;
-		IICSTAT: longword		absolute $54000004;
-		IICADD: longword		absolute $54000008;
-		IICDS: longword		absolute $5400000C;
-		IICLC: longword		absolute $54000010;
-		
-		{ I2S }
-		IISCON: longword		absolute $55000000;
-		IISMOD: longword		absolute $55000004;
-		IISPSR: longword		absolute $55000008;
-		IISFCON: longword		absolute $5500000C;
-		IISFIFO: longword		absolute $55000010;
-		
-	 type
-	   TGPIO = packed record
-		  CON,
-		  DAT,
-		  DN: longword;
-		end;
-	 var
-		{ GPIO }
-		GPA: TGPIO		absolute $56000000;
-		GPB: TGPIO		absolute $56000010;
-		GPC: TGPIO		absolute $56000020;
-		GPD: TGPIO		absolute $56000030;
-		GPE: TGPIO		absolute $56000040;
-		GPF: TGPIO		absolute $56000050;
-		GPG: TGPIO		absolute $56000060;
-		GPH: TGPIO		absolute $56000070;
-		GPJ: TGPIO		absolute $560000D0;
-		MISCCR: longword		absolute $56000080;
-		DCLKCON: longword		absolute $56000084;
-		EXTINT0: longword		absolute $56000088;
-		EXTINT1: longword		absolute $5600008C;
-		EXTINT2: longword		absolute $56000090;
-		EINTFLT0: longword	absolute $56000094;
-		EINTFLT1: longword	absolute $56000098;
-		EINTFLT2: longword	absolute $5600009C;
-		EINTFLT3: longword	absolute $560000A0;
-		EINTMASK: longword	absolute $560000A4;
-		EINTPEND: longword	absolute $560000A8;
-		GSTATUS0: longword	absolute $560000AC;
-		GSTATUS1: longword	absolute $560000B0;
-		GSTATUS2: longword	absolute $560000B4;
-		GSTATUS3: longword	absolute $560000B8;
-		GSTATUS4: longword	absolute $560000BC;
-		MSLCON: longword		absolute $560000CC;
-		
-		{ RTC }
-		RTCCON: byte		absolute $57000040;
-		TICNT: byte			absolute $57000044;
-		RTCALM: byte		absolute $57000050;
-		ALMSEC: byte		absolute $57000054;
-		ALMMIN: byte		absolute $57000058;
-		ALMHOUR: byte		absolute $5700005C;
-		ALMDATE: byte		absolute $57000060;
-		ALMMON: byte		absolute $57000064;
-		ALMYEAR: byte		absolute $57000068;
-		BCDSEC: byte		absolute $57000070;
-		BCDMIN: byte		absolute $57000074;
-		BCDHOUR: byte		absolute $57000078;
-		BCDDATE: byte		absolute $5700007C;
-		BCDDAY: byte		absolute $57000080;
-		BCDMON: byte		absolute $57000084;
-		BCDYEAR: byte		absolute $57000088;
-		RTCLBAT: byte		absolute $5700006C;
-		
-		{ AD converter }
-		ADCCON: longword		absolute $58000000;
-		ADCTSC: longword		absolute $58000004;
-		ADCDLY: longword		absolute $58000008;
-		ADCDAT0: longword		absolute $5800000C;
-		ADCDAT1: longword		absolute $58000010;
-		ADCUPDN: longword		absolute $58000014;
-		
-	 type
-	   TSPI = packed record
-		  SPCON,
-		  SPSTA,
-		  SPPIN,
-		  SPPRE,
-		  SPTDAT,
-		  SPRDAT: longword;
-		end;
-	 var
-		{ SPI }
-		SPI0: TSPI		absolute $59000000;
-		SPI1: TSPI		absolute $59000020;
-		
-		{ SD Interface }
-		SDICON: longword		absolute $5A000000;
-		SDIPRE: longword		absolute $5A000004;
-		SDICARG: longword		absolute $5A000008;
-		SDICCON: longword		absolute $5A00000C;
-		SDICSTA: longword		absolute $5A000010;
-		SDIRSP0: longword		absolute $5A000014;
-		SDIRSP1: longword		absolute $5A000018;
-		SDIRSP2: longword		absolute $5A00001C;
-		SDIRSP3: longword		absolute $5A000020;
-		SDIDTIMER: longword	absolute $5A000024;
-		SDIBSIZE: longword	absolute $5A000028;
-		SDIDCON: longword		absolute $5A00002C;
-		SDIDCNT: longword		absolute $5A000030;
-		SDIDSTA: longword		absolute $5A000034;
-		SDIFSTA: longword		absolute $5A000038;
-		SDIIMSK: longword		absolute $5A00003C;
-		SDIDAT: byte			absolute $5A000040;
-		
-    var
-      Undefined_Handler,
-      SWI_Handler,
-      Prefetch_Handler,
-      Abort_Handler,
-      IRQ_Handler,
-      FIQ_Handler : pointer;
+     TUART = packed record
+      ULCON,
+      UCON,
+      UFCON,
+      UMCON,
+      UTRSTAT,
+      UERSTAT,
+      UFSTAT,
+      UMSTAT,
+      UTXH,
+      URXH,
+      UBRDIV: longword;
+    end;
+   var
+    { UART }
+    UART0: TUART		absolute $50000000;
+    UART1: TUART		absolute $50004000;
+    UART2: TUART		absolute $50008000;
+    
+   type
+     TPWMTimer = packed record
+      TCNTB,
+      TCMPB,
+      TCNTO: longword;
+    end;
+   var
+    { PWM Timer }
+    TCFG0: longword		absolute $51000000;
+    TCFG1: longword 		absolute $51000004;
+    TCON: longword 		absolute $51000008;
+    PWMTimer: array[0..4] of TPWMTimer absolute $5100000C;
+    
+    { USB Device }
+    FUNC_ADDR_REG: byte		absolute $52000140;
+    PWR_REG: byte				absolute $52000144;
+    EP_INT_REG: byte			absolute $52000148;
+    USB_INT_REG: byte			absolute $52000158;
+    EP_INT_EN_REG: byte		absolute $5200015C;
+    USB_INT_EN_REG: byte		absolute $5200016C;
+    FRAME_NUM1_REG: byte		absolute $52000170;
+    FRAME_NUM2_REG: byte		absolute $52000174;
+    INDEX_REG: byte			absolute $52000178;
+    EP0_CSR: byte				absolute $52000184;
+    IN_CSR1_REG: byte			absolute $52000184;
+    IN_CSR2_REG: byte			absolute $52000188;
+    MAXP_REG: byte				absolute $52000180;
+    OUT_CSR1_REG: byte		absolute $52000190;
+    OUT_CSR2_REG: byte		absolute $52000194;
+    OUT_FIFO_CNT1_REG: byte	absolute $52000198;
+    OUT_FIFO_CNT2_REG: byte	absolute $5200019C;
+    EP0_FIFO: byte				absolute $520001C0;
+    EP1_FIFO: byte				absolute $520001C4;
+    EP2_FIFO: byte				absolute $520001C8;
+    EP3_FIFO: byte				absolute $520001CC;
+    EP4_FIFO: byte				absolute $520001D0;
+    EP1_DMA_CON: byte			absolute $52000200;
+    EP1_DMA_UNIT: byte		absolute $52000204;
+    EP1_DMA_FIFO: byte		absolute $52000208;
+    EP1_DMA_TTC_L: byte		absolute $5200020C;
+    EP1_DMA_TTC_M: byte		absolute $52000210;
+    EP1_DMA_TTC_H: byte		absolute $52000214;
+    EP2_DMA_CON: byte			absolute $52000218;
+    EP2_DMA_UNIT: byte		absolute $5200021C;
+    EP2_DMA_FIFO: byte		absolute $52000220;
+    EP2_DMA_TTC_L: byte		absolute $52000224;
+    EP2_DMA_TTC_M: byte		absolute $52000228;
+    EP2_DMA_TTC_H: byte		absolute $5200022C;
+    EP3_DMA_CON: byte			absolute $52000240;
+    EP3_DMA_UNIT: byte		absolute $52000244;
+    EP3_DMA_FIFO: byte		absolute $52000248;
+    EP3_DMA_TTC_L: byte		absolute $5200024C;
+    EP3_DMA_TTC_M: byte		absolute $52000250;
+    EP3_DMA_TTC_H: byte		absolute $52000254;
+    EP4_DMA_CON: byte			absolute $52000258;
+    EP4_DMA_UNIT: byte		absolute $5200025C;
+    EP4_DMA_FIFO: byte		absolute $52000260;
+    EP4_DMA_TTC_L: byte		absolute $52000264;
+    EP4_DMA_TTC_M: byte		absolute $52000268;
+    EP4_DMA_TTC_H: byte		absolute $5200026C;
+    
+    { Watchdog timer }
+    WTCON: longword		absolute $53000000;
+    WTDAT: longword		absolute $53000004;
+    WTCNT: longword		absolute $53000008;
+    
+    { I2C }
+    IICCON: longword		absolute $54000000;
+    IICSTAT: longword		absolute $54000004;
+    IICADD: longword		absolute $54000008;
+    IICDS: longword		absolute $5400000C;
+    IICLC: longword		absolute $54000010;
+    
+    { I2S }
+    IISCON: longword		absolute $55000000;
+    IISMOD: longword		absolute $55000004;
+    IISPSR: longword		absolute $55000008;
+    IISFCON: longword		absolute $5500000C;
+    IISFIFO: longword		absolute $55000010;
+    
+   type
+     TGPIO = packed record
+      CON,
+      DAT,
+      DN: longword;
+    end;
+   var
+    { GPIO }
+    GPA: TGPIO		absolute $56000000;
+    GPB: TGPIO		absolute $56000010;
+    GPC: TGPIO		absolute $56000020;
+    GPD: TGPIO		absolute $56000030;
+    GPE: TGPIO		absolute $56000040;
+    GPF: TGPIO		absolute $56000050;
+    GPG: TGPIO		absolute $56000060;
+    GPH: TGPIO		absolute $56000070;
+    GPJ: TGPIO		absolute $560000D0;
+    MISCCR: longword		absolute $56000080;
+    DCLKCON: longword		absolute $56000084;
+    EXTINT0: longword		absolute $56000088;
+    EXTINT1: longword		absolute $5600008C;
+    EXTINT2: longword		absolute $56000090;
+    EINTFLT0: longword	absolute $56000094;
+    EINTFLT1: longword	absolute $56000098;
+    EINTFLT2: longword	absolute $5600009C;
+    EINTFLT3: longword	absolute $560000A0;
+    EINTMASK: longword	absolute $560000A4;
+    EINTPEND: longword	absolute $560000A8;
+    GSTATUS0: longword	absolute $560000AC;
+    GSTATUS1: longword	absolute $560000B0;
+    GSTATUS2: longword	absolute $560000B4;
+    GSTATUS3: longword	absolute $560000B8;
+    GSTATUS4: longword	absolute $560000BC;
+    MSLCON: longword		absolute $560000CC;
+    
+    { RTC }
+    RTCCON: byte		absolute $57000040;
+    TICNT: byte			absolute $57000044;
+    RTCALM: byte		absolute $57000050;
+    ALMSEC: byte		absolute $57000054;
+    ALMMIN: byte		absolute $57000058;
+    ALMHOUR: byte		absolute $5700005C;
+    ALMDATE: byte		absolute $57000060;
+    ALMMON: byte		absolute $57000064;
+    ALMYEAR: byte		absolute $57000068;
+    BCDSEC: byte		absolute $57000070;
+    BCDMIN: byte		absolute $57000074;
+    BCDHOUR: byte		absolute $57000078;
+    BCDDATE: byte		absolute $5700007C;
+    BCDDAY: byte		absolute $57000080;
+    BCDMON: byte		absolute $57000084;
+    BCDYEAR: byte		absolute $57000088;
+    RTCLBAT: byte		absolute $5700006C;
+    
+    { AD converter }
+    ADCCON: longword		absolute $58000000;
+    ADCTSC: longword		absolute $58000004;
+    ADCDLY: longword		absolute $58000008;
+    ADCDAT0: longword		absolute $5800000C;
+    ADCDAT1: longword		absolute $58000010;
+    ADCUPDN: longword		absolute $58000014;
+    
+   type
+     TSPI = packed record
+      SPCON,
+      SPSTA,
+      SPPIN,
+      SPPRE,
+      SPTDAT,
+      SPRDAT: longword;
+    end;
+   var
+    { SPI }
+    SPI0: TSPI		absolute $59000000;
+    SPI1: TSPI		absolute $59000020;
+    
+    { SD Interface }
+    SDICON: longword		absolute $5A000000;
+    SDIPRE: longword		absolute $5A000004;
+    SDICARG: longword		absolute $5A000008;
+    SDICCON: longword		absolute $5A00000C;
+    SDICSTA: longword		absolute $5A000010;
+    SDIRSP0: longword		absolute $5A000014;
+    SDIRSP1: longword		absolute $5A000018;
+    SDIRSP2: longword		absolute $5A00001C;
+    SDIRSP3: longword		absolute $5A000020;
+    SDIDTIMER: longword	absolute $5A000024;
+    SDIBSIZE: longword	absolute $5A000028;
+    SDIDCON: longword		absolute $5A00002C;
+    SDIDCNT: longword		absolute $5A000030;
+    SDIDSTA: longword		absolute $5A000034;
+    SDIFSTA: longword		absolute $5A000038;
+    SDIIMSK: longword		absolute $5A00003C;
+    SDIDAT: byte			absolute $5A000040;
 
   implementation
 
-    procedure AT91F_Default_FIQ_handler; assembler; nostackframe; public name 'AT91F_Default_FIQ_handler';
-      asm
-      .Lloop:
-        b .Lloop
-      end;
-
-    procedure AT91F_Default_IRQ_handler; assembler; nostackframe; public name 'AT91F_Default_IRQ_handler';
-      asm
-      .Lloop:
-        b .Lloop
-      end;
-
-    procedure AT91F_Spurious_handler; assembler; nostackframe; public name 'AT91F_Spurious_handler';
+    procedure UndefinedInstrHandler; external name 'UndefinedInstrHandler';
+    procedure SWIHandler; external name 'SWIHandler';
+    procedure PrefetchAbortHandler; external name 'PrefetchAbortHandler';
+    procedure DataAbortHandler; external name 'DataAbortHandler';
+    procedure IRQHandler; external name 'IRQHandler';
+    procedure FIQHandler; external name 'FIQHandler';
+        
+    procedure DefaultExceptionHandler; assembler; nostackframe;
       asm
       .Lloop:
         b .Lloop
@@ -370,45 +357,40 @@ unit sc32442b;
         .align 16
         .globl _start
         b   _start
-        b   .LUndefined_Addr  // Undefined Instruction vector
-        b   .LSWI_Addr        // Software Interrupt vector
-        b   .LPrefetch_Addr   // Prefetch abort vector
-        b   .LAbort_Addr      // Data abort vector
+        ldr pc, .LUndefined_Addr  // Undefined Instruction vector
+        ldr pc, .LSWI_Addr        // Software Interrupt vector
+        ldr pc, .LPrefetch_Addr   // Prefetch abort vector
+        ldr pc, .LAbort_Addr      // Data abort vector
         nop                   // reserved
-        b   .LIRQ_Addr        // Interrupt Request (IRQ) vector
-        b   .LFIQ_Addr        // Fast interrupt request (FIQ) vector
+        ldr pc, .LIRQ_Addr        // Interrupt Request (IRQ) vector
+        ldr pc, .LFIQ_Addr        // Fast interrupt request (FIQ) vector
 
     .LUndefined_Addr:
-        ldr r0,.L1
-        ldr pc,[r0]
+        .long UndefinedInstrHandler
     .LSWI_Addr:
-        ldr r0,.L2
-        ldr pc,[r0]
+        .long SWIHandler
     .LPrefetch_Addr:
-        ldr r0,.L3
-        ldr pc,[r0]
+        .long PrefetchAbortHandler
     .LAbort_Addr:
-        ldr r0,.L4
-        ldr pc,[r0]
+        .long DataAbortHandler
     .LIRQ_Addr:
-        ldr r0,.L5
-        ldr pc,[r0]
+        .long IRQHandler
     .LFIQ_Addr:
-        ldr r0,.L5
-        ldr pc,[r0]
+        .long FIQHandler
 
-    .L1:
-        .long     Undefined_Handler
-    .L2:
-        .long     SWI_Handler
-    .L3:
-        .long     Prefetch_Handler
-    .L4:
-        .long     Abort_Handler
-    .L5:
-        .long     IRQ_Handler
-    .L6:
-        .long     FIQ_Handler
+        .weak UndefinedInstrHandler
+        .weak SWIHandler
+        .weak PrefetchAbortHandler
+        .weak DataAbortHandler
+        .weak IRQHandler
+        .weak FIQHandler
+        
+        .set UndefinedInstrHandler, DefaultExceptionHandler
+        .set SWIHandler, DefaultExceptionHandler
+        .set PrefetchAbortHandler, DefaultExceptionHandler
+        .set DataAbortHandler, DefaultExceptionHandler
+        .set IRQHandler, DefaultExceptionHandler
+        .set FIQHandler, DefaultExceptionHandler
 
     _start:
         (*
@@ -454,21 +436,6 @@ unit sc32442b;
         msr   CPSR_c, #0x1f   // switch to System Mode, interrupts enabled
         mov   sp, r0
 
-        // for now, all handlers are set to a default one
-        ldr r1,.LDefaultHandlerAddr
-        ldr r0,.L1
-        str r1,[r0]
-        ldr r0,.L2
-        str r1,[r0]
-        ldr r0,.L3
-        str r1,[r0]
-        ldr r0,.L4
-        str r1,[r0]
-        ldr r0,.L5
-        str r1,[r0]
-        ldr r0,.L6
-        str r1,[r0]
-
         // copy initialized data from flash to ram
         ldr r1,.L_etext
         ldr r2,.L_data
@@ -502,11 +469,6 @@ unit sc32442b;
         .long _edata
 .L_stack_top:
         .long _stack_top
-.LDefaultHandlerAddr:
-        .long .LDefaultHandler
-        // default irq handler just returns
-.LDefaultHandler:
-        mov pc,r14
         .text
       end;
 

rtl/embedded/arm/stm32f103.pp

@@ -1,683 +0,0 @@
-{
-Register definitions and utility code for STM32F103
-Preliminary startup code - TODO: interrupt handler variables
-
-Created by Jeppe Johansen 2009 - [email protected]
-}
-unit stm32f103;
-
-{$goto on}
-{$define stm32f103}
-
-interface
-
-type
- TBitvector32 = bitpacked array[0..31] of 0..1;
-
-{$PACKRECORDS 2}
-const
- PeripheralBase 	= $40000000;
-
- FSMCBase			= $60000000;
-
- APB1Base 			= PeripheralBase;
- APB2Base 			= PeripheralBase+$10000;
- AHBBase 			= PeripheralBase+$20000;
-
- SCS_BASE         = $E000E000;
-
- { FSMC }
- FSMCBank1NOR1		= FSMCBase+$00000000;
- FSMCBank1NOR2		= FSMCBase+$04000000;
- FSMCBank1NOR3		= FSMCBase+$08000000;
- FSMCBank1NOR4		= FSMCBase+$0C000000;
-
- FSMCBank1PSRAM1	= FSMCBase+$00000000;
- FSMCBank1PSRAM2	= FSMCBase+$04000000;
- FSMCBank1PSRAM3	= FSMCBase+$08000000;
- FSMCBank1PSRAM4	= FSMCBase+$0C000000;
-
- FSMCBank2NAND1	= FSMCBase+$10000000;
- FSMCBank3NAND2	= FSMCBase+$20000000;
-
- FSMCBank4PCCARD	= FSMCBase+$30000000;
-
-type
- TTimerRegisters = record
-  CR1, res1,
-  CR2, res2,
-  SMCR, res3,
-  DIER, res4,
-  SR, res5,
-  EGR, res,
-  CCMR1, res6,
-  CCMR2, res7,
-  CCER, res8,
-  CNT, res9,
-  PSC, res10,
-  ARR, res11,
-  RCR, res12,
-  CCR1, res13,
-  CCR2, res14,
-  CCR3, res15,
-  CCR4, res16,
-  BDTR, res17,
-  DCR, res18,
-  DMAR, res19: Word;
- end;
-
- TRTCRegisters = record
-  CRH, res1,
-  CRL, res2,
-  PRLH, res3,
-  PRLL, res4,
-  DIVH, res5,
-  DIVL, res6,
-  CNTH, res7,
-  CNTL, res8,
-  ALRH, res9,
-  ALRL, res10: Word;
- end;
-
- TIWDGRegisters = record
-  KR, res1,
-  PR, res2,
-  RLR, res3,
-  SR, res4: word;
- end;
-
- TWWDGRegisters = record
-  CR, res2,
-  CFR, res3,
-  SR, res4: word;
- end;
-
- TSPIRegisters = record
-  CR1, res1,
-  CR2, res2,
-  SR, res3,
-  DR, res4,
-  CRCPR, res5,
-  RXCRCR, res6,
-  TXCRCR, res7,
-  I2SCFGR, res8,
-  I2SPR, res9: Word;
- end;
-
- TUSARTRegisters = record
-  SR, res1,
-  DR, res2,
-  BRR, res3,
-  CR1, res4,
-  CR2, res5,
-  CR3, res6,
-  GTPR, res7: Word;
- end;
-
- TI2CRegisters = record
-  CR1, res1,
-  CR2, res2,
-  OAR1, res3,
-  OAR2, res4,
-  DR, res5,
-  SR1, res6,
-  SR2, res7,
-  CCR, res8: word;
-  TRISE: byte;
- end;
-
- TUSBRegisters = record
-  EPR: array[0..7] of DWord;
-
-  res: array[0..7] of dword;
-
-  CNTR, res1,
-  ISTR, res2,
-  FNR, res3: Word;
-  DADDR: byte; res4: word; res5: byte;
-  BTABLE: Word;
- end;
-
- TUSBMem = packed array[0..511] of byte;
-
- TCANMailbox = record
-  IR,
-  DTR,
-  DLR,
-  DHR: DWord;
- end;
-
- TCANRegisters = record
-  MCR,
-  MSR,
-  TSR,
-  RF0R,
-  RF1R,
-  IER,
-  ESR,
-  BTR: DWord;
-
-  res5: array[$020..$17F] of byte;
-
-  TX: array[0..2] of TCANMailbox;
-  RX: array[0..2] of TCANMailbox;
-
-  res6: array[$1D0..$1FF] of byte;
-
-  FMR,
-  FM1R,
-  res9: DWord;
-  FS1R, res10: word;
-  res11: DWord;
-  FFA1R, res12: word;
-  res13: DWord;
-  FA1R, res14: word;
-  res15: array[$220..$23F] of byte;
-
-  FOR1,
-  FOR2: DWord;
-
-  FB: array[1..13] of array[1..2] of DWord;
- end;
-
- TBKPRegisters = record
-  DR: array[1..10] of record data, res: word; end;
-
-  RTCCR,
-  CR,
-  CSR,
-  res1,res2: DWord;
-
-  DR2: array[11..42] of record data, res: word; end;
- end;
-
- TPwrRegisters = record
-  CR, res: word;
-  CSR: Word;
- end;
-
- TDACRegisters = record
-  CR,
-  SWTRIGR: DWord;
-
-  DHR12R1, res2,
-  DHR12L1, res3,
-  DHR8R1, res4,
-  DHR12R2, res5,
-  DHR12L2, res6,
-  DHR8R2, res7: word;
-
-  DHR12RD,
-  DHR12LD: DWord;
-
-  DHR8RD, res8,
-
-  DOR1, res9,
-  DOR2, res10: Word;
- end;
-
- TAFIORegisters = record
-  EVCR,
-  MAPR: DWord;
-  EXTICR: array[0..3] of DWord;
- end;
-
- TEXTIRegisters = record
-  IMR,
-  EMR,
-  RTSR,
-  FTSR,
-  SWIER,
-  PR: DWord;
- end;
-
- TPortRegisters = record
-  CRL,
-  CRH,
-  IDR,
-  ODR,
-  BSRR,
-  BRR,
-  LCKR: DWord;
- end;
-
- TADCRegisters = record
-  SR,
-  CR1,
-  CR2,
-  SMPR1,
-  SMPR2: DWord;
-  JOFR1, res2,
-  JOFR2, res3,
-  JOFR3, res4,
-  JOFR4, res5,
-  HTR, res6,
-  LTR, res7: word;
-  SQR1,
-  SQR2,
-  SQR3,
-  JSQR: DWord;
-  JDR1, res8,
-  JDR2, res9,
-  JDR3, res10,
-  JDR4, res11: Word;
-  DR: DWord;
- end;
-
- TSDIORegisters = record
-  POWER,
-  CLKCR,
-  ARG: DWord;
-  CMD, res3,
-  RESPCMD, res4: Word;
-  RESP1,
-  RESP2,
-  RESP3,
-  RESP4,
-  DTIMER,
-  DLEN: DWord;
-  DCTRL, res5: word;
-  DCOUNT,
-  STA,
-  ICR,
-  MASK,
-  FIFOCNT,
-  FIFO: DWord;
- end;
-
- TDMAChannel = record
-  CCR, res1,
-  CNDTR, res2: word;
-  CPAR,
-  CMAR,
-  res: DWord;
- end;
-
- TDMARegisters = record
-  ISR,
-  IFCR: DWord;
-  Channel: array[0..7] of TDMAChannel;
- end;
-
- TRCCRegisters = record
-  CR,
-  CFGR,
-  CIR,
-  APB2RSTR,
-  APB1RSTR,
-  AHBENR,
-  APB2ENR,
-  APB1ENR,
-  BDCR,
-  CSR: DWord;
- end;
-
- TCRCRegisters = record
-  DR: DWord;
-  IDR: byte; res1: word; res2: byte;
-  CR: byte;
- end;
-
- TFSMCRegisters = record
-  nothingyet: byte;
- end;
-
- TFlashRegisters = record
-  ACR,
-  KEYR,
-  OPTKEYR,
-  SR,
-  CR,
-  AR,
-  res,
-  OBR,
-  WRPR: DWord;
- end;
-
- TNVICRegisters = packed record
-  ISER: array[0..7] of longword;
-   reserved0: array[0..23] of longword;
-  ICER: array[0..7] of longword;
-   reserved1: array[0..23] of longword;
-  ISPR: array[0..7] of longword;
-   reserved2: array[0..23] of longword;
-  ICPR: array[0..7] of longword;
-   reserved3: array[0..23] of longword;
-  IABR: array[0..7] of longword;
-   reserved4: array[0..55] of longword;
-  IP: array[0..239] of longword;
-   reserved5: array[0..643] of longword;
-  STIR: longword;
- end;
-
- TSCBRegisters = packed record
-  CPUID,                            {!< CPU ID Base Register                                     }
-  ICSR,                             {!< Interrupt Control State Register                         }
-  VTOR,                             {!< Vector Table Offset Register                             }
-  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
-  SCR,                              {!< System Control Register                                  }
-  CCR: longword;                    {!< Configuration Control Register                           }
-  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
-  SHCSR,                            {!< System Handler Control and State Register                }
-  CFSR,                             {!< Configurable Fault Status Register                       }
-  HFSR,                             {!< Hard Fault Status Register                               }
-  DFSR,                             {!< Debug Fault Status Register                              }
-  MMFAR,                            {!< Mem Manage Address Register                              }
-  BFAR,                             {!< Bus Fault Address Register                               }
-  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
-  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
-  DFR,                              {!< Debug Feature Register                                   }
-  ADR: longword;                    {!< Auxiliary Feature Register                               }
-  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
-  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
- end;
-
- TSysTickRegisters = packed record
-  Ctrl,
-  Load,
-  Val,
-  Calib: longword;
- end;
-
-{$ALIGN 2}
-var
- { Timers }
- Timer1: TTimerRegisters 	absolute (APB2Base+$2C00);
- Timer2: TTimerRegisters 	absolute (APB1Base+$0000);
- Timer3: TTimerRegisters 	absolute (APB1Base+$0400);
- Timer4: TTimerRegisters 	absolute (APB1Base+$0800);
- Timer5: TTimerRegisters 	absolute (APB1Base+$0C00);
- Timer6: TTimerRegisters 	absolute (APB1Base+$1000);
- Timer7: TTimerRegisters 	absolute (APB1Base+$1400);
- Timer8: TTimerRegisters 	absolute (APB2Base+$3400);
-
- { RTC }
- RTC: TRTCRegisters 			absolute (APB1Base+$2800);
-
- { WDG }
- WWDG: TWWDGRegisters 		absolute (APB1Base+$2C00);
- IWDG: TIWDGRegisters 		absolute (APB1Base+$3000);
-
- { SPI }
- SPI1: TSPIRegisters			absolute (APB2Base+$3000);
- SPI2: TSPIRegisters			absolute (APB1Base+$3800);
- SPI3: TSPIRegisters			absolute (APB1Base+$3C00);
-
- { USART/UART }
- USART1: TUSARTRegisters	absolute (APB2Base+$3800);
- USART2: TUSARTRegisters	absolute (APB1Base+$4400);
- USART3: TUSARTRegisters	absolute (APB1Base+$4800);
- UART4: TUSARTRegisters		absolute (APB1Base+$4C00);
- UART5: TUSARTRegisters		absolute (APB1Base+$5000);
-
- { I2C }
- I2C1: TI2CRegisters			absolute (APB1Base+$5400);
- I2C2: TI2CRegisters			absolute (APB1Base+$5800);
-
- { USB }
- USB: TUSBRegisters			absolute (APB1Base+$5C00);
- USBMem: TUSBMem                        absolute (APB1Base+$6000);
-
- { CAN }
- CAN: TCANRegisters			absolute (APB1Base+$6800);
-
- { BKP }
- BKP: TBKPRegisters			absolute (APB1Base+$6C00);
-
- { PWR }
- PWR: TPwrRegisters			absolute (APB1Base+$7000);
-
- { DAC }
- DAC: TDACRegisters			absolute (APB1Base+$7400);
-
- { GPIO }
- AFIO: TAFIORegisters		absolute (APB2Base+$0);
- EXTI: TEXTIRegisters		absolute (APB2Base+$0400);
-
- PortA: TPortRegisters		absolute (APB2Base+$0800);
- PortB: TPortRegisters		absolute (APB2Base+$0C00);
- PortC: TPortRegisters		absolute (APB2Base+$1000);
- PortD: TPortRegisters		absolute (APB2Base+$1400);
- PortE: TPortRegisters		absolute (APB2Base+$1800);
- PortF: TPortRegisters		absolute (APB2Base+$1C00);
- PortG: TPortRegisters		absolute (APB2Base+$2000);
-
- { ADC }
- ADC1: TADCRegisters			absolute (APB2Base+$2400);
- ADC2: TADCRegisters			absolute (APB2Base+$2800);
- ADC3: TADCRegisters			absolute (APB2Base+$3C00);
-
- { SDIO }
- SDIO: TSDIORegisters		absolute (APB2Base+$8000);
-
- { DMA }
- DMA1: TDMARegisters			absolute (AHBBase+$0000);
- DMA2: TDMARegisters			absolute (AHBBase+$0400);
-
- { RCC }
- RCC: TRCCRegisters			absolute (AHBBase+$1000);
-
- { Flash }
- Flash: TFlashRegisters		absolute (AHBBase+$2000);
-
- { CRC }
- CRC: TCRCRegisters			absolute (AHBBase+$3000);
-
- { SCB }
- SCB: TSCBRegisters        absolute (SCS_BASE+$0D00);
-
- { SysTick }
- SysTick: TSysTickRegisters   absolute (SCS_BASE+$0010);
-
- { NVIC }
- NVIC: TNVICRegisters      absolute (SCS_BASE+$0100);
-
-var
-	NMI_Handler,
-	HardFault_Handler,
-	MemManage_Handler,
-	BusFault_Handler,
-	UsageFault_Handler,
-	SWI_Handler,
-	DebugMonitor_Handler,
-	PendingSV_Handler,
-	Systick_Handler: pointer;
-
-implementation
-
-var
-	_data: record end; external name '_data';
-	_edata: record end; external name '_edata';
-	_etext: record end; external name '_etext';
-	_bss_start: record end; external name '_bss_start';
-	_bss_end: record end; external name '_bss_end';
-	_stack_top: record end; external name '_stack_top';
-
-procedure PASCALMAIN; external name 'PASCALMAIN';
-
-procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
-asm
-.Lhalt:
-	b .Lhalt
-end;
-
-procedure _FPC_start; assembler; nostackframe;
-label _start;
-asm
-	.init
-	.balign 16
-	
-	.long _stack_top	 			// First entry in NVIC table is the new stack pointer
-	.long _start+1
-	//b   _start					// Reset
-	.long _start+1
-	//b	 .LNMI_Addr				// Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
-	.long _start+1
-	//b	 .LHardFault_Addr		// All class of fault
-	.long _start+1
-	//b	 .LMemManage_Addr		// Memory management
-	.long _start+1
-	//b	 .LBusFault_Addr		// Pre-fetch fault, memory access fault
-	.long _start+1
-	//b	 .LUsageFault_Addr	// Undefined instruction or illegal state
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//b	 .LSWI_Addr				// Software Interrupt vector
-	.long _start+1
-	//b	 .LDebugMonitor_Addr	// Debug Monitor
-	.long _start+1
-	//nop							// Reserved
-	.long _start+1
-	//b	 .LPendingSV_Addr		//	Pendable request for system service
-	.long _start+1
-	//b	 .LSystick_Addr		// System tick timer
-	//17
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	//20
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-	.long .LDefaultHandler+1
-
-.LNMI_Addr:
-	ldr r0,.L1
-	ldr pc,[r0]
-.LHardFault_Addr:
-	ldr r0,.L2
-	ldr pc,[r0]
-.LMemManage_Addr:
-	ldr r0,.L3
-	ldr pc,[r0]
-.LBusFault_Addr:
-	ldr r0,.L4
-	ldr pc,[r0]
-.LUsageFault_Addr:
-	ldr r0,.L5
-	ldr pc,[r0]
-.LSWI_Addr:
-	ldr r0,.L6
-	ldr pc,[r0]
-.LDebugMonitor_Addr:
-	ldr r0,.L7
-	ldr pc,[r0]
-.LPendingSV_Addr:
-	ldr r0,.L8
-	ldr pc,[r0]
-.LSystick_Addr:
-	ldr r0,.L9
-	ldr pc,[r0]
-
-.L1:
-	.long NMI_Handler
-.L2:
-	.long HardFault_Handler
-.L3:
-	.long MemManage_Handler
-.L4:
-	.long BusFault_Handler
-.L5:
-	.long UsageFault_Handler
-.L6:
-	.long SWI_Handler
-.L7:
-	.long DebugMonitor_Handler
-.L8:
-	.long PendingSV_Handler
-.L9:
-	.long Systick_Handler
-
-	.globl _start
-	.text
-_start:
-	
-	// Copy initialized data to ram
-	ldr r1,.L_etext
-	ldr r2,.L_data
-	ldr r3,.L_edata
-.Lcopyloop:
-	cmp r2,r3
-	ittt ls
-	ldrls r0,[r1],#4
-	strls r0,[r2],#4
-	bls .Lcopyloop
-
-	// clear onboard ram
-	ldr r1,.L_bss_start
-	ldr r2,.L_bss_end
-	mov r0,#0
-.Lzeroloop:
-	cmp r1,r2
-	itt ls
-	strls r0,[r1],#4
-	bls .Lzeroloop
-
-	b PASCALMAIN
-	b _FPC_haltproc
-
-.L_bss_start:
-	.long _bss_start
-.L_bss_end:
-	.long _bss_end
-.L_etext:
-	.long _etext
-.L_data:
-	.long _data
-.L_edata:
-	.long _edata
-.LDefaultHandlerAddr:
-	.long .LDefaultHandler
-	// default irq handler just returns
-.LDefaultHandler:
-	mov pc,r14
-end;
-
-end.
-

rtl/embedded/arm/stm32f10x_conn.pp

@@ -0,0 +1,788 @@
+{
+Register definitions and utility code for STM32F10x - Connectivity line
+
+Created by Jeppe Johansen 2012 - [email protected]
+}
+unit stm32f10x_conn;
+
+{$goto on}
+{$define stm32f10x_conn}
+
+interface
+
+type
+ TBitvector32 = bitpacked array[0..31] of 0..1;
+
+{$PACKRECORDS 2}
+const
+ PeripheralBase 	= $40000000;
+
+ FSMCBase			= $60000000;
+
+ APB1Base 			= PeripheralBase;
+ APB2Base 			= PeripheralBase+$10000;
+ AHBBase 			= PeripheralBase+$20000;
+
+ SCS_BASE         = $E000E000;
+
+ { FSMC }
+ FSMCBank1NOR1		= FSMCBase+$00000000;
+ FSMCBank1NOR2		= FSMCBase+$04000000;
+ FSMCBank1NOR3		= FSMCBase+$08000000;
+ FSMCBank1NOR4		= FSMCBase+$0C000000;
+
+ FSMCBank1PSRAM1	= FSMCBase+$00000000;
+ FSMCBank1PSRAM2	= FSMCBase+$04000000;
+ FSMCBank1PSRAM3	= FSMCBase+$08000000;
+ FSMCBank1PSRAM4	= FSMCBase+$0C000000;
+
+ FSMCBank2NAND1	= FSMCBase+$10000000;
+ FSMCBank3NAND2	= FSMCBase+$20000000;
+
+ FSMCBank4PCCARD	= FSMCBase+$30000000;
+
+type
+ TTimerRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SMCR, res3,
+  DIER, res4,
+  SR, res5,
+  EGR, res,
+  CCMR1, res6,
+  CCMR2, res7,
+  CCER, res8,
+  CNT, res9,
+  PSC, res10,
+  ARR, res11,
+  RCR, res12,
+  CCR1, res13,
+  CCR2, res14,
+  CCR3, res15,
+  CCR4, res16,
+  BDTR, res17,
+  DCR, res18,
+  DMAR, res19: Word;
+ end;
+
+ TRTCRegisters = record
+  CRH, res1,
+  CRL, res2,
+  PRLH, res3,
+  PRLL, res4,
+  DIVH, res5,
+  DIVL, res6,
+  CNTH, res7,
+  CNTL, res8,
+  ALRH, res9,
+  ALRL, res10: Word;
+ end;
+
+ TIWDGRegisters = record
+  KR, res1,
+  PR, res2,
+  RLR, res3,
+  SR, res4: word;
+ end;
+
+ TWWDGRegisters = record
+  CR, res2,
+  CFR, res3,
+  SR, res4: word;
+ end;
+
+ TSPIRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SR, res3,
+  DR, res4,
+  CRCPR, res5,
+  RXCRCR, res6,
+  TXCRCR, res7,
+  I2SCFGR, res8,
+  I2SPR, res9: Word;
+ end;
+
+ TUSARTRegisters = record
+  SR, res1,
+  DR, res2,
+  BRR, res3,
+  CR1, res4,
+  CR2, res5,
+  CR3, res6,
+  GTPR, res7: Word;
+ end;
+
+ TI2CRegisters = record
+  CR1, res1,
+  CR2, res2,
+  OAR1, res3,
+  OAR2, res4,
+  DR, res5,
+  SR1, res6,
+  SR2, res7,
+  CCR, res8: word;
+  TRISE: byte;
+ end;
+
+ TUSBRegisters = record
+  EPR: array[0..7] of longword;
+
+  res: array[0..7] of longword;
+
+  CNTR, res1,
+  ISTR, res2,
+  FNR, res3: Word;
+  DADDR: byte; res4: word; res5: byte;
+  BTABLE: Word;
+ end;
+
+ TUSBMem = packed array[0..511] of byte;
+
+ TCANMailbox = record
+  IR,
+  DTR,
+  DLR,
+  DHR: longword;
+ end;
+
+ TCANRegisters = record
+  MCR,
+  MSR,
+  TSR,
+  RF0R,
+  RF1R,
+  IER,
+  ESR,
+  BTR: longword;
+
+  res5: array[$020..$17F] of byte;
+
+  TX: array[0..2] of TCANMailbox;
+  RX: array[0..2] of TCANMailbox;
+
+  res6: array[$1D0..$1FF] of byte;
+
+  FMR,
+  FM1R,
+  res9: longword;
+  FS1R, res10: word;
+  res11: longword;
+  FFA1R, res12: word;
+  res13: longword;
+  FA1R, res14: word;
+  res15: array[$220..$23F] of byte;
+
+  FOR1,
+  FOR2: longword;
+
+  FB: array[1..13] of array[1..2] of longword;
+ end;
+
+ TBKPRegisters = record
+  DR: array[1..10] of record data, res: word; end;
+
+  RTCCR,
+  CR,
+  CSR,
+  res1,res2: longword;
+
+  DR2: array[11..42] of record data, res: word; end;
+ end;
+
+ TPwrRegisters = record
+  CR, res: word;
+  CSR: Word;
+ end;
+
+ TDACRegisters = record
+  CR,
+  SWTRIGR: longword;
+
+  DHR12R1, res2,
+  DHR12L1, res3,
+  DHR8R1, res4,
+  DHR12R2, res5,
+  DHR12L2, res6,
+  DHR8R2, res7: word;
+
+  DHR12RD,
+  DHR12LD: longword;
+
+  DHR8RD, res8,
+
+  DOR1, res9,
+  DOR2, res10: Word;
+ end;
+
+ TAFIORegisters = record
+  EVCR,
+  MAPR: longword;
+  EXTICR: array[0..3] of longword;
+ end;
+
+ TEXTIRegisters = record
+  IMR,
+  EMR,
+  RTSR,
+  FTSR,
+  SWIER,
+  PR: longword;
+ end;
+
+ TPortRegisters = record
+  CRL,
+  CRH,
+  IDR,
+  ODR,
+  BSRR,
+  BRR,
+  LCKR: longword;
+ end;
+
+ TADCRegisters = record
+  SR,
+  CR1,
+  CR2,
+  SMPR1,
+  SMPR2: longword;
+  JOFR1, res2,
+  JOFR2, res3,
+  JOFR3, res4,
+  JOFR4, res5,
+  HTR, res6,
+  LTR, res7: word;
+  SQR1,
+  SQR2,
+  SQR3,
+  JSQR: longword;
+  JDR1, res8,
+  JDR2, res9,
+  JDR3, res10,
+  JDR4, res11: Word;
+  DR: longword;
+ end;
+
+ TSDIORegisters = record
+  POWER,
+  CLKCR,
+  ARG: longword;
+  CMD, res3,
+  RESPCMD, res4: Word;
+  RESP1,
+  RESP2,
+  RESP3,
+  RESP4,
+  DTIMER,
+  DLEN: longword;
+  DCTRL, res5: word;
+  DCOUNT,
+  STA,
+  ICR,
+  MASK,
+  FIFOCNT,
+  FIFO: longword;
+ end;
+
+ TDMAChannel = record
+  CCR, res1,
+  CNDTR, res2: word;
+  CPAR,
+  CMAR,
+  res: longword;
+ end;
+
+ TDMARegisters = record
+  ISR,
+  IFCR: longword;
+  Channel: array[0..7] of TDMAChannel;
+ end;
+
+ TRCCRegisters = record
+  CR,
+  CFGR,
+  CIR,
+  APB2RSTR,
+  APB1RSTR,
+  AHBENR,
+  APB2ENR,
+  APB1ENR,
+  BDCR,
+  CSR: longword;
+ end;
+
+ TCRCRegisters = record
+  DR: longword;
+  IDR: byte; res1: word; res2: byte;
+  CR: byte;
+ end;
+
+ TFSMCRegisters = record
+  nothingyet: byte;
+ end;
+
+ TFlashRegisters = record
+  ACR,
+  KEYR,
+  OPTKEYR,
+  SR,
+  CR,
+  AR,
+  res,
+  OBR,
+  WRPR: longword;
+ end;
+
+ TNVICRegisters = record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of longword;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  VTOR,                             {!< Vector Table Offset Register                             }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+  SHCSR,                            {!< System Handler Control and State Register                }
+  CFSR,                             {!< Configurable Fault Status Register                       }
+  HFSR,                             {!< Hard Fault Status Register                               }
+  DFSR,                             {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                              }
+  BFAR,                             {!< Bus Fault Address Register                               }
+  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: longword;
+ end;
+
+{$ALIGN 2}
+var
+ { Timers }
+ Timer1: TTimerRegisters 	absolute (APB2Base+$2C00);
+ Timer2: TTimerRegisters 	absolute (APB1Base+$0000);
+ Timer3: TTimerRegisters 	absolute (APB1Base+$0400);
+ Timer4: TTimerRegisters 	absolute (APB1Base+$0800);
+ Timer5: TTimerRegisters 	absolute (APB1Base+$0C00);
+ Timer6: TTimerRegisters 	absolute (APB1Base+$1000);
+ Timer7: TTimerRegisters 	absolute (APB1Base+$1400);
+ Timer8: TTimerRegisters 	absolute (APB2Base+$3400);
+
+ { RTC }
+ RTC: TRTCRegisters 			absolute (APB1Base+$2800);
+
+ { WDG }
+ WWDG: TWWDGRegisters 		absolute (APB1Base+$2C00);
+ IWDG: TIWDGRegisters 		absolute (APB1Base+$3000);
+
+ { SPI }
+ SPI1: TSPIRegisters			absolute (APB2Base+$3000);
+ SPI2: TSPIRegisters			absolute (APB1Base+$3800);
+ SPI3: TSPIRegisters			absolute (APB1Base+$3C00);
+
+ { USART/UART }
+ USART1: TUSARTRegisters	absolute (APB2Base+$3800);
+ USART2: TUSARTRegisters	absolute (APB1Base+$4400);
+ USART3: TUSARTRegisters	absolute (APB1Base+$4800);
+ UART4: TUSARTRegisters		absolute (APB1Base+$4C00);
+ UART5: TUSARTRegisters		absolute (APB1Base+$5000);
+
+ { I2C }
+ I2C1: TI2CRegisters			absolute (APB1Base+$5400);
+ I2C2: TI2CRegisters			absolute (APB1Base+$5800);
+
+ { USB }
+ USB: TUSBRegisters			absolute (APB1Base+$5C00);
+ USBMem: TUSBMem                        absolute (APB1Base+$6000);
+
+ { CAN }
+ CAN: TCANRegisters			absolute (APB1Base+$6800);
+
+ { BKP }
+ BKP: TBKPRegisters			absolute (APB1Base+$6C00);
+
+ { PWR }
+ PWR: TPwrRegisters			absolute (APB1Base+$7000);
+
+ { DAC }
+ DAC: TDACRegisters			absolute (APB1Base+$7400);
+
+ { GPIO }
+ AFIO: TAFIORegisters		absolute (APB2Base+$0);
+ EXTI: TEXTIRegisters		absolute (APB2Base+$0400);
+
+ PortA: TPortRegisters		absolute (APB2Base+$0800);
+ PortB: TPortRegisters		absolute (APB2Base+$0C00);
+ PortC: TPortRegisters		absolute (APB2Base+$1000);
+ PortD: TPortRegisters		absolute (APB2Base+$1400);
+ PortE: TPortRegisters		absolute (APB2Base+$1800);
+ PortF: TPortRegisters		absolute (APB2Base+$1C00);
+ PortG: TPortRegisters		absolute (APB2Base+$2000);
+
+ { ADC }
+ ADC1: TADCRegisters			absolute (APB2Base+$2400);
+ ADC2: TADCRegisters			absolute (APB2Base+$2800);
+ ADC3: TADCRegisters			absolute (APB2Base+$3C00);
+
+ { SDIO }
+ SDIO: TSDIORegisters		absolute (APB2Base+$8000);
+
+ { DMA }
+ DMA1: TDMARegisters			absolute (AHBBase+$0000);
+ DMA2: TDMARegisters			absolute (AHBBase+$0400);
+
+ { RCC }
+ RCC: TRCCRegisters			absolute (AHBBase+$1000);
+
+ { Flash }
+ Flash: TFlashRegisters		absolute (AHBBase+$2000);
+
+ { CRC }
+ CRC: TCRCRegisters			absolute (AHBBase+$3000);
+
+ { SCB }
+ SCB: TSCBRegisters        absolute (SCS_BASE+$0D00);
+
+ { SysTick }
+ SysTick: TSysTickRegisters   absolute (SCS_BASE+$0010);
+
+ { NVIC }
+ NVIC: TNVICRegisters      absolute (SCS_BASE+$0100);
+
+implementation
+
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure Window_Watchdog_interrupt; external name 'Window_Watchdog_interrupt';
+procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
+procedure Tamper_interrupt; external name 'Tamper_interrupt';
+procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
+procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
+procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
+procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
+procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
+procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
+procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
+procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
+procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
+procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
+procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
+procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
+procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
+procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
+procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
+procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
+procedure CAN1_TX_interrupts; external name 'CAN1_TX_interrupts';
+procedure CAN1_RX0_interrupts; external name 'CAN1_RX0_interrupts';
+procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt';
+procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt';
+procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
+procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
+procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
+procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
+procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
+procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
+procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
+procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
+procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
+procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
+procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
+procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
+procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
+procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
+procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
+procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
+procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
+procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
+procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
+procedure USB_OTG_FS_Wakeup_through_EXTI_line_interrupt; external name 'USB_OTG_FS_Wakeup_through_EXTI_line_interrupt';
+procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
+procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
+procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
+procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
+procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
+procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
+procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
+procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
+procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
+procedure DMA2_Channel4_global_interrupt; external name 'DMA2_Channel4_global_interrupt';
+procedure DMA2_Channel5_global_interrupt; external name 'DMA2_Channel5_global_interrupt';
+procedure Ethernet_global_interrupt; external name 'Ethernet_global_interrupt';
+procedure Ethernet_Wakeup_through_EXTI_line_interrupt; external name 'Ethernet_Wakeup_through_EXTI_line_interrupt';
+procedure CAN2_TX_interrupts; external name 'CAN2_TX_interrupts';
+procedure CAN2_RX0_interrupts; external name 'CAN2_RX0_interrupts';
+procedure CAN2_RX1_interrupt; external name 'CAN2_RX1_interrupt';
+procedure CAN2_SCE_interrupt; external name 'CAN2_SCE_interrupt';
+procedure USB_On_The_Go_FS_global_interrupt; external name 'USB_On_The_Go_FS_global_interrupt';
+
+{$i cortexm3_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+   .section ".init.interrupt_vectors"
+interrupt_vectors:
+   .long _stack_top
+   .long Startup
+   .long NMI_interrupt
+   .long Hardfault_interrupt
+   .long MemManage_interrupt
+   .long BusFault_interrupt
+   .long UsageFault_interrupt
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long SWI_interrupt
+   .long DebugMonitor_interrupt
+   .long 0
+   .long PendingSV_interrupt
+   .long SysTick_interrupt
+   
+   .long Window_Watchdog_interrupt
+   .long PVD_through_EXTI_Line_detection_interrupt
+   .long Tamper_interrupt
+   .long RTC_global_interrupt
+   .long Flash_global_interrupt
+   .long RCC_global_interrupt
+   .long EXTI_Line0_interrupt
+   .long EXTI_Line1_interrupt
+   .long EXTI_Line2_interrupt
+   .long EXTI_Line3_interrupt
+   .long EXTI_Line4_interrupt
+   .long DMA1_Channel1_global_interrupt
+   .long DMA1_Channel2_global_interrupt
+   .long DMA1_Channel3_global_interrupt
+   .long DMA1_Channel4_global_interrupt
+   .long DMA1_Channel5_global_interrupt
+   .long DMA1_Channel6_global_interrupt
+   .long DMA1_Channel7_global_interrupt
+   .long ADC1_and_ADC2_global_interrupt
+   .long CAN1_TX_interrupts
+   .long CAN1_RX0_interrupts
+   .long CAN1_RX1_interrupt
+   .long CAN1_SCE_interrupt
+   .long EXTI_Line9_5_interrupts
+   .long TIM1_Break_interrupt
+   .long TIM1_Update_interrupt
+   .long TIM1_Trigger_and_Commutation_interrupts
+   .long TIM1_Capture_Compare_interrupt
+   .long TIM2_global_interrupt
+   .long TIM3_global_interrupt
+   .long TIM4_global_interrupt
+   .long I2C1_event_interrupt
+   .long I2C1_error_interrupt
+   .long I2C2_event_interrupt
+   .long I2C2_error_interrupt
+   .long SPI1_global_interrupt
+   .long SPI2_global_interrupt
+   .long USART1_global_interrupt
+   .long USART2_global_interrupt
+   .long USART3_global_interrupt
+   .long EXTI_Line15_10_interrupts
+   .long RTC_alarm_through_EXTI_line_interrupt
+   .long USB_OTG_FS_Wakeup_through_EXTI_line_interrupt
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long TIM5_global_interrupt
+   .long SPI3_global_interrupt
+   .long UART4_global_interrupt
+   .long UART5_global_interrupt
+   .long TIM6_global_interrupt
+   .long TIM7_global_interrupt
+   .long DMA2_Channel1_global_interrupt
+   .long DMA2_Channel2_global_interrupt
+   .long DMA2_Channel3_global_interrupt
+   .long DMA2_Channel4_global_interrupt
+   .long DMA2_Channel5_global_interrupt
+   .long Ethernet_global_interrupt
+   .long Ethernet_Wakeup_through_EXTI_line_interrupt
+   .long CAN2_TX_interrupts
+   .long CAN2_RX0_interrupts
+   .long CAN2_RX1_interrupt
+   .long CAN2_SCE_interrupt
+   .long USB_On_The_Go_FS_global_interrupt
+   
+   .weak NMI_interrupt
+   .weak Hardfault_interrupt
+   .weak MemManage_interrupt
+   .weak BusFault_interrupt
+   .weak UsageFault_interrupt
+   .weak SWI_interrupt
+   .weak DebugMonitor_interrupt
+   .weak PendingSV_interrupt
+   .weak SysTick_interrupt
+   
+   .weak Window_Watchdog_interrupt
+   .weak PVD_through_EXTI_Line_detection_interrupt
+   .weak Tamper_interrupt
+   .weak RTC_global_interrupt
+   .weak Flash_global_interrupt
+   .weak RCC_global_interrupt
+   .weak EXTI_Line0_interrupt
+   .weak EXTI_Line1_interrupt
+   .weak EXTI_Line2_interrupt
+   .weak EXTI_Line3_interrupt
+   .weak EXTI_Line4_interrupt
+   .weak DMA1_Channel1_global_interrupt
+   .weak DMA1_Channel2_global_interrupt
+   .weak DMA1_Channel3_global_interrupt
+   .weak DMA1_Channel4_global_interrupt
+   .weak DMA1_Channel5_global_interrupt
+   .weak DMA1_Channel6_global_interrupt
+   .weak DMA1_Channel7_global_interrupt
+   .weak ADC1_and_ADC2_global_interrupt
+   .weak CAN1_TX_interrupts
+   .weak CAN1_RX0_interrupts
+   .weak CAN1_RX1_interrupt
+   .weak CAN1_SCE_interrupt
+   .weak EXTI_Line9_5_interrupts
+   .weak TIM1_Break_interrupt
+   .weak TIM1_Update_interrupt
+   .weak TIM1_Trigger_and_Commutation_interrupts
+   .weak TIM1_Capture_Compare_interrupt
+   .weak TIM2_global_interrupt
+   .weak TIM3_global_interrupt
+   .weak TIM4_global_interrupt
+   .weak I2C1_event_interrupt
+   .weak I2C1_error_interrupt
+   .weak I2C2_event_interrupt
+   .weak I2C2_error_interrupt
+   .weak SPI1_global_interrupt
+   .weak SPI2_global_interrupt
+   .weak USART1_global_interrupt
+   .weak USART2_global_interrupt
+   .weak USART3_global_interrupt
+   .weak EXTI_Line15_10_interrupts
+   .weak RTC_alarm_through_EXTI_line_interrupt
+   .weak USB_OTG_FS_Wakeup_through_EXTI_line_interrupt
+   .weak TIM5_global_interrupt
+   .weak SPI3_global_interrupt
+   .weak UART4_global_interrupt
+   .weak UART5_global_interrupt
+   .weak TIM6_global_interrupt
+   .weak TIM7_global_interrupt
+   .weak DMA2_Channel1_global_interrupt
+   .weak DMA2_Channel2_global_interrupt
+   .weak DMA2_Channel3_global_interrupt
+   .weak DMA2_Channel4_global_interrupt
+   .weak DMA2_Channel5_global_interrupt
+   .weak Ethernet_global_interrupt
+   .weak Ethernet_Wakeup_through_EXTI_line_interrupt
+   .weak CAN2_TX_interrupts
+   .weak CAN2_RX0_interrupts
+   .weak CAN2_RX1_interrupt
+   .weak CAN2_SCE_interrupt
+   .weak USB_On_The_Go_FS_global_interrupt
+
+   
+   .set NMI_interrupt, Startup
+   .set Hardfault_interrupt, Startup
+   .set MemManage_interrupt, Startup
+   .set BusFault_interrupt, Startup
+   .set UsageFault_interrupt, Startup
+   .set SWI_interrupt, Startup
+   .set DebugMonitor_interrupt, Startup
+   .set PendingSV_interrupt, Startup
+   .set SysTick_interrupt, Startup
+
+   .set Window_Watchdog_interrupt, Startup
+   .set PVD_through_EXTI_Line_detection_interrupt, Startup
+   .set Tamper_interrupt, Startup
+   .set RTC_global_interrupt, Startup
+   .set Flash_global_interrupt, Startup
+   .set RCC_global_interrupt, Startup
+   .set EXTI_Line0_interrupt, Startup
+   .set EXTI_Line1_interrupt, Startup
+   .set EXTI_Line2_interrupt, Startup
+   .set EXTI_Line3_interrupt, Startup
+   .set EXTI_Line4_interrupt, Startup
+   .set DMA1_Channel1_global_interrupt, Startup
+   .set DMA1_Channel2_global_interrupt, Startup
+   .set DMA1_Channel3_global_interrupt, Startup
+   .set DMA1_Channel4_global_interrupt, Startup
+   .set DMA1_Channel5_global_interrupt, Startup
+   .set DMA1_Channel6_global_interrupt, Startup
+   .set DMA1_Channel7_global_interrupt, Startup
+   .set ADC1_and_ADC2_global_interrupt, Startup
+   .set CAN1_TX_interrupts, Startup
+   .set CAN1_RX0_interrupts, Startup
+   .set CAN1_RX1_interrupt, Startup
+   .set CAN1_SCE_interrupt, Startup
+   .set EXTI_Line9_5_interrupts, Startup
+   .set TIM1_Break_interrupt, Startup
+   .set TIM1_Update_interrupt, Startup
+   .set TIM1_Trigger_and_Commutation_interrupts, Startup
+   .set TIM1_Capture_Compare_interrupt, Startup
+   .set TIM2_global_interrupt, Startup
+   .set TIM3_global_interrupt, Startup
+   .set TIM4_global_interrupt, Startup
+   .set I2C1_event_interrupt, Startup
+   .set I2C1_error_interrupt, Startup
+   .set I2C2_event_interrupt, Startup
+   .set I2C2_error_interrupt, Startup
+   .set SPI1_global_interrupt, Startup
+   .set SPI2_global_interrupt, Startup
+   .set USART1_global_interrupt, Startup
+   .set USART2_global_interrupt, Startup
+   .set USART3_global_interrupt, Startup
+   .set EXTI_Line15_10_interrupts, Startup
+   .set RTC_alarm_through_EXTI_line_interrupt, Startup
+   .set USB_OTG_FS_Wakeup_through_EXTI_line_interrupt, Startup
+   .set TIM5_global_interrupt, Startup
+   .set SPI3_global_interrupt, Startup
+   .set UART4_global_interrupt, Startup
+   .set UART5_global_interrupt, Startup
+   .set TIM6_global_interrupt, Startup
+   .set TIM7_global_interrupt, Startup
+   .set DMA2_Channel1_global_interrupt, Startup
+   .set DMA2_Channel2_global_interrupt, Startup
+   .set DMA2_Channel3_global_interrupt, Startup
+   .set DMA2_Channel4_global_interrupt, Startup
+   .set DMA2_Channel5_global_interrupt, Startup
+   .set Ethernet_global_interrupt, Startup
+   .set Ethernet_Wakeup_through_EXTI_line_interrupt, Startup
+   .set CAN2_TX_interrupts, Startup
+   .set CAN2_RX0_interrupts, Startup
+   .set CAN2_RX1_interrupt, Startup
+   .set CAN2_SCE_interrupt, Startup
+   .set USB_On_The_Go_FS_global_interrupt, Startup
+   
+   .text
+end;
+
+end.

rtl/embedded/arm/stm32f10x_hd.pp

@@ -0,0 +1,777 @@
+{
+Register definitions and utility code for STM32F10x - HD density
+
+Created by Jeppe Johansen 2012 - [email protected]
+}
+unit stm32f10x_hd;
+
+{$goto on}
+{$define stm32f10x_hd}
+
+interface
+
+type
+ TBitvector32 = bitpacked array[0..31] of 0..1;
+
+{$PACKRECORDS 2}
+const
+ PeripheralBase 	= $40000000;
+
+ FSMCBase			= $60000000;
+
+ APB1Base 			= PeripheralBase;
+ APB2Base 			= PeripheralBase+$10000;
+ AHBBase 			= PeripheralBase+$20000;
+
+ SCS_BASE         = $E000E000;
+
+ { FSMC }
+ FSMCBank1NOR1		= FSMCBase+$00000000;
+ FSMCBank1NOR2		= FSMCBase+$04000000;
+ FSMCBank1NOR3		= FSMCBase+$08000000;
+ FSMCBank1NOR4		= FSMCBase+$0C000000;
+
+ FSMCBank1PSRAM1	= FSMCBase+$00000000;
+ FSMCBank1PSRAM2	= FSMCBase+$04000000;
+ FSMCBank1PSRAM3	= FSMCBase+$08000000;
+ FSMCBank1PSRAM4	= FSMCBase+$0C000000;
+
+ FSMCBank2NAND1	= FSMCBase+$10000000;
+ FSMCBank3NAND2	= FSMCBase+$20000000;
+
+ FSMCBank4PCCARD	= FSMCBase+$30000000;
+
+type
+ TTimerRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SMCR, res3,
+  DIER, res4,
+  SR, res5,
+  EGR, res,
+  CCMR1, res6,
+  CCMR2, res7,
+  CCER, res8,
+  CNT, res9,
+  PSC, res10,
+  ARR, res11,
+  RCR, res12,
+  CCR1, res13,
+  CCR2, res14,
+  CCR3, res15,
+  CCR4, res16,
+  BDTR, res17,
+  DCR, res18,
+  DMAR, res19: Word;
+ end;
+
+ TRTCRegisters = record
+  CRH, res1,
+  CRL, res2,
+  PRLH, res3,
+  PRLL, res4,
+  DIVH, res5,
+  DIVL, res6,
+  CNTH, res7,
+  CNTL, res8,
+  ALRH, res9,
+  ALRL, res10: Word;
+ end;
+
+ TIWDGRegisters = record
+  KR, res1,
+  PR, res2,
+  RLR, res3,
+  SR, res4: word;
+ end;
+
+ TWWDGRegisters = record
+  CR, res2,
+  CFR, res3,
+  SR, res4: word;
+ end;
+
+ TSPIRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SR, res3,
+  DR, res4,
+  CRCPR, res5,
+  RXCRCR, res6,
+  TXCRCR, res7,
+  I2SCFGR, res8,
+  I2SPR, res9: Word;
+ end;
+
+ TUSARTRegisters = record
+  SR, res1,
+  DR, res2,
+  BRR, res3,
+  CR1, res4,
+  CR2, res5,
+  CR3, res6,
+  GTPR, res7: Word;
+ end;
+
+ TI2CRegisters = record
+  CR1, res1,
+  CR2, res2,
+  OAR1, res3,
+  OAR2, res4,
+  DR, res5,
+  SR1, res6,
+  SR2, res7,
+  CCR, res8: word;
+  TRISE: byte;
+ end;
+
+ TUSBRegisters = record
+  EPR: array[0..7] of longword;
+
+  res: array[0..7] of longword;
+
+  CNTR, res1,
+  ISTR, res2,
+  FNR, res3: Word;
+  DADDR: byte; res4: word; res5: byte;
+  BTABLE: Word;
+ end;
+
+ TUSBMem = packed array[0..511] of byte;
+
+ TCANMailbox = record
+  IR,
+  DTR,
+  DLR,
+  DHR: longword;
+ end;
+
+ TCANRegisters = record
+  MCR,
+  MSR,
+  TSR,
+  RF0R,
+  RF1R,
+  IER,
+  ESR,
+  BTR: longword;
+
+  res5: array[$020..$17F] of byte;
+
+  TX: array[0..2] of TCANMailbox;
+  RX: array[0..2] of TCANMailbox;
+
+  res6: array[$1D0..$1FF] of byte;
+
+  FMR,
+  FM1R,
+  res9: longword;
+  FS1R, res10: word;
+  res11: longword;
+  FFA1R, res12: word;
+  res13: longword;
+  FA1R, res14: word;
+  res15: array[$220..$23F] of byte;
+
+  FOR1,
+  FOR2: longword;
+
+  FB: array[1..13] of array[1..2] of longword;
+ end;
+
+ TBKPRegisters = record
+  DR: array[1..10] of record data, res: word; end;
+
+  RTCCR,
+  CR,
+  CSR,
+  res1,res2: longword;
+
+  DR2: array[11..42] of record data, res: word; end;
+ end;
+
+ TPwrRegisters = record
+  CR, res: word;
+  CSR: Word;
+ end;
+
+ TDACRegisters = record
+  CR,
+  SWTRIGR: longword;
+
+  DHR12R1, res2,
+  DHR12L1, res3,
+  DHR8R1, res4,
+  DHR12R2, res5,
+  DHR12L2, res6,
+  DHR8R2, res7: word;
+
+  DHR12RD,
+  DHR12LD: longword;
+
+  DHR8RD, res8,
+
+  DOR1, res9,
+  DOR2, res10: Word;
+ end;
+
+ TAFIORegisters = record
+  EVCR,
+  MAPR: longword;
+  EXTICR: array[0..3] of longword;
+ end;
+
+ TEXTIRegisters = record
+  IMR,
+  EMR,
+  RTSR,
+  FTSR,
+  SWIER,
+  PR: longword;
+ end;
+
+ TPortRegisters = record
+  CRL,
+  CRH,
+  IDR,
+  ODR,
+  BSRR,
+  BRR,
+  LCKR: longword;
+ end;
+
+ TADCRegisters = record
+  SR,
+  CR1,
+  CR2,
+  SMPR1,
+  SMPR2: longword;
+  JOFR1, res2,
+  JOFR2, res3,
+  JOFR3, res4,
+  JOFR4, res5,
+  HTR, res6,
+  LTR, res7: word;
+  SQR1,
+  SQR2,
+  SQR3,
+  JSQR: longword;
+  JDR1, res8,
+  JDR2, res9,
+  JDR3, res10,
+  JDR4, res11: Word;
+  DR: longword;
+ end;
+
+ TSDIORegisters = record
+  POWER,
+  CLKCR,
+  ARG: longword;
+  CMD, res3,
+  RESPCMD, res4: Word;
+  RESP1,
+  RESP2,
+  RESP3,
+  RESP4,
+  DTIMER,
+  DLEN: longword;
+  DCTRL, res5: word;
+  DCOUNT,
+  STA,
+  ICR,
+  MASK,
+  FIFOCNT,
+  FIFO: longword;
+ end;
+
+ TDMAChannel = record
+  CCR, res1,
+  CNDTR, res2: word;
+  CPAR,
+  CMAR,
+  res: longword;
+ end;
+
+ TDMARegisters = record
+  ISR,
+  IFCR: longword;
+  Channel: array[0..7] of TDMAChannel;
+ end;
+
+ TRCCRegisters = record
+  CR,
+  CFGR,
+  CIR,
+  APB2RSTR,
+  APB1RSTR,
+  AHBENR,
+  APB2ENR,
+  APB1ENR,
+  BDCR,
+  CSR: longword;
+ end;
+
+ TCRCRegisters = record
+  DR: longword;
+  IDR: byte; res1: word; res2: byte;
+  CR: byte;
+ end;
+
+ TFSMCRegisters = record
+  nothingyet: byte;
+ end;
+
+ TFlashRegisters = record
+  ACR,
+  KEYR,
+  OPTKEYR,
+  SR,
+  CR,
+  AR,
+  res,
+  OBR,
+  WRPR: longword;
+ end;
+
+ TNVICRegisters = record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of longword;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  VTOR,                             {!< Vector Table Offset Register                             }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+  SHCSR,                            {!< System Handler Control and State Register                }
+  CFSR,                             {!< Configurable Fault Status Register                       }
+  HFSR,                             {!< Hard Fault Status Register                               }
+  DFSR,                             {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                              }
+  BFAR,                             {!< Bus Fault Address Register                               }
+  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: longword;
+ end;
+
+{$ALIGN 2}
+var
+ { Timers }
+ Timer1: TTimerRegisters 	absolute (APB2Base+$2C00);
+ Timer2: TTimerRegisters 	absolute (APB1Base+$0000);
+ Timer3: TTimerRegisters 	absolute (APB1Base+$0400);
+ Timer4: TTimerRegisters 	absolute (APB1Base+$0800);
+ Timer5: TTimerRegisters 	absolute (APB1Base+$0C00);
+ Timer6: TTimerRegisters 	absolute (APB1Base+$1000);
+ Timer7: TTimerRegisters 	absolute (APB1Base+$1400);
+ Timer8: TTimerRegisters 	absolute (APB2Base+$3400);
+
+ { RTC }
+ RTC: TRTCRegisters 			absolute (APB1Base+$2800);
+
+ { WDG }
+ WWDG: TWWDGRegisters 		absolute (APB1Base+$2C00);
+ IWDG: TIWDGRegisters 		absolute (APB1Base+$3000);
+
+ { SPI }
+ SPI1: TSPIRegisters			absolute (APB2Base+$3000);
+ SPI2: TSPIRegisters			absolute (APB1Base+$3800);
+ SPI3: TSPIRegisters			absolute (APB1Base+$3C00);
+
+ { USART/UART }
+ USART1: TUSARTRegisters	absolute (APB2Base+$3800);
+ USART2: TUSARTRegisters	absolute (APB1Base+$4400);
+ USART3: TUSARTRegisters	absolute (APB1Base+$4800);
+ UART4: TUSARTRegisters		absolute (APB1Base+$4C00);
+ UART5: TUSARTRegisters		absolute (APB1Base+$5000);
+
+ { I2C }
+ I2C1: TI2CRegisters			absolute (APB1Base+$5400);
+ I2C2: TI2CRegisters			absolute (APB1Base+$5800);
+
+ { USB }
+ USB: TUSBRegisters			absolute (APB1Base+$5C00);
+ USBMem: TUSBMem                        absolute (APB1Base+$6000);
+
+ { CAN }
+ CAN: TCANRegisters			absolute (APB1Base+$6800);
+
+ { BKP }
+ BKP: TBKPRegisters			absolute (APB1Base+$6C00);
+
+ { PWR }
+ PWR: TPwrRegisters			absolute (APB1Base+$7000);
+
+ { DAC }
+ DAC: TDACRegisters			absolute (APB1Base+$7400);
+
+ { GPIO }
+ AFIO: TAFIORegisters		absolute (APB2Base+$0);
+ EXTI: TEXTIRegisters		absolute (APB2Base+$0400);
+
+ PortA: TPortRegisters		absolute (APB2Base+$0800);
+ PortB: TPortRegisters		absolute (APB2Base+$0C00);
+ PortC: TPortRegisters		absolute (APB2Base+$1000);
+ PortD: TPortRegisters		absolute (APB2Base+$1400);
+ PortE: TPortRegisters		absolute (APB2Base+$1800);
+ PortF: TPortRegisters		absolute (APB2Base+$1C00);
+ PortG: TPortRegisters		absolute (APB2Base+$2000);
+
+ { ADC }
+ ADC1: TADCRegisters			absolute (APB2Base+$2400);
+ ADC2: TADCRegisters			absolute (APB2Base+$2800);
+ ADC3: TADCRegisters			absolute (APB2Base+$3C00);
+
+ { SDIO }
+ SDIO: TSDIORegisters		absolute (APB2Base+$8000);
+
+ { DMA }
+ DMA1: TDMARegisters			absolute (AHBBase+$0000);
+ DMA2: TDMARegisters			absolute (AHBBase+$0400);
+
+ { RCC }
+ RCC: TRCCRegisters			absolute (AHBBase+$1000);
+
+ { Flash }
+ Flash: TFlashRegisters		absolute (AHBBase+$2000);
+
+ { CRC }
+ CRC: TCRCRegisters			absolute (AHBBase+$3000);
+
+ { SCB }
+ SCB: TSCBRegisters        absolute (SCS_BASE+$0D00);
+
+ { SysTick }
+ SysTick: TSysTickRegisters   absolute (SCS_BASE+$0010);
+
+ { NVIC }
+ NVIC: TNVICRegisters      absolute (SCS_BASE+$0100);
+
+implementation
+
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
+procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
+procedure Tamper_interrupt; external name 'Tamper_interrupt';
+procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
+procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
+procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
+procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
+procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
+procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
+procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
+procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
+procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
+procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
+procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
+procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
+procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
+procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
+procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
+procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
+procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
+procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
+procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
+procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
+procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
+procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
+procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
+procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
+procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
+procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
+procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
+procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
+procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
+procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
+procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
+procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
+procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
+procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
+procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
+procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
+procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
+procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
+procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
+procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
+procedure TIM8_Break_interrupt; external name 'TIM8_Break_interrupt';
+procedure TIM8_Update_interrupt; external name 'TIM8_Update_interrupt';
+procedure TIM8_Trigger_and_Commutation_interrupts; external name 'TIM8_Trigger_and_Commutation_interrupts';
+procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
+procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
+procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
+procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
+procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
+procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
+procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
+procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
+procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
+procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
+procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
+procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
+procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
+procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
+
+{$i cortexm3_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+   .section ".init.interrupt_vectors"
+interrupt_vectors:
+   .long _stack_top
+   .long Startup
+   .long NMI_interrupt
+   .long Hardfault_interrupt
+   .long MemManage_interrupt
+   .long BusFault_interrupt
+   .long UsageFault_interrupt
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long SWI_interrupt
+   .long DebugMonitor_interrupt
+   .long 0
+   .long PendingSV_interrupt
+   .long SysTick_interrupt
+   
+   .long Window_watchdog_interrupt
+   .long PVD_through_EXTI_Line_detection_interrupt
+   .long Tamper_interrupt
+   .long RTC_global_interrupt
+   .long Flash_global_interrupt
+   .long RCC_global_interrupt
+   .long EXTI_Line0_interrupt
+   .long EXTI_Line1_interrupt
+   .long EXTI_Line2_interrupt
+   .long EXTI_Line3_interrupt
+   .long EXTI_Line4_interrupt
+   .long DMA1_Channel1_global_interrupt
+   .long DMA1_Channel2_global_interrupt
+   .long DMA1_Channel3_global_interrupt
+   .long DMA1_Channel4_global_interrupt
+   .long DMA1_Channel5_global_interrupt
+   .long DMA1_Channel6_global_interrupt
+   .long DMA1_Channel7_global_interrupt
+   .long ADC1_and_ADC2_global_interrupt
+   .long USB_High_Priority_or_CAN_TX_interrupts
+   .long USB_Low_Priority_or_CAN_RX0_interrupts
+   .long CAN_RX1_interrupt
+   .long CAN_SCE_interrupt
+   .long EXTI_Line9_5_interrupts
+   .long TIM1_Break_interrupt
+   .long TIM1_Update_interrupt
+   .long TIM1_Trigger_and_Commutation_interrupts
+   .long TIM1_Capture_Compare_interrupt
+   .long TIM2_global_interrupt
+   .long TIM3_global_interrupt
+   .long TIM4_global_interrupt
+   .long I2C1_event_interrupt
+   .long I2C1_error_interrupt
+   .long I2C2_event_interrupt
+   .long I2C2_error_interrupt
+   .long SPI1_global_interrupt
+   .long SPI2_global_interrupt
+   .long USART1_global_interrupt
+   .long USART2_global_interrupt
+   .long USART3_global_interrupt
+   .long EXTI_Line15_10_interrupts
+   .long RTC_alarm_through_EXTI_line_interrupt
+   .long USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .long TIM8_Break_interrupt
+   .long TIM8_Update_interrupt
+   .long TIM8_Trigger_and_Commutation_interrupts
+   .long TIM8_Capture_Compare_interrupt
+   .long ADC3_global_interrupt
+   .long FSMC_global_interrupt
+   .long SDIO_global_interrupt
+   .long TIM5_global_interrupt
+   .long SPI3_global_interrupt
+   .long UART4_global_interrupt
+   .long UART5_global_interrupt
+   .long TIM6_global_interrupt
+   .long TIM7_global_interrupt
+   .long DMA2_Channel1_global_interrupt
+   .long DMA2_Channel2_global_interrupt
+   .long DMA2_Channel3_global_interrupt
+   .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+   
+   .weak NMI_interrupt
+   .weak Hardfault_interrupt
+   .weak MemManage_interrupt
+   .weak BusFault_interrupt
+   .weak UsageFault_interrupt
+   .weak SWI_interrupt
+   .weak DebugMonitor_interrupt
+   .weak PendingSV_interrupt
+   .weak SysTick_interrupt
+   
+   .weak Window_watchdog_interrupt
+   .weak PVD_through_EXTI_Line_detection_interrupt
+   .weak Tamper_interrupt
+   .weak RTC_global_interrupt
+   .weak Flash_global_interrupt
+   .weak RCC_global_interrupt
+   .weak EXTI_Line0_interrupt
+   .weak EXTI_Line1_interrupt
+   .weak EXTI_Line2_interrupt
+   .weak EXTI_Line3_interrupt
+   .weak EXTI_Line4_interrupt
+   .weak DMA1_Channel1_global_interrupt
+   .weak DMA1_Channel2_global_interrupt
+   .weak DMA1_Channel3_global_interrupt
+   .weak DMA1_Channel4_global_interrupt
+   .weak DMA1_Channel5_global_interrupt
+   .weak DMA1_Channel6_global_interrupt
+   .weak DMA1_Channel7_global_interrupt
+   .weak ADC1_and_ADC2_global_interrupt
+   .weak USB_High_Priority_or_CAN_TX_interrupts
+   .weak USB_Low_Priority_or_CAN_RX0_interrupts
+   .weak CAN_RX1_interrupt
+   .weak CAN_SCE_interrupt
+   .weak EXTI_Line9_5_interrupts
+   .weak TIM1_Break_interrupt
+   .weak TIM1_Update_interrupt
+   .weak TIM1_Trigger_and_Commutation_interrupts
+   .weak TIM1_Capture_Compare_interrupt
+   .weak TIM2_global_interrupt
+   .weak TIM3_global_interrupt
+   .weak TIM4_global_interrupt
+   .weak I2C1_event_interrupt
+   .weak I2C1_error_interrupt
+   .weak I2C2_event_interrupt
+   .weak I2C2_error_interrupt
+   .weak SPI1_global_interrupt
+   .weak SPI2_global_interrupt
+   .weak USART1_global_interrupt
+   .weak USART2_global_interrupt
+   .weak USART3_global_interrupt
+   .weak EXTI_Line15_10_interrupts
+   .weak RTC_alarm_through_EXTI_line_interrupt
+   .weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .weak TIM8_Break_interrupt
+   .weak TIM8_Update_interrupt
+   .weak TIM8_Trigger_and_Commutation_interrupts
+   .weak TIM8_Capture_Compare_interrupt
+   .weak ADC3_global_interrupt
+   .weak FSMC_global_interrupt
+   .weak SDIO_global_interrupt
+   .weak TIM5_global_interrupt
+   .weak SPI3_global_interrupt
+   .weak UART4_global_interrupt
+   .weak UART5_global_interrupt
+   .weak TIM6_global_interrupt
+   .weak TIM7_global_interrupt
+   .weak DMA2_Channel1_global_interrupt
+   .weak DMA2_Channel2_global_interrupt
+   .weak DMA2_Channel3_global_interrupt
+   .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+
+   
+   .set NMI_interrupt, Startup
+   .set Hardfault_interrupt, Startup
+   .set MemManage_interrupt, Startup
+   .set BusFault_interrupt, Startup
+   .set UsageFault_interrupt, Startup
+   .set SWI_interrupt, Startup
+   .set DebugMonitor_interrupt, Startup
+   .set PendingSV_interrupt, Startup
+   .set SysTick_interrupt, Startup
+
+   .set Window_watchdog_interrupt, Startup
+   .set PVD_through_EXTI_Line_detection_interrupt, Startup
+   .set Tamper_interrupt, Startup
+   .set RTC_global_interrupt, Startup
+   .set Flash_global_interrupt, Startup
+   .set RCC_global_interrupt, Startup
+   .set EXTI_Line0_interrupt, Startup
+   .set EXTI_Line1_interrupt, Startup
+   .set EXTI_Line2_interrupt, Startup
+   .set EXTI_Line3_interrupt, Startup
+   .set EXTI_Line4_interrupt, Startup
+   .set DMA1_Channel1_global_interrupt, Startup
+   .set DMA1_Channel2_global_interrupt, Startup
+   .set DMA1_Channel3_global_interrupt, Startup
+   .set DMA1_Channel4_global_interrupt, Startup
+   .set DMA1_Channel5_global_interrupt, Startup
+   .set DMA1_Channel6_global_interrupt, Startup
+   .set DMA1_Channel7_global_interrupt, Startup
+   .set ADC1_and_ADC2_global_interrupt, Startup
+   .set USB_High_Priority_or_CAN_TX_interrupts, Startup
+   .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
+   .set CAN_RX1_interrupt, Startup
+   .set CAN_SCE_interrupt, Startup
+   .set EXTI_Line9_5_interrupts, Startup
+   .set TIM1_Break_interrupt, Startup
+   .set TIM1_Update_interrupt, Startup
+   .set TIM1_Trigger_and_Commutation_interrupts, Startup
+   .set TIM1_Capture_Compare_interrupt, Startup
+   .set TIM2_global_interrupt, Startup
+   .set TIM3_global_interrupt, Startup
+   .set TIM4_global_interrupt, Startup
+   .set I2C1_event_interrupt, Startup
+   .set I2C1_error_interrupt, Startup
+   .set I2C2_event_interrupt, Startup
+   .set I2C2_error_interrupt, Startup
+   .set SPI1_global_interrupt, Startup
+   .set SPI2_global_interrupt, Startup
+   .set USART1_global_interrupt, Startup
+   .set USART2_global_interrupt, Startup
+   .set USART3_global_interrupt, Startup
+   .set EXTI_Line15_10_interrupts, Startup
+   .set RTC_alarm_through_EXTI_line_interrupt, Startup
+   .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
+   .set TIM8_Break_interrupt, Startup
+   .set TIM8_Update_interrupt, Startup
+   .set TIM8_Trigger_and_Commutation_interrupts, Startup
+   .set TIM8_Capture_Compare_interrupt, Startup
+   .set ADC3_global_interrupt, Startup
+   .set FSMC_global_interrupt, Startup
+   .set SDIO_global_interrupt, Startup
+   .set TIM5_global_interrupt, Startup
+   .set SPI3_global_interrupt, Startup
+   .set UART4_global_interrupt, Startup
+   .set UART5_global_interrupt, Startup
+   .set TIM6_global_interrupt, Startup
+   .set TIM7_global_interrupt, Startup
+   .set DMA2_Channel1_global_interrupt, Startup
+   .set DMA2_Channel2_global_interrupt, Startup
+   .set DMA2_Channel3_global_interrupt, Startup
+   .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
+   
+   .text
+end;
+
+end.

rtl/embedded/arm/stm32f10x_ld.pp

@@ -0,0 +1,777 @@
+{
+Register definitions and utility code for STM32F10x - Low Density
+
+Created by Jeppe Johansen 2012 - [email protected]
+}
+unit stm32f10x_ld;
+
+{$goto on}
+{$define stm32f10x_ld}
+
+interface
+
+type
+ TBitvector32 = bitpacked array[0..31] of 0..1;
+
+{$PACKRECORDS 2}
+const
+ PeripheralBase 	= $40000000;
+
+ FSMCBase			= $60000000;
+
+ APB1Base 			= PeripheralBase;
+ APB2Base 			= PeripheralBase+$10000;
+ AHBBase 			= PeripheralBase+$20000;
+
+ SCS_BASE         = $E000E000;
+
+ { FSMC }
+ FSMCBank1NOR1		= FSMCBase+$00000000;
+ FSMCBank1NOR2		= FSMCBase+$04000000;
+ FSMCBank1NOR3		= FSMCBase+$08000000;
+ FSMCBank1NOR4		= FSMCBase+$0C000000;
+
+ FSMCBank1PSRAM1	= FSMCBase+$00000000;
+ FSMCBank1PSRAM2	= FSMCBase+$04000000;
+ FSMCBank1PSRAM3	= FSMCBase+$08000000;
+ FSMCBank1PSRAM4	= FSMCBase+$0C000000;
+
+ FSMCBank2NAND1	= FSMCBase+$10000000;
+ FSMCBank3NAND2	= FSMCBase+$20000000;
+
+ FSMCBank4PCCARD	= FSMCBase+$30000000;
+
+type
+ TTimerRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SMCR, res3,
+  DIER, res4,
+  SR, res5,
+  EGR, res,
+  CCMR1, res6,
+  CCMR2, res7,
+  CCER, res8,
+  CNT, res9,
+  PSC, res10,
+  ARR, res11,
+  RCR, res12,
+  CCR1, res13,
+  CCR2, res14,
+  CCR3, res15,
+  CCR4, res16,
+  BDTR, res17,
+  DCR, res18,
+  DMAR, res19: Word;
+ end;
+
+ TRTCRegisters = record
+  CRH, res1,
+  CRL, res2,
+  PRLH, res3,
+  PRLL, res4,
+  DIVH, res5,
+  DIVL, res6,
+  CNTH, res7,
+  CNTL, res8,
+  ALRH, res9,
+  ALRL, res10: Word;
+ end;
+
+ TIWDGRegisters = record
+  KR, res1,
+  PR, res2,
+  RLR, res3,
+  SR, res4: word;
+ end;
+
+ TWWDGRegisters = record
+  CR, res2,
+  CFR, res3,
+  SR, res4: word;
+ end;
+
+ TSPIRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SR, res3,
+  DR, res4,
+  CRCPR, res5,
+  RXCRCR, res6,
+  TXCRCR, res7,
+  I2SCFGR, res8,
+  I2SPR, res9: Word;
+ end;
+
+ TUSARTRegisters = record
+  SR, res1,
+  DR, res2,
+  BRR, res3,
+  CR1, res4,
+  CR2, res5,
+  CR3, res6,
+  GTPR, res7: Word;
+ end;
+
+ TI2CRegisters = record
+  CR1, res1,
+  CR2, res2,
+  OAR1, res3,
+  OAR2, res4,
+  DR, res5,
+  SR1, res6,
+  SR2, res7,
+  CCR, res8: word;
+  TRISE: byte;
+ end;
+
+ TUSBRegisters = record
+  EPR: array[0..7] of longword;
+
+  res: array[0..7] of longword;
+
+  CNTR, res1,
+  ISTR, res2,
+  FNR, res3: Word;
+  DADDR: byte; res4: word; res5: byte;
+  BTABLE: Word;
+ end;
+
+ TUSBMem = packed array[0..511] of byte;
+
+ TCANMailbox = record
+  IR,
+  DTR,
+  DLR,
+  DHR: longword;
+ end;
+
+ TCANRegisters = record
+  MCR,
+  MSR,
+  TSR,
+  RF0R,
+  RF1R,
+  IER,
+  ESR,
+  BTR: longword;
+
+  res5: array[$020..$17F] of byte;
+
+  TX: array[0..2] of TCANMailbox;
+  RX: array[0..2] of TCANMailbox;
+
+  res6: array[$1D0..$1FF] of byte;
+
+  FMR,
+  FM1R,
+  res9: longword;
+  FS1R, res10: word;
+  res11: longword;
+  FFA1R, res12: word;
+  res13: longword;
+  FA1R, res14: word;
+  res15: array[$220..$23F] of byte;
+
+  FOR1,
+  FOR2: longword;
+
+  FB: array[1..13] of array[1..2] of longword;
+ end;
+
+ TBKPRegisters = record
+  DR: array[1..10] of record data, res: word; end;
+
+  RTCCR,
+  CR,
+  CSR,
+  res1,res2: longword;
+
+  DR2: array[11..42] of record data, res: word; end;
+ end;
+
+ TPwrRegisters = record
+  CR, res: word;
+  CSR: Word;
+ end;
+
+ TDACRegisters = record
+  CR,
+  SWTRIGR: longword;
+
+  DHR12R1, res2,
+  DHR12L1, res3,
+  DHR8R1, res4,
+  DHR12R2, res5,
+  DHR12L2, res6,
+  DHR8R2, res7: word;
+
+  DHR12RD,
+  DHR12LD: longword;
+
+  DHR8RD, res8,
+
+  DOR1, res9,
+  DOR2, res10: Word;
+ end;
+
+ TAFIORegisters = record
+  EVCR,
+  MAPR: longword;
+  EXTICR: array[0..3] of longword;
+ end;
+
+ TEXTIRegisters = record
+  IMR,
+  EMR,
+  RTSR,
+  FTSR,
+  SWIER,
+  PR: longword;
+ end;
+
+ TPortRegisters = record
+  CRL,
+  CRH,
+  IDR,
+  ODR,
+  BSRR,
+  BRR,
+  LCKR: longword;
+ end;
+
+ TADCRegisters = record
+  SR,
+  CR1,
+  CR2,
+  SMPR1,
+  SMPR2: longword;
+  JOFR1, res2,
+  JOFR2, res3,
+  JOFR3, res4,
+  JOFR4, res5,
+  HTR, res6,
+  LTR, res7: word;
+  SQR1,
+  SQR2,
+  SQR3,
+  JSQR: longword;
+  JDR1, res8,
+  JDR2, res9,
+  JDR3, res10,
+  JDR4, res11: Word;
+  DR: longword;
+ end;
+
+ TSDIORegisters = record
+  POWER,
+  CLKCR,
+  ARG: longword;
+  CMD, res3,
+  RESPCMD, res4: Word;
+  RESP1,
+  RESP2,
+  RESP3,
+  RESP4,
+  DTIMER,
+  DLEN: longword;
+  DCTRL, res5: word;
+  DCOUNT,
+  STA,
+  ICR,
+  MASK,
+  FIFOCNT,
+  FIFO: longword;
+ end;
+
+ TDMAChannel = record
+  CCR, res1,
+  CNDTR, res2: word;
+  CPAR,
+  CMAR,
+  res: longword;
+ end;
+
+ TDMARegisters = record
+  ISR,
+  IFCR: longword;
+  Channel: array[0..7] of TDMAChannel;
+ end;
+
+ TRCCRegisters = record
+  CR,
+  CFGR,
+  CIR,
+  APB2RSTR,
+  APB1RSTR,
+  AHBENR,
+  APB2ENR,
+  APB1ENR,
+  BDCR,
+  CSR: longword;
+ end;
+
+ TCRCRegisters = record
+  DR: longword;
+  IDR: byte; res1: word; res2: byte;
+  CR: byte;
+ end;
+
+ TFSMCRegisters = record
+  nothingyet: byte;
+ end;
+
+ TFlashRegisters = record
+  ACR,
+  KEYR,
+  OPTKEYR,
+  SR,
+  CR,
+  AR,
+  res,
+  OBR,
+  WRPR: longword;
+ end;
+
+ TNVICRegisters = record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of longword;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  VTOR,                             {!< Vector Table Offset Register                             }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+  SHCSR,                            {!< System Handler Control and State Register                }
+  CFSR,                             {!< Configurable Fault Status Register                       }
+  HFSR,                             {!< Hard Fault Status Register                               }
+  DFSR,                             {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                              }
+  BFAR,                             {!< Bus Fault Address Register                               }
+  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: longword;
+ end;
+
+{$ALIGN 2}
+var
+ { Timers }
+ Timer1: TTimerRegisters 	absolute (APB2Base+$2C00);
+ Timer2: TTimerRegisters 	absolute (APB1Base+$0000);
+ Timer3: TTimerRegisters 	absolute (APB1Base+$0400);
+ Timer4: TTimerRegisters 	absolute (APB1Base+$0800);
+ Timer5: TTimerRegisters 	absolute (APB1Base+$0C00);
+ Timer6: TTimerRegisters 	absolute (APB1Base+$1000);
+ Timer7: TTimerRegisters 	absolute (APB1Base+$1400);
+ Timer8: TTimerRegisters 	absolute (APB2Base+$3400);
+
+ { RTC }
+ RTC: TRTCRegisters 			absolute (APB1Base+$2800);
+
+ { WDG }
+ WWDG: TWWDGRegisters 		absolute (APB1Base+$2C00);
+ IWDG: TIWDGRegisters 		absolute (APB1Base+$3000);
+
+ { SPI }
+ SPI1: TSPIRegisters			absolute (APB2Base+$3000);
+ SPI2: TSPIRegisters			absolute (APB1Base+$3800);
+ SPI3: TSPIRegisters			absolute (APB1Base+$3C00);
+
+ { USART/UART }
+ USART1: TUSARTRegisters	absolute (APB2Base+$3800);
+ USART2: TUSARTRegisters	absolute (APB1Base+$4400);
+ USART3: TUSARTRegisters	absolute (APB1Base+$4800);
+ UART4: TUSARTRegisters		absolute (APB1Base+$4C00);
+ UART5: TUSARTRegisters		absolute (APB1Base+$5000);
+
+ { I2C }
+ I2C1: TI2CRegisters			absolute (APB1Base+$5400);
+ I2C2: TI2CRegisters			absolute (APB1Base+$5800);
+
+ { USB }
+ USB: TUSBRegisters			absolute (APB1Base+$5C00);
+ USBMem: TUSBMem                        absolute (APB1Base+$6000);
+
+ { CAN }
+ CAN: TCANRegisters			absolute (APB1Base+$6800);
+
+ { BKP }
+ BKP: TBKPRegisters			absolute (APB1Base+$6C00);
+
+ { PWR }
+ PWR: TPwrRegisters			absolute (APB1Base+$7000);
+
+ { DAC }
+ DAC: TDACRegisters			absolute (APB1Base+$7400);
+
+ { GPIO }
+ AFIO: TAFIORegisters		absolute (APB2Base+$0);
+ EXTI: TEXTIRegisters		absolute (APB2Base+$0400);
+
+ PortA: TPortRegisters		absolute (APB2Base+$0800);
+ PortB: TPortRegisters		absolute (APB2Base+$0C00);
+ PortC: TPortRegisters		absolute (APB2Base+$1000);
+ PortD: TPortRegisters		absolute (APB2Base+$1400);
+ PortE: TPortRegisters		absolute (APB2Base+$1800);
+ PortF: TPortRegisters		absolute (APB2Base+$1C00);
+ PortG: TPortRegisters		absolute (APB2Base+$2000);
+
+ { ADC }
+ ADC1: TADCRegisters			absolute (APB2Base+$2400);
+ ADC2: TADCRegisters			absolute (APB2Base+$2800);
+ ADC3: TADCRegisters			absolute (APB2Base+$3C00);
+
+ { SDIO }
+ SDIO: TSDIORegisters		absolute (APB2Base+$8000);
+
+ { DMA }
+ DMA1: TDMARegisters			absolute (AHBBase+$0000);
+ DMA2: TDMARegisters			absolute (AHBBase+$0400);
+
+ { RCC }
+ RCC: TRCCRegisters			absolute (AHBBase+$1000);
+
+ { Flash }
+ Flash: TFlashRegisters		absolute (AHBBase+$2000);
+
+ { CRC }
+ CRC: TCRCRegisters			absolute (AHBBase+$3000);
+
+ { SCB }
+ SCB: TSCBRegisters        absolute (SCS_BASE+$0D00);
+
+ { SysTick }
+ SysTick: TSysTickRegisters   absolute (SCS_BASE+$0010);
+
+ { NVIC }
+ NVIC: TNVICRegisters      absolute (SCS_BASE+$0100);
+
+implementation
+
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
+procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
+procedure Tamper_interrupt; external name 'Tamper_interrupt';
+procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
+procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
+procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
+procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
+procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
+procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
+procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
+procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
+procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
+procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
+procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
+procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
+procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
+procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
+procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
+procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
+procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
+procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
+procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
+procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
+procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
+procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
+procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
+procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
+procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
+procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
+procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
+procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
+procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
+procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
+procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
+procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
+procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
+procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
+procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
+procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
+procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
+procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
+procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
+procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
+procedure TIM8_Break_interrupt; external name 'TIM8_Break_interrupt';
+procedure TIM8_Update_interrupt; external name 'TIM8_Update_interrupt';
+procedure TIM8_Trigger_and_Commutation_interrupts; external name 'TIM8_Trigger_and_Commutation_interrupts';
+procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
+procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
+procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
+procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
+procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
+procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
+procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
+procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
+procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
+procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
+procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
+procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
+procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
+procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
+
+{$i cortexm3_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+   .section ".init.interrupt_vectors"
+interrupt_vectors:
+   .long _stack_top
+   .long Startup
+   .long NMI_interrupt
+   .long Hardfault_interrupt
+   .long MemManage_interrupt
+   .long BusFault_interrupt
+   .long UsageFault_interrupt
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long SWI_interrupt
+   .long DebugMonitor_interrupt
+   .long 0
+   .long PendingSV_interrupt
+   .long SysTick_interrupt
+   
+   .long Window_watchdog_interrupt
+   .long PVD_through_EXTI_Line_detection_interrupt
+   .long Tamper_interrupt
+   .long RTC_global_interrupt
+   .long Flash_global_interrupt
+   .long RCC_global_interrupt
+   .long EXTI_Line0_interrupt
+   .long EXTI_Line1_interrupt
+   .long EXTI_Line2_interrupt
+   .long EXTI_Line3_interrupt
+   .long EXTI_Line4_interrupt
+   .long DMA1_Channel1_global_interrupt
+   .long DMA1_Channel2_global_interrupt
+   .long DMA1_Channel3_global_interrupt
+   .long DMA1_Channel4_global_interrupt
+   .long DMA1_Channel5_global_interrupt
+   .long DMA1_Channel6_global_interrupt
+   .long DMA1_Channel7_global_interrupt
+   .long ADC1_and_ADC2_global_interrupt
+   .long USB_High_Priority_or_CAN_TX_interrupts
+   .long USB_Low_Priority_or_CAN_RX0_interrupts
+   .long CAN_RX1_interrupt
+   .long CAN_SCE_interrupt
+   .long EXTI_Line9_5_interrupts
+   .long TIM1_Break_interrupt
+   .long TIM1_Update_interrupt
+   .long TIM1_Trigger_and_Commutation_interrupts
+   .long TIM1_Capture_Compare_interrupt
+   .long TIM2_global_interrupt
+   .long TIM3_global_interrupt
+   .long TIM4_global_interrupt
+   .long I2C1_event_interrupt
+   .long I2C1_error_interrupt
+   .long I2C2_event_interrupt
+   .long I2C2_error_interrupt
+   .long SPI1_global_interrupt
+   .long SPI2_global_interrupt
+   .long USART1_global_interrupt
+   .long USART2_global_interrupt
+   .long USART3_global_interrupt
+   .long EXTI_Line15_10_interrupts
+   .long RTC_alarm_through_EXTI_line_interrupt
+   .long USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .long TIM8_Break_interrupt
+   .long TIM8_Update_interrupt
+   .long TIM8_Trigger_and_Commutation_interrupts
+   .long TIM8_Capture_Compare_interrupt
+   .long ADC3_global_interrupt
+   .long FSMC_global_interrupt
+   .long SDIO_global_interrupt
+   .long TIM5_global_interrupt
+   .long SPI3_global_interrupt
+   .long UART4_global_interrupt
+   .long UART5_global_interrupt
+   .long TIM6_global_interrupt
+   .long TIM7_global_interrupt
+   .long DMA2_Channel1_global_interrupt
+   .long DMA2_Channel2_global_interrupt
+   .long DMA2_Channel3_global_interrupt
+   .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+   
+   .weak NMI_interrupt
+   .weak Hardfault_interrupt
+   .weak MemManage_interrupt
+   .weak BusFault_interrupt
+   .weak UsageFault_interrupt
+   .weak SWI_interrupt
+   .weak DebugMonitor_interrupt
+   .weak PendingSV_interrupt
+   .weak SysTick_interrupt
+   
+   .weak Window_watchdog_interrupt
+   .weak PVD_through_EXTI_Line_detection_interrupt
+   .weak Tamper_interrupt
+   .weak RTC_global_interrupt
+   .weak Flash_global_interrupt
+   .weak RCC_global_interrupt
+   .weak EXTI_Line0_interrupt
+   .weak EXTI_Line1_interrupt
+   .weak EXTI_Line2_interrupt
+   .weak EXTI_Line3_interrupt
+   .weak EXTI_Line4_interrupt
+   .weak DMA1_Channel1_global_interrupt
+   .weak DMA1_Channel2_global_interrupt
+   .weak DMA1_Channel3_global_interrupt
+   .weak DMA1_Channel4_global_interrupt
+   .weak DMA1_Channel5_global_interrupt
+   .weak DMA1_Channel6_global_interrupt
+   .weak DMA1_Channel7_global_interrupt
+   .weak ADC1_and_ADC2_global_interrupt
+   .weak USB_High_Priority_or_CAN_TX_interrupts
+   .weak USB_Low_Priority_or_CAN_RX0_interrupts
+   .weak CAN_RX1_interrupt
+   .weak CAN_SCE_interrupt
+   .weak EXTI_Line9_5_interrupts
+   .weak TIM1_Break_interrupt
+   .weak TIM1_Update_interrupt
+   .weak TIM1_Trigger_and_Commutation_interrupts
+   .weak TIM1_Capture_Compare_interrupt
+   .weak TIM2_global_interrupt
+   .weak TIM3_global_interrupt
+   .weak TIM4_global_interrupt
+   .weak I2C1_event_interrupt
+   .weak I2C1_error_interrupt
+   .weak I2C2_event_interrupt
+   .weak I2C2_error_interrupt
+   .weak SPI1_global_interrupt
+   .weak SPI2_global_interrupt
+   .weak USART1_global_interrupt
+   .weak USART2_global_interrupt
+   .weak USART3_global_interrupt
+   .weak EXTI_Line15_10_interrupts
+   .weak RTC_alarm_through_EXTI_line_interrupt
+   .weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .weak TIM8_Break_interrupt
+   .weak TIM8_Update_interrupt
+   .weak TIM8_Trigger_and_Commutation_interrupts
+   .weak TIM8_Capture_Compare_interrupt
+   .weak ADC3_global_interrupt
+   .weak FSMC_global_interrupt
+   .weak SDIO_global_interrupt
+   .weak TIM5_global_interrupt
+   .weak SPI3_global_interrupt
+   .weak UART4_global_interrupt
+   .weak UART5_global_interrupt
+   .weak TIM6_global_interrupt
+   .weak TIM7_global_interrupt
+   .weak DMA2_Channel1_global_interrupt
+   .weak DMA2_Channel2_global_interrupt
+   .weak DMA2_Channel3_global_interrupt
+   .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+
+   
+   .set NMI_interrupt, Startup
+   .set Hardfault_interrupt, Startup
+   .set MemManage_interrupt, Startup
+   .set BusFault_interrupt, Startup
+   .set UsageFault_interrupt, Startup
+   .set SWI_interrupt, Startup
+   .set DebugMonitor_interrupt, Startup
+   .set PendingSV_interrupt, Startup
+   .set SysTick_interrupt, Startup
+
+   .set Window_watchdog_interrupt, Startup
+   .set PVD_through_EXTI_Line_detection_interrupt, Startup
+   .set Tamper_interrupt, Startup
+   .set RTC_global_interrupt, Startup
+   .set Flash_global_interrupt, Startup
+   .set RCC_global_interrupt, Startup
+   .set EXTI_Line0_interrupt, Startup
+   .set EXTI_Line1_interrupt, Startup
+   .set EXTI_Line2_interrupt, Startup
+   .set EXTI_Line3_interrupt, Startup
+   .set EXTI_Line4_interrupt, Startup
+   .set DMA1_Channel1_global_interrupt, Startup
+   .set DMA1_Channel2_global_interrupt, Startup
+   .set DMA1_Channel3_global_interrupt, Startup
+   .set DMA1_Channel4_global_interrupt, Startup
+   .set DMA1_Channel5_global_interrupt, Startup
+   .set DMA1_Channel6_global_interrupt, Startup
+   .set DMA1_Channel7_global_interrupt, Startup
+   .set ADC1_and_ADC2_global_interrupt, Startup
+   .set USB_High_Priority_or_CAN_TX_interrupts, Startup
+   .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
+   .set CAN_RX1_interrupt, Startup
+   .set CAN_SCE_interrupt, Startup
+   .set EXTI_Line9_5_interrupts, Startup
+   .set TIM1_Break_interrupt, Startup
+   .set TIM1_Update_interrupt, Startup
+   .set TIM1_Trigger_and_Commutation_interrupts, Startup
+   .set TIM1_Capture_Compare_interrupt, Startup
+   .set TIM2_global_interrupt, Startup
+   .set TIM3_global_interrupt, Startup
+   .set TIM4_global_interrupt, Startup
+   .set I2C1_event_interrupt, Startup
+   .set I2C1_error_interrupt, Startup
+   .set I2C2_event_interrupt, Startup
+   .set I2C2_error_interrupt, Startup
+   .set SPI1_global_interrupt, Startup
+   .set SPI2_global_interrupt, Startup
+   .set USART1_global_interrupt, Startup
+   .set USART2_global_interrupt, Startup
+   .set USART3_global_interrupt, Startup
+   .set EXTI_Line15_10_interrupts, Startup
+   .set RTC_alarm_through_EXTI_line_interrupt, Startup
+   .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
+   .set TIM8_Break_interrupt, Startup
+   .set TIM8_Update_interrupt, Startup
+   .set TIM8_Trigger_and_Commutation_interrupts, Startup
+   .set TIM8_Capture_Compare_interrupt, Startup
+   .set ADC3_global_interrupt, Startup
+   .set FSMC_global_interrupt, Startup
+   .set SDIO_global_interrupt, Startup
+   .set TIM5_global_interrupt, Startup
+   .set SPI3_global_interrupt, Startup
+   .set UART4_global_interrupt, Startup
+   .set UART5_global_interrupt, Startup
+   .set TIM6_global_interrupt, Startup
+   .set TIM7_global_interrupt, Startup
+   .set DMA2_Channel1_global_interrupt, Startup
+   .set DMA2_Channel2_global_interrupt, Startup
+   .set DMA2_Channel3_global_interrupt, Startup
+   .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
+   
+   .text
+end;
+
+end.

rtl/embedded/arm/stm32f10x_md.pp

@@ -0,0 +1,777 @@
+{
+Register definitions and utility code for STM32F10x - Medium density
+
+Created by Jeppe Johansen 2012 - [email protected]
+}
+unit stm32f10x_md;
+
+{$goto on}
+{$define stm32f10x_md}
+
+interface
+
+type
+ TBitvector32 = bitpacked array[0..31] of 0..1;
+
+{$PACKRECORDS 2}
+const
+ PeripheralBase 	= $40000000;
+
+ FSMCBase			= $60000000;
+
+ APB1Base 			= PeripheralBase;
+ APB2Base 			= PeripheralBase+$10000;
+ AHBBase 			= PeripheralBase+$20000;
+
+ SCS_BASE         = $E000E000;
+
+ { FSMC }
+ FSMCBank1NOR1		= FSMCBase+$00000000;
+ FSMCBank1NOR2		= FSMCBase+$04000000;
+ FSMCBank1NOR3		= FSMCBase+$08000000;
+ FSMCBank1NOR4		= FSMCBase+$0C000000;
+
+ FSMCBank1PSRAM1	= FSMCBase+$00000000;
+ FSMCBank1PSRAM2	= FSMCBase+$04000000;
+ FSMCBank1PSRAM3	= FSMCBase+$08000000;
+ FSMCBank1PSRAM4	= FSMCBase+$0C000000;
+
+ FSMCBank2NAND1	= FSMCBase+$10000000;
+ FSMCBank3NAND2	= FSMCBase+$20000000;
+
+ FSMCBank4PCCARD	= FSMCBase+$30000000;
+
+type
+ TTimerRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SMCR, res3,
+  DIER, res4,
+  SR, res5,
+  EGR, res,
+  CCMR1, res6,
+  CCMR2, res7,
+  CCER, res8,
+  CNT, res9,
+  PSC, res10,
+  ARR, res11,
+  RCR, res12,
+  CCR1, res13,
+  CCR2, res14,
+  CCR3, res15,
+  CCR4, res16,
+  BDTR, res17,
+  DCR, res18,
+  DMAR, res19: Word;
+ end;
+
+ TRTCRegisters = record
+  CRH, res1,
+  CRL, res2,
+  PRLH, res3,
+  PRLL, res4,
+  DIVH, res5,
+  DIVL, res6,
+  CNTH, res7,
+  CNTL, res8,
+  ALRH, res9,
+  ALRL, res10: Word;
+ end;
+
+ TIWDGRegisters = record
+  KR, res1,
+  PR, res2,
+  RLR, res3,
+  SR, res4: word;
+ end;
+
+ TWWDGRegisters = record
+  CR, res2,
+  CFR, res3,
+  SR, res4: word;
+ end;
+
+ TSPIRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SR, res3,
+  DR, res4,
+  CRCPR, res5,
+  RXCRCR, res6,
+  TXCRCR, res7,
+  I2SCFGR, res8,
+  I2SPR, res9: Word;
+ end;
+
+ TUSARTRegisters = record
+  SR, res1,
+  DR, res2,
+  BRR, res3,
+  CR1, res4,
+  CR2, res5,
+  CR3, res6,
+  GTPR, res7: Word;
+ end;
+
+ TI2CRegisters = record
+  CR1, res1,
+  CR2, res2,
+  OAR1, res3,
+  OAR2, res4,
+  DR, res5,
+  SR1, res6,
+  SR2, res7,
+  CCR, res8: word;
+  TRISE: byte;
+ end;
+
+ TUSBRegisters = record
+  EPR: array[0..7] of longword;
+
+  res: array[0..7] of longword;
+
+  CNTR, res1,
+  ISTR, res2,
+  FNR, res3: Word;
+  DADDR: byte; res4: word; res5: byte;
+  BTABLE: Word;
+ end;
+
+ TUSBMem = packed array[0..511] of byte;
+
+ TCANMailbox = record
+  IR,
+  DTR,
+  DLR,
+  DHR: longword;
+ end;
+
+ TCANRegisters = record
+  MCR,
+  MSR,
+  TSR,
+  RF0R,
+  RF1R,
+  IER,
+  ESR,
+  BTR: longword;
+
+  res5: array[$020..$17F] of byte;
+
+  TX: array[0..2] of TCANMailbox;
+  RX: array[0..2] of TCANMailbox;
+
+  res6: array[$1D0..$1FF] of byte;
+
+  FMR,
+  FM1R,
+  res9: longword;
+  FS1R, res10: word;
+  res11: longword;
+  FFA1R, res12: word;
+  res13: longword;
+  FA1R, res14: word;
+  res15: array[$220..$23F] of byte;
+
+  FOR1,
+  FOR2: longword;
+
+  FB: array[1..13] of array[1..2] of longword;
+ end;
+
+ TBKPRegisters = record
+  DR: array[1..10] of record data, res: word; end;
+
+  RTCCR,
+  CR,
+  CSR,
+  res1,res2: longword;
+
+  DR2: array[11..42] of record data, res: word; end;
+ end;
+
+ TPwrRegisters = record
+  CR, res: word;
+  CSR: Word;
+ end;
+
+ TDACRegisters = record
+  CR,
+  SWTRIGR: longword;
+
+  DHR12R1, res2,
+  DHR12L1, res3,
+  DHR8R1, res4,
+  DHR12R2, res5,
+  DHR12L2, res6,
+  DHR8R2, res7: word;
+
+  DHR12RD,
+  DHR12LD: longword;
+
+  DHR8RD, res8,
+
+  DOR1, res9,
+  DOR2, res10: Word;
+ end;
+
+ TAFIORegisters = record
+  EVCR,
+  MAPR: longword;
+  EXTICR: array[0..3] of longword;
+ end;
+
+ TEXTIRegisters = record
+  IMR,
+  EMR,
+  RTSR,
+  FTSR,
+  SWIER,
+  PR: longword;
+ end;
+
+ TPortRegisters = record
+  CRL,
+  CRH,
+  IDR,
+  ODR,
+  BSRR,
+  BRR,
+  LCKR: longword;
+ end;
+
+ TADCRegisters = record
+  SR,
+  CR1,
+  CR2,
+  SMPR1,
+  SMPR2: longword;
+  JOFR1, res2,
+  JOFR2, res3,
+  JOFR3, res4,
+  JOFR4, res5,
+  HTR, res6,
+  LTR, res7: word;
+  SQR1,
+  SQR2,
+  SQR3,
+  JSQR: longword;
+  JDR1, res8,
+  JDR2, res9,
+  JDR3, res10,
+  JDR4, res11: Word;
+  DR: longword;
+ end;
+
+ TSDIORegisters = record
+  POWER,
+  CLKCR,
+  ARG: longword;
+  CMD, res3,
+  RESPCMD, res4: Word;
+  RESP1,
+  RESP2,
+  RESP3,
+  RESP4,
+  DTIMER,
+  DLEN: longword;
+  DCTRL, res5: word;
+  DCOUNT,
+  STA,
+  ICR,
+  MASK,
+  FIFOCNT,
+  FIFO: longword;
+ end;
+
+ TDMAChannel = record
+  CCR, res1,
+  CNDTR, res2: word;
+  CPAR,
+  CMAR,
+  res: longword;
+ end;
+
+ TDMARegisters = record
+  ISR,
+  IFCR: longword;
+  Channel: array[0..7] of TDMAChannel;
+ end;
+
+ TRCCRegisters = record
+  CR,
+  CFGR,
+  CIR,
+  APB2RSTR,
+  APB1RSTR,
+  AHBENR,
+  APB2ENR,
+  APB1ENR,
+  BDCR,
+  CSR: longword;
+ end;
+
+ TCRCRegisters = record
+  DR: longword;
+  IDR: byte; res1: word; res2: byte;
+  CR: byte;
+ end;
+
+ TFSMCRegisters = record
+  nothingyet: byte;
+ end;
+
+ TFlashRegisters = record
+  ACR,
+  KEYR,
+  OPTKEYR,
+  SR,
+  CR,
+  AR,
+  res,
+  OBR,
+  WRPR: longword;
+ end;
+
+ TNVICRegisters = record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of longword;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  VTOR,                             {!< Vector Table Offset Register                             }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+  SHCSR,                            {!< System Handler Control and State Register                }
+  CFSR,                             {!< Configurable Fault Status Register                       }
+  HFSR,                             {!< Hard Fault Status Register                               }
+  DFSR,                             {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                              }
+  BFAR,                             {!< Bus Fault Address Register                               }
+  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: longword;
+ end;
+
+{$ALIGN 2}
+var
+ { Timers }
+ Timer1: TTimerRegisters 	absolute (APB2Base+$2C00);
+ Timer2: TTimerRegisters 	absolute (APB1Base+$0000);
+ Timer3: TTimerRegisters 	absolute (APB1Base+$0400);
+ Timer4: TTimerRegisters 	absolute (APB1Base+$0800);
+ Timer5: TTimerRegisters 	absolute (APB1Base+$0C00);
+ Timer6: TTimerRegisters 	absolute (APB1Base+$1000);
+ Timer7: TTimerRegisters 	absolute (APB1Base+$1400);
+ Timer8: TTimerRegisters 	absolute (APB2Base+$3400);
+
+ { RTC }
+ RTC: TRTCRegisters 			absolute (APB1Base+$2800);
+
+ { WDG }
+ WWDG: TWWDGRegisters 		absolute (APB1Base+$2C00);
+ IWDG: TIWDGRegisters 		absolute (APB1Base+$3000);
+
+ { SPI }
+ SPI1: TSPIRegisters			absolute (APB2Base+$3000);
+ SPI2: TSPIRegisters			absolute (APB1Base+$3800);
+ SPI3: TSPIRegisters			absolute (APB1Base+$3C00);
+
+ { USART/UART }
+ USART1: TUSARTRegisters	absolute (APB2Base+$3800);
+ USART2: TUSARTRegisters	absolute (APB1Base+$4400);
+ USART3: TUSARTRegisters	absolute (APB1Base+$4800);
+ UART4: TUSARTRegisters		absolute (APB1Base+$4C00);
+ UART5: TUSARTRegisters		absolute (APB1Base+$5000);
+
+ { I2C }
+ I2C1: TI2CRegisters			absolute (APB1Base+$5400);
+ I2C2: TI2CRegisters			absolute (APB1Base+$5800);
+
+ { USB }
+ USB: TUSBRegisters			absolute (APB1Base+$5C00);
+ USBMem: TUSBMem                        absolute (APB1Base+$6000);
+
+ { CAN }
+ CAN: TCANRegisters			absolute (APB1Base+$6800);
+
+ { BKP }
+ BKP: TBKPRegisters			absolute (APB1Base+$6C00);
+
+ { PWR }
+ PWR: TPwrRegisters			absolute (APB1Base+$7000);
+
+ { DAC }
+ DAC: TDACRegisters			absolute (APB1Base+$7400);
+
+ { GPIO }
+ AFIO: TAFIORegisters		absolute (APB2Base+$0);
+ EXTI: TEXTIRegisters		absolute (APB2Base+$0400);
+
+ PortA: TPortRegisters		absolute (APB2Base+$0800);
+ PortB: TPortRegisters		absolute (APB2Base+$0C00);
+ PortC: TPortRegisters		absolute (APB2Base+$1000);
+ PortD: TPortRegisters		absolute (APB2Base+$1400);
+ PortE: TPortRegisters		absolute (APB2Base+$1800);
+ PortF: TPortRegisters		absolute (APB2Base+$1C00);
+ PortG: TPortRegisters		absolute (APB2Base+$2000);
+
+ { ADC }
+ ADC1: TADCRegisters			absolute (APB2Base+$2400);
+ ADC2: TADCRegisters			absolute (APB2Base+$2800);
+ ADC3: TADCRegisters			absolute (APB2Base+$3C00);
+
+ { SDIO }
+ SDIO: TSDIORegisters		absolute (APB2Base+$8000);
+
+ { DMA }
+ DMA1: TDMARegisters			absolute (AHBBase+$0000);
+ DMA2: TDMARegisters			absolute (AHBBase+$0400);
+
+ { RCC }
+ RCC: TRCCRegisters			absolute (AHBBase+$1000);
+
+ { Flash }
+ Flash: TFlashRegisters		absolute (AHBBase+$2000);
+
+ { CRC }
+ CRC: TCRCRegisters			absolute (AHBBase+$3000);
+
+ { SCB }
+ SCB: TSCBRegisters        absolute (SCS_BASE+$0D00);
+
+ { SysTick }
+ SysTick: TSysTickRegisters   absolute (SCS_BASE+$0010);
+
+ { NVIC }
+ NVIC: TNVICRegisters      absolute (SCS_BASE+$0100);
+
+implementation
+
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
+procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
+procedure Tamper_interrupt; external name 'Tamper_interrupt';
+procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
+procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
+procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
+procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
+procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
+procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
+procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
+procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
+procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
+procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
+procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
+procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
+procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
+procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
+procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
+procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
+procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
+procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
+procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
+procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
+procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
+procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
+procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
+procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
+procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
+procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
+procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
+procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
+procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
+procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
+procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
+procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
+procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
+procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
+procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
+procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
+procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
+procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
+procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
+procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
+procedure TIM8_Break_interrupt; external name 'TIM8_Break_interrupt';
+procedure TIM8_Update_interrupt; external name 'TIM8_Update_interrupt';
+procedure TIM8_Trigger_and_Commutation_interrupts; external name 'TIM8_Trigger_and_Commutation_interrupts';
+procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
+procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
+procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
+procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
+procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
+procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
+procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
+procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
+procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
+procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
+procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
+procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
+procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
+procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
+
+{$i cortexm3_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+   .section ".init.interrupt_vectors"
+interrupt_vectors:
+   .long _stack_top
+   .long Startup
+   .long NMI_interrupt
+   .long Hardfault_interrupt
+   .long MemManage_interrupt
+   .long BusFault_interrupt
+   .long UsageFault_interrupt
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long SWI_interrupt
+   .long DebugMonitor_interrupt
+   .long 0
+   .long PendingSV_interrupt
+   .long SysTick_interrupt
+   
+   .long Window_watchdog_interrupt
+   .long PVD_through_EXTI_Line_detection_interrupt
+   .long Tamper_interrupt
+   .long RTC_global_interrupt
+   .long Flash_global_interrupt
+   .long RCC_global_interrupt
+   .long EXTI_Line0_interrupt
+   .long EXTI_Line1_interrupt
+   .long EXTI_Line2_interrupt
+   .long EXTI_Line3_interrupt
+   .long EXTI_Line4_interrupt
+   .long DMA1_Channel1_global_interrupt
+   .long DMA1_Channel2_global_interrupt
+   .long DMA1_Channel3_global_interrupt
+   .long DMA1_Channel4_global_interrupt
+   .long DMA1_Channel5_global_interrupt
+   .long DMA1_Channel6_global_interrupt
+   .long DMA1_Channel7_global_interrupt
+   .long ADC1_and_ADC2_global_interrupt
+   .long USB_High_Priority_or_CAN_TX_interrupts
+   .long USB_Low_Priority_or_CAN_RX0_interrupts
+   .long CAN_RX1_interrupt
+   .long CAN_SCE_interrupt
+   .long EXTI_Line9_5_interrupts
+   .long TIM1_Break_interrupt
+   .long TIM1_Update_interrupt
+   .long TIM1_Trigger_and_Commutation_interrupts
+   .long TIM1_Capture_Compare_interrupt
+   .long TIM2_global_interrupt
+   .long TIM3_global_interrupt
+   .long TIM4_global_interrupt
+   .long I2C1_event_interrupt
+   .long I2C1_error_interrupt
+   .long I2C2_event_interrupt
+   .long I2C2_error_interrupt
+   .long SPI1_global_interrupt
+   .long SPI2_global_interrupt
+   .long USART1_global_interrupt
+   .long USART2_global_interrupt
+   .long USART3_global_interrupt
+   .long EXTI_Line15_10_interrupts
+   .long RTC_alarm_through_EXTI_line_interrupt
+   .long USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .long TIM8_Break_interrupt
+   .long TIM8_Update_interrupt
+   .long TIM8_Trigger_and_Commutation_interrupts
+   .long TIM8_Capture_Compare_interrupt
+   .long ADC3_global_interrupt
+   .long FSMC_global_interrupt
+   .long SDIO_global_interrupt
+   .long TIM5_global_interrupt
+   .long SPI3_global_interrupt
+   .long UART4_global_interrupt
+   .long UART5_global_interrupt
+   .long TIM6_global_interrupt
+   .long TIM7_global_interrupt
+   .long DMA2_Channel1_global_interrupt
+   .long DMA2_Channel2_global_interrupt
+   .long DMA2_Channel3_global_interrupt
+   .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+   
+   .weak NMI_interrupt
+   .weak Hardfault_interrupt
+   .weak MemManage_interrupt
+   .weak BusFault_interrupt
+   .weak UsageFault_interrupt
+   .weak SWI_interrupt
+   .weak DebugMonitor_interrupt
+   .weak PendingSV_interrupt
+   .weak SysTick_interrupt
+   
+   .weak Window_watchdog_interrupt
+   .weak PVD_through_EXTI_Line_detection_interrupt
+   .weak Tamper_interrupt
+   .weak RTC_global_interrupt
+   .weak Flash_global_interrupt
+   .weak RCC_global_interrupt
+   .weak EXTI_Line0_interrupt
+   .weak EXTI_Line1_interrupt
+   .weak EXTI_Line2_interrupt
+   .weak EXTI_Line3_interrupt
+   .weak EXTI_Line4_interrupt
+   .weak DMA1_Channel1_global_interrupt
+   .weak DMA1_Channel2_global_interrupt
+   .weak DMA1_Channel3_global_interrupt
+   .weak DMA1_Channel4_global_interrupt
+   .weak DMA1_Channel5_global_interrupt
+   .weak DMA1_Channel6_global_interrupt
+   .weak DMA1_Channel7_global_interrupt
+   .weak ADC1_and_ADC2_global_interrupt
+   .weak USB_High_Priority_or_CAN_TX_interrupts
+   .weak USB_Low_Priority_or_CAN_RX0_interrupts
+   .weak CAN_RX1_interrupt
+   .weak CAN_SCE_interrupt
+   .weak EXTI_Line9_5_interrupts
+   .weak TIM1_Break_interrupt
+   .weak TIM1_Update_interrupt
+   .weak TIM1_Trigger_and_Commutation_interrupts
+   .weak TIM1_Capture_Compare_interrupt
+   .weak TIM2_global_interrupt
+   .weak TIM3_global_interrupt
+   .weak TIM4_global_interrupt
+   .weak I2C1_event_interrupt
+   .weak I2C1_error_interrupt
+   .weak I2C2_event_interrupt
+   .weak I2C2_error_interrupt
+   .weak SPI1_global_interrupt
+   .weak SPI2_global_interrupt
+   .weak USART1_global_interrupt
+   .weak USART2_global_interrupt
+   .weak USART3_global_interrupt
+   .weak EXTI_Line15_10_interrupts
+   .weak RTC_alarm_through_EXTI_line_interrupt
+   .weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .weak TIM8_Break_interrupt
+   .weak TIM8_Update_interrupt
+   .weak TIM8_Trigger_and_Commutation_interrupts
+   .weak TIM8_Capture_Compare_interrupt
+   .weak ADC3_global_interrupt
+   .weak FSMC_global_interrupt
+   .weak SDIO_global_interrupt
+   .weak TIM5_global_interrupt
+   .weak SPI3_global_interrupt
+   .weak UART4_global_interrupt
+   .weak UART5_global_interrupt
+   .weak TIM6_global_interrupt
+   .weak TIM7_global_interrupt
+   .weak DMA2_Channel1_global_interrupt
+   .weak DMA2_Channel2_global_interrupt
+   .weak DMA2_Channel3_global_interrupt
+   .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+
+   
+   .set NMI_interrupt, Startup
+   .set Hardfault_interrupt, Startup
+   .set MemManage_interrupt, Startup
+   .set BusFault_interrupt, Startup
+   .set UsageFault_interrupt, Startup
+   .set SWI_interrupt, Startup
+   .set DebugMonitor_interrupt, Startup
+   .set PendingSV_interrupt, Startup
+   .set SysTick_interrupt, Startup
+
+   .set Window_watchdog_interrupt, Startup
+   .set PVD_through_EXTI_Line_detection_interrupt, Startup
+   .set Tamper_interrupt, Startup
+   .set RTC_global_interrupt, Startup
+   .set Flash_global_interrupt, Startup
+   .set RCC_global_interrupt, Startup
+   .set EXTI_Line0_interrupt, Startup
+   .set EXTI_Line1_interrupt, Startup
+   .set EXTI_Line2_interrupt, Startup
+   .set EXTI_Line3_interrupt, Startup
+   .set EXTI_Line4_interrupt, Startup
+   .set DMA1_Channel1_global_interrupt, Startup
+   .set DMA1_Channel2_global_interrupt, Startup
+   .set DMA1_Channel3_global_interrupt, Startup
+   .set DMA1_Channel4_global_interrupt, Startup
+   .set DMA1_Channel5_global_interrupt, Startup
+   .set DMA1_Channel6_global_interrupt, Startup
+   .set DMA1_Channel7_global_interrupt, Startup
+   .set ADC1_and_ADC2_global_interrupt, Startup
+   .set USB_High_Priority_or_CAN_TX_interrupts, Startup
+   .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
+   .set CAN_RX1_interrupt, Startup
+   .set CAN_SCE_interrupt, Startup
+   .set EXTI_Line9_5_interrupts, Startup
+   .set TIM1_Break_interrupt, Startup
+   .set TIM1_Update_interrupt, Startup
+   .set TIM1_Trigger_and_Commutation_interrupts, Startup
+   .set TIM1_Capture_Compare_interrupt, Startup
+   .set TIM2_global_interrupt, Startup
+   .set TIM3_global_interrupt, Startup
+   .set TIM4_global_interrupt, Startup
+   .set I2C1_event_interrupt, Startup
+   .set I2C1_error_interrupt, Startup
+   .set I2C2_event_interrupt, Startup
+   .set I2C2_error_interrupt, Startup
+   .set SPI1_global_interrupt, Startup
+   .set SPI2_global_interrupt, Startup
+   .set USART1_global_interrupt, Startup
+   .set USART2_global_interrupt, Startup
+   .set USART3_global_interrupt, Startup
+   .set EXTI_Line15_10_interrupts, Startup
+   .set RTC_alarm_through_EXTI_line_interrupt, Startup
+   .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
+   .set TIM8_Break_interrupt, Startup
+   .set TIM8_Update_interrupt, Startup
+   .set TIM8_Trigger_and_Commutation_interrupts, Startup
+   .set TIM8_Capture_Compare_interrupt, Startup
+   .set ADC3_global_interrupt, Startup
+   .set FSMC_global_interrupt, Startup
+   .set SDIO_global_interrupt, Startup
+   .set TIM5_global_interrupt, Startup
+   .set SPI3_global_interrupt, Startup
+   .set UART4_global_interrupt, Startup
+   .set UART5_global_interrupt, Startup
+   .set TIM6_global_interrupt, Startup
+   .set TIM7_global_interrupt, Startup
+   .set DMA2_Channel1_global_interrupt, Startup
+   .set DMA2_Channel2_global_interrupt, Startup
+   .set DMA2_Channel3_global_interrupt, Startup
+   .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
+   
+   .text
+end;
+
+end.

rtl/embedded/arm/stm32f10x_xl.pp

@@ -0,0 +1,778 @@
+{
+Register definitions and utility code for STM32F10x - XL density
+
+Created by Jeppe Johansen 2012 - [email protected]
+}
+unit stm32f10x_xl;
+
+{$goto on}
+{$define stm32f10x_xl}
+
+interface
+
+type
+ TBitvector32 = bitpacked array[0..31] of 0..1;
+
+{$PACKRECORDS 2}
+const
+ PeripheralBase 	= $40000000;
+
+ FSMCBase			= $60000000;
+
+ APB1Base 			= PeripheralBase;
+ APB2Base 			= PeripheralBase+$10000;
+ AHBBase 			= PeripheralBase+$20000;
+
+ SCS_BASE         = $E000E000;
+
+ { FSMC }
+ FSMCBank1NOR1		= FSMCBase+$00000000;
+ FSMCBank1NOR2		= FSMCBase+$04000000;
+ FSMCBank1NOR3		= FSMCBase+$08000000;
+ FSMCBank1NOR4		= FSMCBase+$0C000000;
+
+ FSMCBank1PSRAM1	= FSMCBase+$00000000;
+ FSMCBank1PSRAM2	= FSMCBase+$04000000;
+ FSMCBank1PSRAM3	= FSMCBase+$08000000;
+ FSMCBank1PSRAM4	= FSMCBase+$0C000000;
+
+ FSMCBank2NAND1	= FSMCBase+$10000000;
+ FSMCBank3NAND2	= FSMCBase+$20000000;
+
+ FSMCBank4PCCARD	= FSMCBase+$30000000;
+
+type
+ TTimerRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SMCR, res3,
+  DIER, res4,
+  SR, res5,
+  EGR, res,
+  CCMR1, res6,
+  CCMR2, res7,
+  CCER, res8,
+  CNT, res9,
+  PSC, res10,
+  ARR, res11,
+  RCR, res12,
+  CCR1, res13,
+  CCR2, res14,
+  CCR3, res15,
+  CCR4, res16,
+  BDTR, res17,
+  DCR, res18,
+  DMAR, res19: Word;
+ end;
+
+ TRTCRegisters = record
+  CRH, res1,
+  CRL, res2,
+  PRLH, res3,
+  PRLL, res4,
+  DIVH, res5,
+  DIVL, res6,
+  CNTH, res7,
+  CNTL, res8,
+  ALRH, res9,
+  ALRL, res10: Word;
+ end;
+
+ TIWDGRegisters = record
+  KR, res1,
+  PR, res2,
+  RLR, res3,
+  SR, res4: word;
+ end;
+
+ TWWDGRegisters = record
+  CR, res2,
+  CFR, res3,
+  SR, res4: word;
+ end;
+
+ TSPIRegisters = record
+  CR1, res1,
+  CR2, res2,
+  SR, res3,
+  DR, res4,
+  CRCPR, res5,
+  RXCRCR, res6,
+  TXCRCR, res7,
+  I2SCFGR, res8,
+  I2SPR, res9: Word;
+ end;
+
+ TUSARTRegisters = record
+  SR, res1,
+  DR, res2,
+  BRR, res3,
+  CR1, res4,
+  CR2, res5,
+  CR3, res6,
+  GTPR, res7: Word;
+ end;
+
+ TI2CRegisters = record
+  CR1, res1,
+  CR2, res2,
+  OAR1, res3,
+  OAR2, res4,
+  DR, res5,
+  SR1, res6,
+  SR2, res7,
+  CCR, res8: word;
+  TRISE: byte;
+ end;
+
+ TUSBRegisters = record
+  EPR: array[0..7] of longword;
+
+  res: array[0..7] of longword;
+
+  CNTR, res1,
+  ISTR, res2,
+  FNR, res3: Word;
+  DADDR: byte; res4: word; res5: byte;
+  BTABLE: Word;
+ end;
+
+ TUSBMem = packed array[0..511] of byte;
+
+ TCANMailbox = record
+  IR,
+  DTR,
+  DLR,
+  DHR: longword;
+ end;
+
+ TCANRegisters = record
+  MCR,
+  MSR,
+  TSR,
+  RF0R,
+  RF1R,
+  IER,
+  ESR,
+  BTR: longword;
+
+  res5: array[$020..$17F] of byte;
+
+  TX: array[0..2] of TCANMailbox;
+  RX: array[0..2] of TCANMailbox;
+
+  res6: array[$1D0..$1FF] of byte;
+
+  FMR,
+  FM1R,
+  res9: longword;
+  FS1R, res10: word;
+  res11: longword;
+  FFA1R, res12: word;
+  res13: longword;
+  FA1R, res14: word;
+  res15: array[$220..$23F] of byte;
+
+  FOR1,
+  FOR2: longword;
+
+  FB: array[1..13] of array[1..2] of longword;
+ end;
+
+ TBKPRegisters = record
+  DR: array[1..10] of record data, res: word; end;
+
+  RTCCR,
+  CR,
+  CSR,
+  res1,res2: longword;
+
+  DR2: array[11..42] of record data, res: word; end;
+ end;
+
+ TPwrRegisters = record
+  CR, res: word;
+  CSR: Word;
+ end;
+
+ TDACRegisters = record
+  CR,
+  SWTRIGR: longword;
+
+  DHR12R1, res2,
+  DHR12L1, res3,
+  DHR8R1, res4,
+  DHR12R2, res5,
+  DHR12L2, res6,
+  DHR8R2, res7: word;
+
+  DHR12RD,
+  DHR12LD: longword;
+
+  DHR8RD, res8,
+
+  DOR1, res9,
+  DOR2, res10: Word;
+ end;
+
+ TAFIORegisters = record
+  EVCR,
+  MAPR: longword;
+  EXTICR: array[0..3] of longword;
+ end;
+
+ TEXTIRegisters = record
+  IMR,
+  EMR,
+  RTSR,
+  FTSR,
+  SWIER,
+  PR: longword;
+ end;
+
+ TPortRegisters = record
+  CRL,
+  CRH,
+  IDR,
+  ODR,
+  BSRR,
+  BRR,
+  LCKR: longword;
+ end;
+
+ TADCRegisters = record
+  SR,
+  CR1,
+  CR2,
+  SMPR1,
+  SMPR2: longword;
+  JOFR1, res2,
+  JOFR2, res3,
+  JOFR3, res4,
+  JOFR4, res5,
+  HTR, res6,
+  LTR, res7: word;
+  SQR1,
+  SQR2,
+  SQR3,
+  JSQR: longword;
+  JDR1, res8,
+  JDR2, res9,
+  JDR3, res10,
+  JDR4, res11: Word;
+  DR: longword;
+ end;
+
+ TSDIORegisters = record
+  POWER,
+  CLKCR,
+  ARG: longword;
+  CMD, res3,
+  RESPCMD, res4: Word;
+  RESP1,
+  RESP2,
+  RESP3,
+  RESP4,
+  DTIMER,
+  DLEN: longword;
+  DCTRL, res5: word;
+  DCOUNT,
+  STA,
+  ICR,
+  MASK,
+  FIFOCNT,
+  FIFO: longword;
+ end;
+
+ TDMAChannel = record
+  CCR, res1,
+  CNDTR, res2: word;
+  CPAR,
+  CMAR,
+  res: longword;
+ end;
+
+ TDMARegisters = record
+  ISR,
+  IFCR: longword;
+  Channel: array[0..7] of TDMAChannel;
+ end;
+
+ TRCCRegisters = record
+  CR,
+  CFGR,
+  CIR,
+  APB2RSTR,
+  APB1RSTR,
+  AHBENR,
+  APB2ENR,
+  APB1ENR,
+  BDCR,
+  CSR: longword;
+ end;
+
+ TCRCRegisters = record
+  DR: longword;
+  IDR: byte; res1: word; res2: byte;
+  CR: byte;
+ end;
+
+ TFSMCRegisters = record
+  nothingyet: byte;
+ end;
+
+ TFlashRegisters = record
+  ACR,
+  KEYR,
+  OPTKEYR,
+  SR,
+  CR,
+  AR,
+  res,
+  OBR,
+  WRPR: longword;
+ end;
+
+ TNVICRegisters = record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of longword;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  VTOR,                             {!< Vector Table Offset Register                             }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+  SHCSR,                            {!< System Handler Control and State Register                }
+  CFSR,                             {!< Configurable Fault Status Register                       }
+  HFSR,                             {!< Hard Fault Status Register                               }
+  DFSR,                             {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                              }
+  BFAR,                             {!< Bus Fault Address Register                               }
+  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: longword;
+ end;
+
+{$ALIGN 2}
+var
+ { Timers }
+ Timer1: TTimerRegisters 	absolute (APB2Base+$2C00);
+ Timer2: TTimerRegisters 	absolute (APB1Base+$0000);
+ Timer3: TTimerRegisters 	absolute (APB1Base+$0400);
+ Timer4: TTimerRegisters 	absolute (APB1Base+$0800);
+ Timer5: TTimerRegisters 	absolute (APB1Base+$0C00);
+ Timer6: TTimerRegisters 	absolute (APB1Base+$1000);
+ Timer7: TTimerRegisters 	absolute (APB1Base+$1400);
+ Timer8: TTimerRegisters 	absolute (APB2Base+$3400);
+
+ { RTC }
+ RTC: TRTCRegisters 			absolute (APB1Base+$2800);
+
+ { WDG }
+ WWDG: TWWDGRegisters 		absolute (APB1Base+$2C00);
+ IWDG: TIWDGRegisters 		absolute (APB1Base+$3000);
+
+ { SPI }
+ SPI1: TSPIRegisters			absolute (APB2Base+$3000);
+ SPI2: TSPIRegisters			absolute (APB1Base+$3800);
+ SPI3: TSPIRegisters			absolute (APB1Base+$3C00);
+
+ { USART/UART }
+ USART1: TUSARTRegisters	absolute (APB2Base+$3800);
+ USART2: TUSARTRegisters	absolute (APB1Base+$4400);
+ USART3: TUSARTRegisters	absolute (APB1Base+$4800);
+ UART4: TUSARTRegisters		absolute (APB1Base+$4C00);
+ UART5: TUSARTRegisters		absolute (APB1Base+$5000);
+
+ { I2C }
+ I2C1: TI2CRegisters			absolute (APB1Base+$5400);
+ I2C2: TI2CRegisters			absolute (APB1Base+$5800);
+
+ { USB }
+ USB: TUSBRegisters			absolute (APB1Base+$5C00);
+ USBMem: TUSBMem                        absolute (APB1Base+$6000);
+
+ { CAN }
+ CAN: TCANRegisters			absolute (APB1Base+$6800);
+
+ { BKP }
+ BKP: TBKPRegisters			absolute (APB1Base+$6C00);
+
+ { PWR }
+ PWR: TPwrRegisters			absolute (APB1Base+$7000);
+
+ { DAC }
+ DAC: TDACRegisters			absolute (APB1Base+$7400);
+
+ { GPIO }
+ AFIO: TAFIORegisters		absolute (APB2Base+$0);
+ EXTI: TEXTIRegisters		absolute (APB2Base+$0400);
+
+ PortA: TPortRegisters		absolute (APB2Base+$0800);
+ PortB: TPortRegisters		absolute (APB2Base+$0C00);
+ PortC: TPortRegisters		absolute (APB2Base+$1000);
+ PortD: TPortRegisters		absolute (APB2Base+$1400);
+ PortE: TPortRegisters		absolute (APB2Base+$1800);
+ PortF: TPortRegisters		absolute (APB2Base+$1C00);
+ PortG: TPortRegisters		absolute (APB2Base+$2000);
+
+ { ADC }
+ ADC1: TADCRegisters			absolute (APB2Base+$2400);
+ ADC2: TADCRegisters			absolute (APB2Base+$2800);
+ ADC3: TADCRegisters			absolute (APB2Base+$3C00);
+
+ { SDIO }
+ SDIO: TSDIORegisters		absolute (APB2Base+$8000);
+
+ { DMA }
+ DMA1: TDMARegisters			absolute (AHBBase+$0000);
+ DMA2: TDMARegisters			absolute (AHBBase+$0400);
+
+ { RCC }
+ RCC: TRCCRegisters			absolute (AHBBase+$1000);
+
+ { Flash }
+ Flash: TFlashRegisters		absolute (AHBBase+$2000);
+
+ { CRC }
+ CRC: TCRCRegisters			absolute (AHBBase+$3000);
+
+ { SCB }
+ SCB: TSCBRegisters        absolute (SCS_BASE+$0D00);
+
+ { SysTick }
+ SysTick: TSysTickRegisters   absolute (SCS_BASE+$0010);
+
+ { NVIC }
+ NVIC: TNVICRegisters      absolute (SCS_BASE+$0100);
+
+implementation
+
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
+procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
+procedure Tamper_interrupt; external name 'Tamper_interrupt';
+procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
+procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
+procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
+procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
+procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
+procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
+procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
+procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
+procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
+procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
+procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
+procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
+procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
+procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
+procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
+procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
+procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
+procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
+procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
+procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
+procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
+procedure TIM1_Break_TIM9_global_interrupt; external name 'TIM1_Break_TIM9_global_interrupt';
+procedure TIM1_Update_TIM10_global_interrupt; external name 'TIM1_Update_TIM10_global_interrupt';
+procedure TIM1_Trigger_and_Commutation_TIM11_global_interrupts; external name 'TIM1_Trigger_and_Commutation_TIM11_global_interrupts';
+procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
+procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
+procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
+procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
+procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
+procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
+procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
+procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
+procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
+procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
+procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
+procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
+procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
+procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
+procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
+procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
+procedure TIM8_Break_TIM12_global_interrupt; external name 'TIM8_Break_TIM12_global_interrupt';
+procedure TIM8_Update_TIM13_global_interrupt; external name 'TIM8_Update_TIM13_global_interrupt';
+procedure TIM8_Trigger_and_Commutation_TIM14_global_interrupts; external name 'TIM8_Trigger_and_Commutation_TIM14_global_interrupts';
+procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
+procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
+procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
+procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
+procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
+procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
+procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
+procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
+procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
+procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
+procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
+procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
+procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
+procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
+
+{$i cortexm3_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+   .section ".init.interrupt_vectors"
+interrupt_vectors:
+   .long _stack_top
+   .long Startup
+   .long NMI_interrupt
+   .long Hardfault_interrupt
+   .long MemManage_interrupt
+   .long BusFault_interrupt
+   .long UsageFault_interrupt
+   .long 0
+   .long 0
+   .long 0
+   .long 0
+   .long SWI_interrupt
+   .long DebugMonitor_interrupt
+   .long 0
+   .long PendingSV_interrupt
+   .long SysTick_interrupt
+   
+   .long Window_watchdog_interrupt
+   .long PVD_through_EXTI_Line_detection_interrupt
+   .long Tamper_interrupt
+   .long RTC_global_interrupt
+   .long Flash_global_interrupt
+   .long RCC_global_interrupt
+   .long EXTI_Line0_interrupt
+   .long EXTI_Line1_interrupt
+   .long EXTI_Line2_interrupt
+   .long EXTI_Line3_interrupt
+   .long EXTI_Line4_interrupt
+   .long DMA1_Channel1_global_interrupt
+   .long DMA1_Channel2_global_interrupt
+   .long DMA1_Channel3_global_interrupt
+   .long DMA1_Channel4_global_interrupt
+   .long DMA1_Channel5_global_interrupt
+   .long DMA1_Channel6_global_interrupt
+   .long DMA1_Channel7_global_interrupt
+   .long ADC1_and_ADC2_global_interrupt
+   .long USB_High_Priority_or_CAN_TX_interrupts
+   .long USB_Low_Priority_or_CAN_RX0_interrupts
+   .long CAN_RX1_interrupt
+   .long CAN_SCE_interrupt
+   .long EXTI_Line9_5_interrupts
+   .long TIM1_Break_TIM9_global_interrupt
+   .long TIM1_Update_TIM10_global_interrupt
+   .long TIM1_Trigger_and_Commutation_TIM11_global_interrupts
+   .long TIM1_Capture_Compare_interrupt
+   .long TIM2_global_interrupt
+   .long TIM3_global_interrupt
+   .long TIM4_global_interrupt
+   .long I2C1_event_interrupt
+   .long I2C1_error_interrupt
+   .long I2C2_event_interrupt
+   .long I2C2_error_interrupt
+   .long SPI1_global_interrupt
+   .long SPI2_global_interrupt
+   .long USART1_global_interrupt
+   .long USART2_global_interrupt
+   .long USART3_global_interrupt
+   .long EXTI_Line15_10_interrupts
+   .long RTC_alarm_through_EXTI_line_interrupt
+   .long USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .long TIM8_Break_TIM12_global_interrupt
+   .long TIM8_Update_TIM13_global_interrupt
+   .long TIM8_Trigger_and_Commutation_TIM14_global_interrupts
+   .long TIM8_Capture_Compare_interrupt
+   .long ADC3_global_interrupt
+   .long FSMC_global_interrupt
+   .long SDIO_global_interrupt
+   .long TIM5_global_interrupt
+   .long SPI3_global_interrupt
+   .long UART4_global_interrupt
+   .long UART5_global_interrupt
+   .long TIM6_global_interrupt
+   .long TIM7_global_interrupt
+   .long DMA2_Channel1_global_interrupt
+   .long DMA2_Channel2_global_interrupt
+   .long DMA2_Channel3_global_interrupt
+   .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+   
+   
+   .weak NMI_interrupt
+   .weak Hardfault_interrupt
+   .weak MemManage_interrupt
+   .weak BusFault_interrupt
+   .weak UsageFault_interrupt
+   .weak SWI_interrupt
+   .weak DebugMonitor_interrupt
+   .weak PendingSV_interrupt
+   .weak SysTick_interrupt
+   
+   .weak Window_watchdog_interrupt
+   .weak PVD_through_EXTI_Line_detection_interrupt
+   .weak Tamper_interrupt
+   .weak RTC_global_interrupt
+   .weak Flash_global_interrupt
+   .weak RCC_global_interrupt
+   .weak EXTI_Line0_interrupt
+   .weak EXTI_Line1_interrupt
+   .weak EXTI_Line2_interrupt
+   .weak EXTI_Line3_interrupt
+   .weak EXTI_Line4_interrupt
+   .weak DMA1_Channel1_global_interrupt
+   .weak DMA1_Channel2_global_interrupt
+   .weak DMA1_Channel3_global_interrupt
+   .weak DMA1_Channel4_global_interrupt
+   .weak DMA1_Channel5_global_interrupt
+   .weak DMA1_Channel6_global_interrupt
+   .weak DMA1_Channel7_global_interrupt
+   .weak ADC1_and_ADC2_global_interrupt
+   .weak USB_High_Priority_or_CAN_TX_interrupts
+   .weak USB_Low_Priority_or_CAN_RX0_interrupts
+   .weak CAN_RX1_interrupt
+   .weak CAN_SCE_interrupt
+   .weak EXTI_Line9_5_interrupts
+   .weak TIM1_Break_TIM9_global_interrupt
+   .weak TIM1_Update_TIM10_global_interrupt
+   .weak TIM1_Trigger_and_Commutation_TIM11_global_interrupts
+   .weak TIM1_Capture_Compare_interrupt
+   .weak TIM2_global_interrupt
+   .weak TIM3_global_interrupt
+   .weak TIM4_global_interrupt
+   .weak I2C1_event_interrupt
+   .weak I2C1_error_interrupt
+   .weak I2C2_event_interrupt
+   .weak I2C2_error_interrupt
+   .weak SPI1_global_interrupt
+   .weak SPI2_global_interrupt
+   .weak USART1_global_interrupt
+   .weak USART2_global_interrupt
+   .weak USART3_global_interrupt
+   .weak EXTI_Line15_10_interrupts
+   .weak RTC_alarm_through_EXTI_line_interrupt
+   .weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
+   .weak TIM8_Break_TIM12_global_interrupt
+   .weak TIM8_Update_TIM13_global_interrupt
+   .weak TIM8_Trigger_and_Commutation_TIM14_global_interrupts
+   .weak TIM8_Capture_Compare_interrupt
+   .weak ADC3_global_interrupt
+   .weak FSMC_global_interrupt
+   .weak SDIO_global_interrupt
+   .weak TIM5_global_interrupt
+   .weak SPI3_global_interrupt
+   .weak UART4_global_interrupt
+   .weak UART5_global_interrupt
+   .weak TIM6_global_interrupt
+   .weak TIM7_global_interrupt
+   .weak DMA2_Channel1_global_interrupt
+   .weak DMA2_Channel2_global_interrupt
+   .weak DMA2_Channel3_global_interrupt
+   .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
+
+   
+   .set NMI_interrupt, Startup
+   .set Hardfault_interrupt, Startup
+   .set MemManage_interrupt, Startup
+   .set BusFault_interrupt, Startup
+   .set UsageFault_interrupt, Startup
+   .set SWI_interrupt, Startup
+   .set DebugMonitor_interrupt, Startup
+   .set PendingSV_interrupt, Startup
+   .set SysTick_interrupt, Startup
+
+   .set Window_watchdog_interrupt, Startup
+   .set PVD_through_EXTI_Line_detection_interrupt, Startup
+   .set Tamper_interrupt, Startup
+   .set RTC_global_interrupt, Startup
+   .set Flash_global_interrupt, Startup
+   .set RCC_global_interrupt, Startup
+   .set EXTI_Line0_interrupt, Startup
+   .set EXTI_Line1_interrupt, Startup
+   .set EXTI_Line2_interrupt, Startup
+   .set EXTI_Line3_interrupt, Startup
+   .set EXTI_Line4_interrupt, Startup
+   .set DMA1_Channel1_global_interrupt, Startup
+   .set DMA1_Channel2_global_interrupt, Startup
+   .set DMA1_Channel3_global_interrupt, Startup
+   .set DMA1_Channel4_global_interrupt, Startup
+   .set DMA1_Channel5_global_interrupt, Startup
+   .set DMA1_Channel6_global_interrupt, Startup
+   .set DMA1_Channel7_global_interrupt, Startup
+   .set ADC1_and_ADC2_global_interrupt, Startup
+   .set USB_High_Priority_or_CAN_TX_interrupts, Startup
+   .set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
+   .set CAN_RX1_interrupt, Startup
+   .set CAN_SCE_interrupt, Startup
+   .set EXTI_Line9_5_interrupts, Startup
+   .set TIM1_Break_TIM9_global_interrupt, Startup
+   .set TIM1_Update_TIM10_global_interrupt, Startup
+   .set TIM1_Trigger_and_Commutation_TIM11_global_interrupts, Startup
+   .set TIM1_Capture_Compare_interrupt, Startup
+   .set TIM2_global_interrupt, Startup
+   .set TIM3_global_interrupt, Startup
+   .set TIM4_global_interrupt, Startup
+   .set I2C1_event_interrupt, Startup
+   .set I2C1_error_interrupt, Startup
+   .set I2C2_event_interrupt, Startup
+   .set I2C2_error_interrupt, Startup
+   .set SPI1_global_interrupt, Startup
+   .set SPI2_global_interrupt, Startup
+   .set USART1_global_interrupt, Startup
+   .set USART2_global_interrupt, Startup
+   .set USART3_global_interrupt, Startup
+   .set EXTI_Line15_10_interrupts, Startup
+   .set RTC_alarm_through_EXTI_line_interrupt, Startup
+   .set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
+   .set TIM8_Break_TIM12_global_interrupt, Startup
+   .set TIM8_Update_TIM13_global_interrupt, Startup
+   .set TIM8_Trigger_and_Commutation_TIM14_global_interrupts, Startup
+   .set TIM8_Capture_Compare_interrupt, Startup
+   .set ADC3_global_interrupt, Startup
+   .set FSMC_global_interrupt, Startup
+   .set SDIO_global_interrupt, Startup
+   .set TIM5_global_interrupt, Startup
+   .set SPI3_global_interrupt, Startup
+   .set UART4_global_interrupt, Startup
+   .set UART5_global_interrupt, Startup
+   .set TIM6_global_interrupt, Startup
+   .set TIM7_global_interrupt, Startup
+   .set DMA2_Channel1_global_interrupt, Startup
+   .set DMA2_Channel2_global_interrupt, Startup
+   .set DMA2_Channel3_global_interrupt, Startup
+   .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
+   
+   .text
+end;
+
+end.

rtl/embedded/consoleio.pp

@@ -17,28 +17,130 @@ Unit consoleio;
 
   interface
 
+    type
+      TWriteCharFunc = function(ACh: char; AUserData: pointer): boolean;
+      TReadCharFunc = function(var ACh: char; AUserData: pointer): boolean;
+
+    procedure OpenIO(var f: Text; AWrite: TWriteCharFunc; ARead: TReadCharFunc; AMode:longint; AUserData: pointer);
+
   implementation
 
+    {$i textrec.inc}
+
+    type
+      PUserData = ^TUserData;
+      TUserData = record
+        WriteChar: TWriteCharFunc;
+        ReadChar: TReadCharFunc;
+        UserData: Pointer;
+      end;
+
+    function EmptyWrite(ACh: char; AUserData: pointer): boolean;
+      begin
+        result:=true;
+      end;
+
+    function EmptyRead(var ACh: char; AUserData: pointer): boolean;
+      begin
+        result:=true;
+        ACh:=#0;
+      end;
+
+    procedure Console_Close(var t:TextRec);
+      begin
+      end;
+
+    function ReadData(Func: TReadCharFunc; UserData: pointer; Buffer: pchar; count: longint): longint;
+      var
+        c: char;
+        got_linechar: boolean;
+      begin
+        result:=0;
+        got_linechar:=false;
+        while (result < count) and (not got_linechar) do
+          begin
+            if Func(c, UserData) then
+              begin
+                if c = #10 then
+                  got_linechar:=true;
+                buffer^:=c;
+                inc(buffer);
+                inc(result);
+              end;
+          end;
+      end;
+
+    Procedure Console_Read(var t:TextRec);
+      var
+        userdata: PUserData;
+      begin
+        userdata:[email protected][1];
+        InOutRes:=0;
+        t.bufend:=ReadData(userdata^.ReadChar,userdata^.UserData,pchar(t.bufptr),t.bufsize);
+        t.bufpos:=0;
+      end;
+
+    Procedure Console_Write(var t:TextRec);
+      var
+        userdata: PUserData;
+        p: pchar;
+        i: longint;
+      begin
+        if t.BufPos=0 then exit;
+        userdata:[email protected][1];
+        i := 0;
+        p := pchar(t.bufptr);
+        while i < t.bufpos do
+          begin
+            if not userdata^.WriteChar(p^, userdata^.UserData) then
+              break;
+            inc(p);
+            inc(i);
+          end;
+        if i<>t.BufPos then
+          InOutRes:=101
+        else
+          InOutRes:=0;
+        t.BufPos:=0;
+      end;
+
+    procedure OpenIO(var f: Text; AWrite: TWriteCharFunc; ARead: TReadCharFunc; AMode:longint; AUserData: pointer);
+      var
+        userdata: PUserData;
+      begin
+        Assign(f,'');
+        userdata:=@TextRec(f).UserData[1];
+        TextRec(f).Mode:=AMode;
+        case AMode of
+          fmInput: TextRec(f).Handle:=StdInputHandle;
+          fmOutput: TextRec(f).Handle:=StdOutputHandle;
+        end;
+        TextRec(f).CloseFunc:=@Console_Close;
+        TextRec(f).FlushFunc:=nil;
+        case AMode of
+          fmInput: TextRec(f).InOutFunc:=@Console_Read;
+          fmOutput: 
+            begin
+              TextRec(f).InOutFunc:=@Console_Write;
+              TextRec(f).FlushFunc:=@Console_Write;
+            end;
+        end;
+        userdata^.WriteChar := AWrite;
+        userdata^.ReadChar := ARead;
+        userdata^.UserData := AUserData;
+      end;
+
     procedure SysInitStdIO;
       begin
-        // OpenStdIO(Input,fmInput,0);
-        // OpenStdIO(Output,fmOutput,0);
-        // OpenStdIO(ErrOutput,fmOutput,0);
-        // OpenStdIO(StdOut,fmOutput,0);
-        // OpenStdIO(StdErr,fmOutput,0);
+        OpenIO(Input, @EmptyWrite, @EmptyRead, fmInput, nil);
+        OpenIO(Output, @EmptyWrite, @EmptyRead, fmOutput, nil);
+        OpenIO(ErrOutput, @EmptyWrite, @EmptyRead, fmOutput, nil);
+        OpenIO(StdOut, @EmptyWrite, @EmptyRead, fmOutput, nil);
+        OpenIO(StdErr, @EmptyWrite, @EmptyRead, fmOutput, nil);
       end;
 
    procedure SysFlushStdIO;
      begin
-       { Make sure that all output is written to the redirected file }
-{!!!!!!!!       if Textrec(Output).Mode=fmOutput then
-         Flush(Output);
-       if Textrec(ErrOutput).Mode=fmOutput then
-         Flush(ErrOutput);
-       if Textrec(stdout).Mode=fmOutput then
-         Flush(stdout);
-       if Textrec(StdErr).Mode=fmOutput then
-         Flush(StdErr);  }
      end;
 
 var

rtl/embedded/heapmgr.pp

@@ -2,7 +2,7 @@
     This file is part of the Free Pascal run time library.
     Copyright (c) 2011 by the Free Pascal development team.
 
-    Heap manager for the FPC embedded target
+    Tiny heap manager for the FPC embedded target
 
     See the file COPYING.FPC, included in this distribution,
     for details about the copyright.
@@ -15,52 +15,234 @@
 {$mode objfpc}
 Unit heapmgr;
 
-interface
-
-implementation
-
-  var
-    Memorymanager: TMemoryManager;external name 'FPC_SYSTEM_MEMORYMANAGER';
-
-  Procedure HandleError (Errno : longint);external name 'FPC_HANDLEERROR';
-
-  {*****************************************************************************
-        OS Memory allocation / deallocation
-   ****************************************************************************}
-  function SysOSAlloc(size: ptruint): pointer;
-  begin
-    result:=nil; // pointer($02000000);
-  end;
-
-
-  procedure SysOSFree(p: pointer; size: ptruint);
-  begin
-  end;
-
-  {$define FPC_IN_HEAPMGR}
-  {$i heap.inc}
-
-  const
-    MyMemoryManager: TMemoryManager = (
-      NeedLock: false;  // Obsolete
-      GetMem: @SysGetMem;
-      FreeMem: @SysFreeMem;
-      FreeMemSize: @SysFreeMemSize;
-      AllocMem: @SysAllocMem;
-      ReAllocMem: @SysReAllocMem;
-      MemSize: @SysMemSize;
-      InitThread: nil;
-      DoneThread: nil;
-      RelocateHeap: nil;
-      GetHeapStatus: @SysGetHeapStatus;
-      GetFPCHeapStatus: @SysGetFPCHeapStatus;
-    );
+  interface
+
+    procedure RegisterHeapBlock(AAddress: pointer; ASize: ptruint);
+
+  implementation
+
+    const
+      MinBlock = 16;
+
+    type
+      PHeapBlock = ^THeapBlock;
+      THeapBlock = record
+        Size: ptruint;
+        Next: PHeapBlock;
+        EndAddr: pointer;
+      end;
+
+    var
+      Blocks: PHeapBlock = nil;
+
+    procedure InternalFreeMem(Addr: Pointer; Size: ptruint); forward;
+
+    function FindSize(p: pointer): ptruint;
+      begin
+        FindSize := PPtrUInt(p)[-1];
+      end;
+
+    function SysGetMem(Size: ptruint): pointer;
+      var
+        p, prev: PHeapBlock;
+        AllocSize, RestSize: ptruint;
+      begin
+        AllocSize := align(size+sizeof(ptruint), sizeof(pointer));
+
+        p := Blocks;
+        prev := nil;
+        while assigned(p) and (p^.Size < AllocSize) do
+          begin
+            prev := p;
+            p := p^.Next;
+          end;
+
+        if assigned(p) then
+          begin
+            result := @pptruint(p)[1];
+
+            if p^.Size-AllocSize >= MinBlock then
+              RestSize := p^.Size-AllocSize
+            else
+              begin
+                AllocSize := p^.Size;
+                RestSize := 0;
+              end;
+
+            if prev = nil then
+              Blocks := p^.Next
+            else
+              prev^.next := p^.next;
+
+            pptruint(p)^ := size;
+
+            InternalFreemem(pointer(ptruint(p)+AllocSize), RestSize);
+          end
+        else
+          Result := nil;
+      end;
+
+    function GetAlignedMem(Size, Alignment: ptruint): pointer;
+      var
+        mem: Pointer;
+        memp: ptruint;
+      begin
+        if alignment <= sizeof(pointer) then
+          result := GetMem(size)
+        else
+          begin
+            mem := GetMem(Size+Alignment-1);
+            memp := align(ptruint(mem), Alignment);
+            InternalFreemem(mem, ptruint(memp)-ptruint(mem));
+            result := pointer(memp);
+          end;
+      end;
+
+    procedure InternalFreeMem(Addr: Pointer; Size: ptruint);
+      var 
+        b, p, prev: PHeapBlock;
+        concatenated: boolean;
+      begin
+        concatenated := true;
+        while concatenated do
+          begin
+            concatenated := false;
+            b := addr;
+
+            b^.Next := Blocks;
+            b^.Size := Size;
+            b^.EndAddr := pointer(ptruint(addr)+size);
+
+            if Blocks = nil then
+              Blocks := b
+            else
+              begin
+                p := Blocks;
+                prev := nil;
+
+                while assigned(p) do
+                  begin
+                    if p^.EndAddr = addr then
+                      begin
+                        addr:=p;
+                        size:=p^.size+size;
+                        if prev = nil then
+                          blocks:=p^.next
+                        else
+                          prev^.next:=p^.next;
+                        concatenated:=true;
+                        break;
+                      end
+                    else if p = b^.EndAddr then
+                      begin
+                        size:=p^.size+size;
+                        if prev = nil then
+                          blocks:=p^.next
+                        else
+                          prev^.next:=p^.next;
+                        concatenated:=true;
+                        break;
+                      end;
+                    
+                    prev := p;
+                    p := p^.next;
+                  end;
+
+                if not concatenated then
+                  begin
+                    p := Blocks;
+                    prev := nil;
+
+                    while assigned(p) and (p^.Size < size) do
+                      begin
+                        prev := p;
+                        p := p^.Next;
+                      end;
+
+                    if assigned(prev) then
+                      begin
+                        b^.Next := p;
+                        prev^.Next := b;
+                      end
+                    else
+                      Blocks := b;
+                  end;
+              end;
+          end;
+      end;
+
+    function SysFreeMem(Addr: Pointer): ptruint;
+      var
+        sz: ptruint;
+      begin
+        sz := Align(FindSize(addr)+SizeOf(ptruint), sizeof(pointer));
+
+        InternalFreeMem(@pptruint(addr)[-1], sz);
+        
+        result := sz;
+      end;
+
+    function SysFreeMemSize(Addr: Pointer; Size: Ptruint): ptruint;
+      begin
+        result := SysFreeMem(addr);
+      end;
+
+    function SysMemSize(p: pointer): ptruint;
+      begin
+        result := findsize(p);
+      end;
+
+    function SysAllocMem(size: ptruint): pointer;
+      begin
+        result := SysGetMem(size);
+        if result<>nil then
+          FillChar(result^,SysMemSize(result),0);
+      end;
+
+    function SysReAllocMem(var p: pointer; size: ptruint):pointer;
+      var
+        sz: ptruint;
+      begin
+        result := AllocMem(size);
+        if result <> nil then
+          begin
+            if p <> nil then
+              begin
+                sz := FindSize(p);
+                if sz > size then
+                  sz := size;
+                move(pbyte(p)^, pbyte(result)^, sz);
+              end;
+          end;
+        SysFreeMem(p);
+        p := result;
+      end;
+
+    procedure RegisterHeapBlock(AAddress: pointer; ASize: ptruint);
+      begin
+        FreeMem(AAddress, ASize);
+      end;
+
+    const
+      MyMemoryManager: TMemoryManager = (
+        NeedLock: false;  // Obsolete
+        GetMem: @SysGetMem;
+        FreeMem: @SysFreeMem;
+        FreeMemSize: @SysFreeMemSize;
+        AllocMem: @SysAllocMem;
+        ReAllocMem: @SysReAllocMem;
+        MemSize: @SysMemSize;
+        InitThread: nil;
+        DoneThread: nil;
+        RelocateHeap: nil;
+        GetHeapStatus: nil;
+        GetFPCHeapStatus: nil;
+      );
 
 
 initialization
   SetMemoryManager(MyMemoryManager);
-  InitHeap;
 finalization
-  FinalizeHeap;
+  //FinalizeHeap;
 end.
 

rtl/embedded/system.pp

@@ -67,7 +67,7 @@ const
   CtrlZMarksEOF: boolean = false; (* #26 not considered as end of file *)
 
   sLineBreak = LineEnding;
-  DefaultTextLineBreakStyle : TTextLineBreakStyle = tlbsLF;
+  DefaultTextLineBreakStyle : TTextLineBreakStyle = tlbsCrLF;
 {$endif FPC_HAS_FEATURE_TEXTIO}
 
 {$ifdef FPC_HAS_FEATURE_COMMANDARGS}