Merged revisions 9721 via svnmerge from

http://svn.freepascal.org/svn/fpc/trunk

........
  r9721 | tom_at_work | 2008-01-12 14:47:55 +0100 (Sa, 12 Jan 2008) | 1 line
  
  * removed code which splits "unaligned" 8 byte stores/loads into two 4 bytes stores/loads on ppc64. The processor manuals and extensive testing showed that PPC970+ class processors have hardware assisted handling of unaligned memory accesses, which results in 8 byte memory accesses to be always faster than 4 byte ones
........

git-svn-id: branches/fixes_2_2@9722 -

compiler/powerpc64/cgcpu.pas

@@ -745,12 +745,15 @@ begin
 
   if not (fromsize in [OS_8, OS_S8, OS_16, OS_S16, OS_32, OS_S32, OS_64, OS_S64]) then
     internalerror(2002090904);
-  ref2 := ref;
-  fixref(list, ref2);
+
   { the caller is expected to have adjusted the reference already
    in this case }
   if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
     fromsize := tosize;
+
+  ref2 := ref;
+  fixref(list, ref2);
+
   op := loadinstr[fromsize, ref2.index <> NR_NO, false];
   { there is no LWAU instruction, simulate using ADDI and LWA }
   if (op = A_NOP) then begin