Merge branch source:main into main

compiler/aarch64/aasmcpu.pas

@@ -1147,7 +1147,8 @@ implementation
            A_UMULL,
            A_UMULH,
            A_UXTB,
-           A_UXTH:
+           A_UXTH,
+           A_MRS:
              if opnr=0 then
                result:=operand_write
              else

compiler/aarch64/ccpuinnr.inc

@@ -0,0 +1,17 @@
+{
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+  in_a64_fcadd  = in_cpu_first,
+  in_a64_yield = in_cpu_first+1
+

compiler/aarch64/ncpuinl.pas

@@ -51,6 +51,9 @@ interface
         procedure second_fma; override;
         procedure second_prefetch; override;
         procedure second_minmax; override;
+        procedure pass_generate_code_cpu; override;
+        function pass_typecheck_cpu: tnode; override;
+        function first_cpu: tnode; override;
       private
         procedure load_fpu_location;
       end;
@@ -71,6 +74,44 @@ implementation
                               taarch64inlinenode
 *****************************************************************************}
 
+     function taarch64inlinenode.pass_typecheck_cpu: tnode;
+       begin
+         Result:=nil;
+         case inlinenumber of
+           in_a64_yield:
+             resultdef:=voidtype;
+           else
+             result:=inherited;
+         end;
+       end;
+
+
+    function taarch64inlinenode.first_cpu : tnode;
+      begin
+        Result:=nil;
+        case inlinenumber of
+          in_a64_yield:
+            begin
+              expectloc:=LOC_VOID;
+              resultdef:=voidtype;
+            end;
+          else
+            Result:=inherited first_cpu;
+        end;
+      end;
+
+
+     procedure taarch64inlinenode.pass_generate_code_cpu;
+       begin
+         case inlinenumber of
+           in_a64_yield:
+             current_asmdata.CurrAsmList.concat(taicpu.op_none(A_YIELD));
+           else
+             inherited pass_generate_code_cpu;
+         end;
+       end;
+
+
     procedure taarch64inlinenode.load_fpu_location;
       begin
         secondpass(left);

compiler/arm/ccpuinnr.inc

@@ -0,0 +1,16 @@
+{
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+  in_arm_yield  = in_cpu_first
+

compiler/arm/narminl.pas

@@ -52,6 +52,10 @@ interface
         procedure second_prefetch; override;
         procedure second_abs_long; override;
         procedure second_fma; override;
+
+        function first_cpu: tnode; override;
+        procedure pass_generate_code_cpu; override;
+        function pass_typecheck_cpu: tnode; override;
       private
         procedure load_fpu_location(out singleprec: boolean);
       end;
@@ -62,7 +66,7 @@ implementation
     uses
       globtype,verbose,globals,
       procinfo,
-      cpuinfo, defutil,symdef,aasmdata,aasmcpu,
+      compinnr,cpuinfo,defutil,symdef,aasmdata,aasmcpu,
       cgbase,cgutils,pass_1,pass_2,
       cpubase,ncgutil,cgobj,cgcpu, hlcgobj,
       nutils,ncal;
@@ -71,6 +75,44 @@ implementation
                               tarminlinenode
 *****************************************************************************}
 
+     function tarminlinenode.pass_typecheck_cpu: tnode;
+       begin
+         Result:=nil;
+         case inlinenumber of
+           in_arm_yield:
+             resultdef:=voidtype;
+           else
+             result:=inherited;
+         end;
+       end;
+
+
+    function tarminlinenode.first_cpu : tnode;
+      begin
+        Result:=nil;
+        case inlinenumber of
+          in_arm_yield:
+            begin
+              expectloc:=LOC_VOID;
+              resultdef:=voidtype;
+            end;
+          else
+            Result:=inherited first_cpu;
+        end;
+      end;
+
+
+     procedure tarminlinenode.pass_generate_code_cpu;
+       begin
+         case inlinenumber of
+           in_arm_yield:
+             current_asmdata.CurrAsmList.concat(taicpu.op_none(A_YIELD));
+           else
+             inherited pass_generate_code_cpu;
+         end;
+       end;
+
+
     procedure tarminlinenode.load_fpu_location(out singleprec: boolean);
       begin
         secondpass(left);

compiler/compinnr.pas

@@ -218,6 +218,18 @@ type
 {$if defined(WASM32)}
      ,
      {$i ccpuinnr.inc}
+{$endif}
+{$if defined(ARM)}
+     ,
+     {$i ccpuinnr.inc}
+{$endif}
+{$if defined(AARCH64)}
+     ,
+     {$i ccpuinnr.inc}
+{$endif}
+{$if defined(RISCV)}
+     ,
+     {$i riscv/ccpuinnr.inc}
 {$endif}
    );
 

compiler/i8086/n8086inl.pas

@@ -29,9 +29,6 @@ interface
        nx86inl,node;
 
     type
-
-       { ti8086inlinenode }
-
        ti8086inlinenode = class(tx86inlinenode)
          function pass_typecheck_cpu: tnode; override;
          procedure pass_generate_code_cpu;override;

compiler/riscv/ccpuinnr.inc

@@ -0,0 +1,23 @@
+{
+    Copyright (c) 2025 by the Free Pascal development team
+
+    RISCV specific compiler proc./intrinsic numbers
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+
+  in_riscv_pause  = in_cpu_first

compiler/riscv/cpubase.pas

@@ -179,6 +179,9 @@ uses
 //        A_FCVT_D_S,A_FCVT_S_D,
 //        A_FCVT_W_D,A_FCVT_WU_D,A_FCVT_D_W,A_FCVT_D_WU,
 
+        { Zihintpause }
+        A_PAUSE,
+
         { Machine mode }
         A_MRET,A_HRET,A_SRET,A_URET,
         A_WFI,

compiler/riscv/itcpugas.pas

@@ -163,6 +163,9 @@ unit itcpugas;
         'flq','fsq',
         'fmax.q','fmax.q',
 
+        { Zihintpause }
+        'pause',
+
         { Machine mode }
         'mret','hret','sret','uret',
         'wfi',

compiler/riscv/nrvinl.pas

@@ -51,6 +51,10 @@ interface
 
         procedure second_fma; override;
         procedure second_minmax; override;
+
+        function pass_typecheck_cpu: tnode; override;
+        function first_cpu: tnode; override;
+        procedure pass_generate_code_cpu; override;
       protected
         procedure load_fpu_location;
       end;
@@ -74,6 +78,44 @@ implementation
                               trvinlinenode
 *****************************************************************************}
 
+     function trvinlinenode.pass_typecheck_cpu: tnode;
+       begin
+         Result:=nil;
+         case inlinenumber of
+           in_riscv_pause:
+             resultdef:=voidtype;
+           else
+             result:=inherited;
+         end;
+       end;
+
+
+    function trvinlinenode.first_cpu : tnode;
+      begin
+        Result:=nil;
+        case inlinenumber of
+          in_riscv_pause:
+            begin
+              expectloc:=LOC_VOID;
+              resultdef:=voidtype;
+            end;
+          else
+            Result:=inherited first_cpu;
+        end;
+      end;
+
+
+     procedure trvinlinenode.pass_generate_code_cpu;
+       begin
+         case inlinenumber of
+           in_riscv_pause:
+             current_asmdata.CurrAsmList.concat(taicpu.op_none(A_PAUSE));
+           else
+             inherited pass_generate_code_cpu;
+         end;
+       end;
+
+
      function trvinlinenode.first_sqrt_real : tnode;
        begin
          if (current_settings.fputype >= fpu_fd) then

compiler/x86/cx86innr.inc

@@ -26,6 +26,7 @@
   in_x86_get_es   = in_cpu_first+11,
   in_x86_get_fs   = in_cpu_first+12,
   in_x86_get_gs   = in_cpu_first+13,
+  in_x86_pause    = in_cpu_first+14,
 
   { include mm inline routines }
   {$I cx86mminnr.inc}

compiler/x86/nx86inl.pas

@@ -140,6 +140,7 @@ implementation
                CheckParameters(2);
                resultdef:=voidtype;
              end;
+           in_x86_pause,
            in_x86_cli,
            in_x86_sti:
              resultdef:=voidtype;
@@ -179,6 +180,7 @@ implementation
            in_x86_outportb,
            in_x86_outportw,
            in_x86_outportl,
+           in_x86_pause,
            in_x86_cli,
            in_x86_sti:
              expectloc:=LOC_VOID;
@@ -616,6 +618,8 @@ implementation
              current_asmdata.CurrAsmList.concat(taicpu.op_none(A_CLI));
            in_x86_sti:
              current_asmdata.CurrAsmList.concat(taicpu.op_none(A_STI));
+           in_x86_pause:
+             current_asmdata.CurrAsmList.concat(taicpu.op_none(A_PAUSE));
            in_x86_get_cs:
              get_segreg(NR_CS);
            in_x86_get_ss:

rtl/aarch64/cpuinnr.inc

@@ -14,3 +14,4 @@
  **********************************************************************}
 
 fpc_in_aarch64_fcadd = fpc_in_cpu_first+0;
+fpc_in_aarch64_yield = fpc_in_cpu_first+1;

rtl/aarch64/cpuprocs.inc

@@ -12,3 +12,5 @@
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 
  **********************************************************************}
+
+procedure fpc_aarch64_yield;[internproc:fpc_in_aarch64_yield];

rtl/arm/cpuinnr.inc

@@ -0,0 +1,16 @@
+  {
+    Defines CPU intrinsic indicies for ARM
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2021 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+fpc_in_arm_yield = fpc_in_cpu_first+0;

rtl/arm/cpuprocs.inc

@@ -0,0 +1,16 @@
+{
+    Defines CPU intrinsics for ARM
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+procedure fpc_arm_yield;[internproc:fpc_in_arm_yield];

rtl/arm/intrinsics.pp

@@ -0,0 +1,28 @@
+{
+    Provides CPU intrinsics for ARM
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2021 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+{$IFNDEF FPC_DOTTEDUNITS}
+unit intrinsics;
+{$ENDIF FPC_DOTTEDUNITS}
+
+  interface
+
+    const
+    {$i cpuinnr.inc}
+
+    {$i cpuprocs.inc}
+
+  implementation
+
+end.

rtl/darwin/Makefile

@@ -919,6 +919,9 @@ endif
 ifeq ($(ARCH),x86_64)
 CPU_UNITS=$(CPUUNIT)
 endif
+ifeq ($(ARCH),aarch64)
+CPU_UNITS=$(INTRINSICSUNIT)
+endif
 RTL=..
 INC=$(RTL)/inc
 COMMON=$(RTL)/common
@@ -2696,6 +2699,13 @@ mmx$(PPUEXT) : $(MMX_DEPS)
 	$(COMPILER) $(MMX_OPT) $<
 System.CPU.MMX$(PPUEXT) : $(NSINC)/System.CPU.MMX.pp $(MMX_DEPS)
 	$(COMPILER) $(MMX_OPT) $<
+INTRINSICS_DEPS=$(PROCINC)/intrinsics.pp \
+	 $(SYSTEMUNIT)$(PPUEXT) \
+	 $(INTRINSICS_DEPS_OS) $(INTRINSICS_DEPS_CPU)
+intrinsics$(PPUEXT) : $(INTRINSICS_DEPS)
+	$(COMPILER) $(INTRINSICS_OPT) $<
+System.Intrinsics$(PPUEXT) : $(NSINC)/System.Intrinsics.pp $(INTRINSICS_DEPS)
+	$(COMPILER) $(INTRINSICS_OPT) $<
 ifeq ($(filter -dFPC_USE_LIBC,$(FPCOPT)),)
   X86_DEPS_OS+=$(SYSCALLUNIT)$(PPUEXT)
 endif

rtl/darwin/Makefile.fpc

@@ -55,6 +55,10 @@ ifeq ($(ARCH),x86_64)
 CPU_UNITS=$(CPUUNIT)
 endif
 
+ifeq ($(ARCH),aarch64)
+CPU_UNITS=$(INTRINSICSUNIT)
+endif
+
 RTL=..
 INC=$(RTL)/inc
 COMMON=$(RTL)/common

rtl/i386/cpuh.inc

@@ -42,6 +42,7 @@ function fpc_x86_get_ds:longint;[internproc:fpc_in_x86_get_ds];
 function fpc_x86_get_es:longint;[internproc:fpc_in_x86_get_es];
 function fpc_x86_get_fs:longint;[internproc:fpc_in_x86_get_fs];
 function fpc_x86_get_gs:longint;[internproc:fpc_in_x86_get_gs];
+procedure fpc_x86_pause;[internproc:fpc_in_x86_pause];
 
 { include automatically generated procs }
 {$if not defined(VER3_2)}

rtl/i386/cpuinnr.inc

@@ -26,6 +26,7 @@
   fpc_in_x86_get_es   = fpc_in_cpu_first+11;
   fpc_in_x86_get_fs   = fpc_in_cpu_first+12;
   fpc_in_x86_get_gs   = fpc_in_cpu_first+13;
-  
+  fpc_in_x86_pause    = fpc_in_cpu_first+14;
+
   { include automatically generated numbers }
   {$i cpumminnr.inc}  

rtl/i8086/cpuinnr.inc

@@ -25,4 +25,5 @@
   fpc_in_x86_get_ds   = fpc_in_cpu_first+10;
   fpc_in_x86_get_es   = fpc_in_cpu_first+11;
   fpc_in_x86_get_fs   = fpc_in_cpu_first+12;
-  fpc_in_x86_get_gs   = fpc_in_cpu_first+13;
+  fpc_in_x86_get_gs   = fpc_in_cpu_first+13;
+  fpc_in_x86_pause    = fpc_in_cpu_first+14;

rtl/inc/Makefile.rtl

@@ -1203,6 +1203,21 @@ mmx$(PPUEXT) : $(MMX_DEPS)
 System.CPU.MMX$(PPUEXT) : $(NSINC)/System.CPU.MMX.pp $(MMX_DEPS)
 	$(COMPILER) $(MMX_OPT) $<
 
+
+#
+# Intrinsics
+#
+
+INTRINSICS_DEPS=$(PROCINC)/intrinsics.pp \
+         $(SYSTEMUNIT)$(PPUEXT) \
+         $(INTRINSICS_DEPS_OS) $(INTRINSICS_DEPS_CPU)
+
+intrinsics$(PPUEXT) : $(INTRINSICS_DEPS)
+	$(COMPILER) $(INTRINSICS_OPT) $<
+
+System.Intrinsics$(PPUEXT) : $(NSINC)/System.Intrinsics.pp $(INTRINSICS_DEPS)
+	$(COMPILER) $(INTRINSICS_OPT) $<
+
 #
 # X86
 #

rtl/linux/Makefile

@@ -957,6 +957,9 @@ CPU_UNITS=$(X86UNIT) $(PORTSUNIT) $(CPUUNIT)
 SYSINIT_UNITS=si_prc si_c si_g si_dll
 override LOADERS=abitag
 endif
+ifeq ($(ARCH),aarch64)
+CPU_UNITS=$(INTRINSICSUNIT)
+endif
 ifeq ($(ARCH),powerpc64)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_c si_g si_dll
@@ -968,10 +971,12 @@ endif
 ifeq ($(ARCH),riscv32)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 ifeq ($(ARCH),riscv64)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c si_g
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 ifeq ($(ARCH),mips64)
 override LOADERS=
@@ -986,7 +991,7 @@ override FPCOPT+=-Ur
 endif
 ifeq ($(ARCH),arm)
 override LOADERS+=ucprt0
-CPU_UNITS=$(CPUUNIT)
+CPU_UNITS=$(CPUUNIT) $(INTRINSICSUNIT)
 endif
 ifeq ($(ARCH),sparc)
   override FPCOPT+=-Fisparcgen
@@ -3191,6 +3196,13 @@ mmx$(PPUEXT) : $(MMX_DEPS)
 	$(COMPILER) $(MMX_OPT) $<
 System.CPU.MMX$(PPUEXT) : $(NSINC)/System.CPU.MMX.pp $(MMX_DEPS)
 	$(COMPILER) $(MMX_OPT) $<
+INTRINSICS_DEPS=$(PROCINC)/intrinsics.pp \
+	 $(SYSTEMUNIT)$(PPUEXT) \
+	 $(INTRINSICS_DEPS_OS) $(INTRINSICS_DEPS_CPU)
+intrinsics$(PPUEXT) : $(INTRINSICS_DEPS)
+	$(COMPILER) $(INTRINSICS_OPT) $<
+System.Intrinsics$(PPUEXT) : $(NSINC)/System.Intrinsics.pp $(INTRINSICS_DEPS)
+	$(COMPILER) $(INTRINSICS_OPT) $<
 ifeq ($(filter -dFPC_USE_LIBC,$(FPCOPT)),)
   X86_DEPS_OS+=$(SYSCALLUNIT)$(PPUEXT)
 endif

rtl/linux/Makefile.fpc

@@ -78,7 +78,7 @@ endif
 endif
 # syscall unit compiled with -dFPC_USE_LIBC
 # required mode objfpc which adds a dependency to
-# objpas unit 
+# objpas unit
 ifneq ($(filter -dFPC_USE_LIBC,$(OPT) $(CROSSOPT)),)
   SYSCALL_DEPS_OS+=$(OBJPASUNIT)$(PPUEXT)
 endif
@@ -103,6 +103,10 @@ SYSINIT_UNITS=si_prc si_c si_g si_dll
 override LOADERS=abitag
 endif
 
+ifeq ($(ARCH),aarch64)
+CPU_UNITS=$(INTRINSICSUNIT)
+endif
+
 ifeq ($(ARCH),powerpc64)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_c si_g si_dll
@@ -116,11 +120,13 @@ endif
 ifeq ($(ARCH),riscv32)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 
 ifeq ($(ARCH),riscv64)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c si_g
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 
 ifeq ($(ARCH),mips64)
@@ -143,7 +149,7 @@ endif
 
 ifeq ($(ARCH),arm)
 override LOADERS+=ucprt0
-CPU_UNITS=$(CPUUNIT)
+CPU_UNITS=$(CPUUNIT) $(INTRINSICSUNIT)
 endif
 
 ifeq ($(ARCH),sparc)

rtl/riscv/cpuinnr.inc

@@ -0,0 +1,16 @@
+  {
+    Defines CPU intrinsic indicies for RiscV
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2021 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+fpc_in_riscv_pause = fpc_in_cpu_first+0;

rtl/riscv/cpuprocs.inc

@@ -0,0 +1,16 @@
+{
+    Defines CPU intrinsics for RiscV
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+procedure fpc_riscv_pause;[internproc:fpc_in_riscv_pause];

rtl/riscv/intrinsics.inc

@@ -0,0 +1,28 @@
+{
+    Provides CPU intrinsics for RiscV
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2021 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+{$IFNDEF FPC_DOTTEDUNITS}
+unit intrinsics;
+{$ENDIF FPC_DOTTEDUNITS}
+
+  interface
+
+    const
+    {$i cpuinnr.inc}
+
+    {$i cpuprocs.inc}
+
+  implementation
+
+end.

rtl/riscv32/intrinsics.pp

@@ -0,0 +1,16 @@
+{
+    Provides CPU intrinsics for RiscV 32
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+{$I ../ricsv/intrinsics.inc}

rtl/riscv64/intrinsics.pp

@@ -0,0 +1,16 @@
+{
+    Provides CPU intrinsics for RiscV 64
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+{$I ../riscv/intrinsics.inc}

rtl/x86_64/cpuh.inc

@@ -34,6 +34,7 @@ function fpc_x86_get_ds:longint;[internproc:fpc_in_x86_get_ds];
 function fpc_x86_get_es:longint;[internproc:fpc_in_x86_get_es];
 function fpc_x86_get_fs:longint;[internproc:fpc_in_x86_get_fs];
 function fpc_x86_get_gs:longint;[internproc:fpc_in_x86_get_gs];
+procedure fpc_x86_pause;[internproc:fpc_in_x86_pause];
 
 { include automatically generated procs }
 {$if not defined(VER3_2)}

rtl/x86_64/cpuinnr.inc

@@ -26,6 +26,7 @@
   fpc_in_x86_get_es   = fpc_in_cpu_first+11;
   fpc_in_x86_get_fs   = fpc_in_cpu_first+12;
   fpc_in_x86_get_gs   = fpc_in_cpu_first+13;
+  fpc_in_x86_pause    = fpc_in_cpu_first+14;
   
    { include automatically generated numbers }
    {$ifdef VER3_3_1}