* tried to change everything to use int64/qword, doesn't work yet :(

utils/simulator/alphasim.pas

@@ -18,7 +18,12 @@
 program alphaemu;
 
   uses
-     dos,simbase,simlib,
+{$ifdef delphi}
+     dmisc,
+{$else}
+     dos,
+{$endif}
+     simbase,simlib,
 {$ifdef FPC}
 {$ifdef go32v2}
      dpmiexcp,
@@ -34,7 +39,7 @@ program alphaemu;
 
   { elf file types }
   type
-     telf64_hdr = record
+     telf64_hdr = packed record
         e_ident : array[0..15] of char;
         e_type : integer;
         e_machine : word;
@@ -51,7 +56,7 @@ program alphaemu;
         e_shstrndx : integer;
      end;
 
-     telf64_phdr = record
+     telf64_phdr = packed record
         p_type : longint;
         p_flags : longint;
         { Segment file offset }
@@ -72,10 +77,17 @@ program alphaemu;
      pelf64_phdr_array = ^telf64_phdr_array;
 
   const
+{$ifdef fpc}
+     { 64kB Stacksize }
+     stacksize = 64*1024;
+     { stack start at 4 GB }
+     stackstart : dword = 1024*1024*1024*4-stacksize;
+{$else fpc}
      { 64kB Stacksize }
-     stacksize = 64.0*1024.0;
+     stacksize = 64*1024.0;
      { stack start at 4 GB }
-     stackstart = 1024.0*1024.0*1024.0*4.0-stacksize;
+     stackstart = 1024.0*1024.0*1024.0*4-stacksize;
+{$endif fpc}
   { alpha specific types }
   type
      tintreg = record
@@ -171,7 +183,8 @@ program alphaemu;
     begin
 {$ifdef DEBUG}
        elapsedtime:=realtime-sim.starttime;
-       write('Executed ',sim.instrcount:0:0,' instructions in ',
+
+       write('Executed ',sim.instrcount:0,' instructions in ',
          elapsedtime:0:2,' sec');
        if elapsedtime<>0.0 then
          begin
@@ -190,7 +203,7 @@ program alphaemu;
        memory.init;
        { setup dummy registers }
        state.r[31].valueq:=0;
-       state.f[31].valued:=0.0;
+       state.f[31].valued:=0;
        memory.allocate(stackstart,stacksize);
     end;
 
@@ -236,7 +249,7 @@ program alphaemu;
 {$endif DEBUG}
     end;
 
-  procedure talphasim.run(pc : qword);
+  procedure talphasim.run(pc : taddr);
 
     var
        instruction : tinstruction;
@@ -244,7 +257,7 @@ program alphaemu;
        lit : byte;
        va : tintreg;
 
-    function getbranchdisp : qword;
+    function getbranchdisp : int64;
 
       var
          l : longint;
@@ -435,7 +448,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  if rega<>r_zero then
-                   state.r[rega].valueq:=state.r[regb].valueq+integer(instruction and $ffff);
+                   state.r[rega].valueq:=state.r[regb].valueq+int64(integer(instruction and $ffff));
               end;
             { LDAH }
             $9:
@@ -444,7 +457,7 @@ program alphaemu;
                  regb:=(instruction and $1f0000) shr 16;
                  if rega<>r_zero then
                    state.r[rega].valueq:=state.r[regb].valueq+
-                     (longint(integer(instruction and $ffff))*65536);
+                     (int64(integer(instruction and $ffff))*65536);
               end;
             { LDQ_U }
             $B:
@@ -453,7 +466,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  valueqb:=state.r[regb].valueq+
-                     (longint(integer(instruction and $ffff)));
+                     (int64(integer(instruction and $ffff)));
                  tqwordrec(valueqb).low32:=tqwordrec(valueqb).low32 and $fffffff8;
                  if rega<>r_zero then
                    state.r[rega].valueq:=memory.readq(valueqb);
@@ -465,7 +478,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  memory.writeq(va.valueq,state.r[rega].valueq);
               end;
 
@@ -643,10 +656,8 @@ program alphaemu;
                       begin
                          if regc<>r_zero then
                            begin
-                              state.r[regc].low32:=state.r[rega].low32 xor
-                                tqwordrec(valueqb).low32;
-                              state.r[regc].high32:=state.r[rega].high32 xor
-                                tqwordrec(valueqb).high32;
+                              state.r[regc].valueq:=state.r[rega].valueq xor
+                                valueqb;
                            end;
                       end;
                     { CMOVLT }
@@ -666,10 +677,8 @@ program alphaemu;
                       begin
                          if regc<>r_zero then
                            begin
-                              state.r[regc].low32:=tqwordrec(valueqa).low32 xor
-                                not(tqwordrec(valueqb).low32);
-                              state.r[regc].high32:=tqwordrec(valueqa).high32 xor
-                                not(tqwordrec(valueqb).high32);
+                              state.r[regc].valueq:=valueqa xor
+                                not(valueqb);
                            end;
                       end;
                     { CMOVLE }
@@ -782,7 +791,7 @@ program alphaemu;
                     $34:
                       begin
                          if regc<>r_zero then
-                           shift_right_q(valueqa,trunc(valueqb) and $3f,state.r[regc].valueq);
+                           state.r[regc].valueq:=state.r[regc].valueq shr (valueqb and $3f);
                       end;
                     { EXTQL }
                     $36:
@@ -878,7 +887,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  if rega<>f_zero then
                    begin
                       { we need to copy the bit pattern! }
@@ -894,7 +903,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  if rega<>f_zero then
                    state.f[rega].valueq:=memory.readq(va.valueq);
                  { !!!!!! no translation exceptions! }
@@ -907,7 +916,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  fs:=state.f[rega].valued;
                  memory.writed(va.valueq,longint(fs));
                  { !!!!!! no tranlation exceptions! }
@@ -919,7 +928,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  memory.writeq(va.valueq,state.f[rega].valueq);
                  { !!!!!! no translation exceptions! }
               end;
@@ -931,7 +940,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  fs:=state.f[rega].valued;
                  memory.writed(va.valueq,longint(fs));
                  { !!!!!! no tranlation exceptions! }
@@ -943,7 +952,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  memory.writeq(va.valueq,state.f[rega].valueq);
                  { !!!!!! no translation exceptions! }
               end;
@@ -955,7 +964,7 @@ program alphaemu;
                  regb:=(instruction and $1f0000) shr 16;
                  if rega<>r_zero then
                    state.r[rega].low32:=memory.readalignedd(state.r[regb].valueq+
-                     (longint(integer(instruction and $ffff))));
+                     (int64(integer(instruction and $ffff))));
                  { sign extend }
                  if state.r[rega].low32<0 then
                    state.r[rega].high32:=$ffffffff
@@ -970,7 +979,7 @@ program alphaemu;
                  regb:=(instruction and $1f0000) shr 16;
                  if rega<>r_zero then
                    state.r[rega].valueq:=memory.readalignedq(state.r[regb].valueq+
-                     (longint(integer(instruction and $ffff))));
+                     (int64(integer(instruction and $ffff))));
               end;
             { STL }
             $2C:
@@ -979,7 +988,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  memory.writealignedd(va.valueq,state.r[rega].low32);
               end;
             { STQ }
@@ -989,7 +998,7 @@ program alphaemu;
                  rega:=(instruction and $3e00000) shr 21;
                  regb:=(instruction and $1f0000) shr 16;
                  va.valueq:=state.r[regb].valueq+
-                   (longint(integer(instruction and $ffff)));
+                   (int64(integer(instruction and $ffff)));
                  memory.writeq(va.valueq,state.r[rega].valueq);
               end;
             { BR,BSR }
@@ -1267,10 +1276,21 @@ program alphaemu;
   end.
 {
   $Log$
-  Revision 1.3  2000-02-09 16:44:15  peter
+  Revision 1.4  2000-02-19 15:57:25  florian
+    * tried to change everything to use int64/qword, doesn't work yet :(
+
+  Revision 1.3  2000/02/09 16:44:15  peter
     * log truncated
 
   Revision 1.2  2000/01/07 16:46:06  daniel
     * copyright 2000
 
+  Revision 1.1  1999/06/14 11:49:48  florian
+    + initial revision, it runs simple Alpha Linux ELF executables
+       - integer operations are nearly completed (non with overflow checking)
+       - floating point operations aren't implemented (except loading and
+         storing)
+       - only the really necessary system calls are implemented by dummys
+         write syscalls are redirected to the console
+
 }

utils/simulator/fastmm64.pas

@@ -53,6 +53,7 @@ unit fastmm64;
       begin
          writeln;
          writeln('Exception: ',s,' at $',qword2str(addr));
+         runerror(255);
          stopsim;
       end;
 
@@ -73,6 +74,7 @@ unit fastmm64;
            if (tqwordrec(addr).high32 and $fffffff0)<>0 then
              begin
                 writeln('This memory manager supports only 36 bit');
+                writeln('Base address was ',qword2str(addr));
                 halt(1);
              end;
            upperbits:=((tqwordrec(addr).high32 and $f) shl 12) or ((tqwordrec(addr).low32 and $fff) shr 20);
@@ -91,8 +93,10 @@ unit fastmm64;
            begin
               if size>1024*1024 then
                 asize:=1024*1024;
-              size:=size-asize;
               allocateblock(addr);
+              if asize>size then
+                break;
+              size:=size-asize;
               addr:=addr+asize;
            end;
       end;
@@ -200,10 +204,20 @@ unit fastmm64;
 end.
 {
   $Log$
-  Revision 1.3  2000-02-09 16:44:15  peter
+  Revision 1.4  2000-02-19 15:57:25  florian
+    * tried to change everything to use int64/qword, doesn't work yet :(
+
+  Revision 1.3  2000/02/09 16:44:15  peter
     * log truncated
 
   Revision 1.2  2000/01/07 16:46:06  daniel
     * copyright 2000
 
+  Revision 1.1  1999/06/14 11:49:48  florian
+    + initial revision, it runs simple Alpha Linux ELF executables
+       - integer operations are nearly completed (non with overflow checking)
+       - floating point operations aren't implemented (except loading and
+         storing)
+       - only the really necessary system calls are implemented by dummys
+         write syscalls are redirected to the console
 }

utils/simulator/simbase.pas

@@ -14,21 +14,26 @@
 
  **********************************************************************}
 {$N+}
+{$H-}
 unit simbase;
 
   interface
-
+{$ifdef Delphi}
+    uses
+       dmisc;
+{$else Delphi}
     uses
        dos;
+{$endif Delphi}
 
     { global types }
     type
        { tindex must be at least of type integer }
        tindex = integer;
-
+{$ifndef FPC}
        int64 = comp;
        qword = comp;
-
+{$endif FPC}
        dword = longint;
        tdword = array[0..3] of byte;
 
@@ -111,10 +116,21 @@ begin
 end.
 {
   $Log$
-  Revision 1.3  2000-02-09 16:44:15  peter
+  Revision 1.4  2000-02-19 15:57:25  florian
+    * tried to change everything to use int64/qword, doesn't work yet :(
+
+  Revision 1.3  2000/02/09 16:44:15  peter
     * log truncated
 
   Revision 1.2  2000/01/07 16:46:07  daniel
     * copyright 2000
 
+  Revision 1.1  1999/06/14 11:49:48  florian
+    + initial revision, it runs simple Alpha Linux ELF executables
+       - integer operations are nearly completed (non with overflow checking)
+       - floating point operations aren't implemented (except loading and
+         storing)
+       - only the really necessary system calls are implemented by dummys
+         write syscalls are redirected to the console
+
 }

utils/simulator/simlib.pas

@@ -25,35 +25,35 @@ unit simlib;
     uses
        simbase;
 
-    procedure byte_zap(q : qword;b : byte;var result : qword);
+    procedure byte_zap(q : qword;b : byte;var r : qword);
 
     { shifts q b bytes left }
-    procedure shift_left_q(q : qword;b : byte;var result : qword);
+    procedure shift_left_q(q : qword;b : byte;var r : qword);
 
     { shifts q b bytes right }
-    procedure shift_right_q(q : qword;b : byte;var result : qword);
+    procedure shift_right_q(q : qword;b : byte;var r : qword);
 
     { returns true if i1<i2 assuming that c1 and c2 are unsigned !}
-    function ltu(c1,c2 : comp) : boolean;
+    function ltu(c1,c2 : qword) : boolean;
 
     { returns true if i1=<i2 assuming that c1 and c2 are unsigned !}
-    function leu(c1,c2 : comp) : boolean;
+    function leu(c1,c2 : qword) : boolean;
 
     { adds to owords, returns true if an overflow occurs }
-    function addoword(o1,o2 : oword;var result : oword) : boolean;
+    function addoword(o1,o2 : oword;var r : oword) : boolean;
 
     { adds two words, returns true if an overflow occurs }
-    function addword(w1,w2 : word;var result : word) : boolean;
+    function addword(w1,w2 : word;var r : word) : boolean;
 
     { sets an oword to zero }
     procedure zerooword(var o : oword);
 
     { multiplies two qwords into a full oword }
-    procedure mulqword(q1,q2 : qword;var result : oword);
+    procedure mulqword(q1,q2 : qword;var r : oword);
 
   implementation
 
-    procedure byte_zap(q : qword;b : byte;var result : qword);
+    procedure byte_zap(q : qword;b : byte;var r : qword);
 
       var
          i : tindex;
@@ -61,64 +61,64 @@ unit simlib;
       begin
          for i:=0 to 7 do
            if ((1 shl i) and b)=0 then
-             tqwordrec(result).bytes[i]:=tqwordrec(q).bytes[i]
+             tqwordrec(r).bytes[i]:=tqwordrec(q).bytes[i]
            else
-             tqwordrec(result).bytes[i]:=0;
+             tqwordrec(r).bytes[i]:=0;
       end;
 
     { shifts q b bytes left }
-    procedure shift_left_q(q : qword;b : byte;var result : qword);
+    procedure shift_left_q(q : qword;b : byte;var r : qword);
 
       var
          i : tindex;
 
       begin
-         result:=0;
+         r:=0;
          if b>63 then
          else if b>31 then
-           tqwordrec(result).high32:=tqwordrec(q).low32 shl (b-32)
+           tqwordrec(r).high32:=tqwordrec(q).low32 shl (b-32)
          else
            begin
               { bad solution! A qword shift would be nice! }
-              result:=q;
+              r:=q;
               for i:=1 to b do
                 begin
-                   tqwordrec(result).high32:=tqwordrec(result).high32 shl 1;
-                   if (tqwordrec(result).low32 and $80000000)<>0 then
-                     tqwordrec(result).high32:=tqwordrec(result).high32 or 1;
-                   tqwordrec(result).low32:=tqwordrec(result).low32 shl 1;
+                   tqwordrec(r).high32:=tqwordrec(r).high32 shl 1;
+                   if (tqwordrec(r).low32 and $80000000)<>0 then
+                     tqwordrec(r).high32:=tqwordrec(r).high32 or 1;
+                   tqwordrec(r).low32:=tqwordrec(r).low32 shl 1;
                 end;
            end;
       end;
 
     { shifts q b bytes right }
-    procedure shift_right_q(q : qword;b : byte;var result : qword);
+    procedure shift_right_q(q : qword;b : byte;var r : qword);
 
       var
          i : tindex;
 
       begin
-         result:=0;
+         r:=0;
          if b>63 then
          else if b>31 then
-           tqwordrec(result).low32:=tqwordrec(q).high32 shr (b-32)
+           tqwordrec(r).low32:=tqwordrec(q).high32 shr (b-32)
          else
            begin
               { bad solution! A qword shift would be nice! }
-              result:=q;
+              r:=q;
               for i:=1 to b do
                 begin
-                   tqwordrec(result).low32:=tqwordrec(result).low32 shr 1;
-                   if (tqwordrec(result).high32 and 1)<>0 then
-                     tqwordrec(result).low32:=tqwordrec(result).low32 or
+                   tqwordrec(r).low32:=tqwordrec(r).low32 shr 1;
+                   if (tqwordrec(r).high32 and 1)<>0 then
+                     tqwordrec(r).low32:=tqwordrec(r).low32 or
                        $80000000;
-                   tqwordrec(result).high32:=tqwordrec(result).high32 shr 1;
+                   tqwordrec(r).high32:=tqwordrec(r).high32 shr 1;
                 end;
            end;
       end;
 
     { returns true if i1<i2 assuming that c1 and c2 are unsigned !}
-    function ltu(c1,c2 : comp) : boolean;
+    function ltu(c1,c2 : qword) : boolean;
 
       begin
          if (c1>=0) and (c2>=0) then
@@ -132,7 +132,7 @@ unit simlib;
       end;
 
     { returns true if i1=<i2 assuming that c1 and c2 are unsigned !}
-    function leu(c1,c2 : comp) : boolean;
+    function leu(c1,c2 : qword) : boolean;
 
       begin
          if (c1>=0) and (c2>=0) then
@@ -146,15 +146,15 @@ unit simlib;
       end;
 
     { "ands" two qwords }
-    procedure andqword(w1,w2 : qword;var result : qword);
+    procedure andqword(w1,w2 : qword;var r : qword);
 
       begin
-         tqwordrec(result).low32:=tqwordrec(w1).low32 and tqwordrec(w2).low32;
-         tqwordrec(result).high32:=tqwordrec(w1).high32 and tqwordrec(w2).high32;
+         tqwordrec(r).low32:=tqwordrec(w1).low32 and tqwordrec(w2).low32;
+         tqwordrec(r).high32:=tqwordrec(w1).high32 and tqwordrec(w2).high32;
       end;
 
     { adds two words, returns true if an overflow occurs }
-    function addword(w1,w2 : word;var result : word) : boolean;
+    function addword(w1,w2 : word;var r : word) : boolean;
 
       var
          l : longint;
@@ -162,11 +162,11 @@ unit simlib;
       begin
          l:=w1+w2;
          addword:=(l and $10000)<>0;
-         result:=l and $ffff;
+         r:=l and $ffff;
       end;
 
     { adds two owords, returns true if an overflow occurs }
-    function addoword(o1,o2 : oword;var result : oword) : boolean;
+    function addoword(o1,o2 : oword;var r : oword) : boolean;
 
       var
          i : tindex;
@@ -176,11 +176,11 @@ unit simlib;
          carry:=0;
          for i:=0 to 7 do
            begin
-              result[i]:=o1[i]+o2[i]+carry;
-              { an overflow has occured, if the result is less
+              r[i]:=o1[i]+o2[i]+carry;
+              { an overflow has occured, if the r is less
                 than one of the summands
               }
-              if (result[i]<o1[i]) or (result[i]<o2[i]) then
+              if (r[i]<o1[i]) or (r[i]<o2[i]) then
                 carry:=1
               else
                 carry:=0;
@@ -196,7 +196,7 @@ unit simlib;
       end;
 
     { multiplies two qwords into a full oword }
-    procedure mulqword(q1,q2 : qword;var result : oword);
+    procedure mulqword(q1,q2 : qword;var r : oword);
 
       var
          i : tindex;
@@ -204,9 +204,9 @@ unit simlib;
          ho1 : oword;
 
       begin
-         { result is zero }
+         { r is zero }
          zerooword(ho1);
-         result:=ho1;
+         r:=ho1;
          towordrec(ho1).low64:=q1;
 
          bitpos:=1;
@@ -215,7 +215,7 @@ unit simlib;
            begin
               andqword(q2,bitpos,h);
               if h<>0 then
-                addoword(result,ho1,result);
+                addoword(r,ho1,r);
 
               { ho1:=2*ho1 }
               addoword(ho1,ho1,ho1);
@@ -226,10 +226,25 @@ unit simlib;
 end.
 {
   $Log$
-  Revision 1.3  2000-02-09 16:44:15  peter
+  Revision 1.4  2000-02-19 15:57:25  florian
+    * tried to change everything to use int64/qword, doesn't work yet :(
+
+  Revision 1.3  2000/02/09 16:44:15  peter
     * log truncated
 
   Revision 1.2  2000/01/07 16:46:07  daniel
     * copyright 2000
 
+<<<<<<< simlib.pas
+  Revision 1.1  1999/06/14 11:49:48  florian
+    + initial revision, it runs simple Alpha Linux ELF executables
+       - integer operations are nearly completed (non with overflow checking)
+       - floating point operations aren't implemented (except loading and
+         storing)
+       - only the really necessary system calls are implemented by dummys
+         write syscalls are redirected to the console
+
+}
+=======
 }
+>>>>>>> 1.3