Mass trailing space removal for rtl.

rtl/COPYING.txt

@@ -146,7 +146,7 @@ such a program is covered only if its contents constitute a work based
 on the Library (independent of the use of the Library in a tool for
 writing it).  Whether that is true depends on what the Library does
 and what the program that uses the Library does.
-  
+
   1. You may copy and distribute verbatim copies of the Library's
 complete source code as you receive it, in any medium, provided that
 you conspicuously and appropriately publish on each copy an

rtl/README.txt

@@ -9,9 +9,9 @@ makefile.fpc to guess reasonable defaults for everything it needs.
 (these files can be found in base.zip on the FTP site)
 
 The only variable that you may want to set are
-FPC             - What compiler to use. Use an absolute path. 
+FPC             - What compiler to use. Use an absolute path.
                   (default is ppc386)
-INSTALL_UNITDIR - Where to install the RTL units 
+INSTALL_UNITDIR - Where to install the RTL units
 OPT             - any special options you want to set for the compiler.
 
 In principle, you can also descend into the subdirectory of your OS, and
@@ -19,7 +19,7 @@ type 'make' there, that should also compile everything.
 
 The tree contains subdirectories for all the supported operating systems,
 as well as all processor architectures. The processor directories contain
-low-level routines which are required for the system unit (if they are not 
+low-level routines which are required for the system unit (if they are not
 available in high-level language form), as well as optimized versions of
 the pascal generic routines (the generic routine source code is localed in
 the inc subdirectory).

rtl/aix/ostypes.inc

@@ -89,7 +89,7 @@ TYPE
    TFlock   = flock;
    pFlock   = ^flock;
 
-   TFDSetEl = culong; 
+   TFDSetEl = culong;
    TFDSet    = array[0..wordsinfdset-1] of TFDSetEl;
    pFDSet    = ^TFDSet;
 
@@ -131,7 +131,7 @@ TYPE
        2 : (
             dummy    : cuint64;
             d_fileno : ino64_t;
-           ); 
+           );
    end;
 
 
@@ -245,7 +245,7 @@ type
 	    iov_len  : size_t;
 	   end;
   tiovec=iovec;
-  piovec=^tiovec;		
+  piovec=^tiovec;
 
  tms = packed record
          tms_utime  : clock_t;  { User CPU time }

rtl/aix/pthread.inc

@@ -29,7 +29,7 @@
     _PTHREAD_MUTEX_NORMAL        = 5;
     _PTHREAD_MUTEX_ERRORCHECK    = 3;
     _PTHREAD_MUTEX_RECURSIVE     = 4;
-    
+
   type
     sched_param = record
       __sched_priority: cint;

rtl/aix/ptypes.inc

@@ -181,7 +181,7 @@ Type
 
   mbstate_t = pointer;
   pmbstate_t = ^mbstate_t;
-  
+
 
 //  clock32_t = int32_t;
   timeval32 = record

rtl/aix/sysosh.inc

@@ -19,7 +19,7 @@ type
   THandle = Longint;
   TThreadID = Cardinal;
   TOSTimestamp = Int64;
-  
+
   PRTLCriticalSection = ^TRTLCriticalSection;
   TRTLCriticalSection = record
 {$ifdef cpu64}

rtl/aix/termios.inc

@@ -404,7 +404,7 @@ type
   cc_t = byte;
 
 const
-  NCCS = 16;  
+  NCCS = 16;
 type
   Pspeed_t = ^speed_t;
   speed_t = dword;
@@ -446,170 +446,170 @@ function cfsetispeed(var _para1:termios; _para2:speed_t):longint;cdecl;external;
 { values for optional_actions arguments to tcsetattr()  }
 
 const
-  TCSANOW = 0;  
-  TCSADRAIN = 1;  
-  TCSAFLUSH = 2;  
+  TCSANOW = 0;
+  TCSADRAIN = 1;
+  TCSAFLUSH = 2;
 { values for the queue_selector argument to tcflush()  }
-  TCIFLUSH = 0;  
-  TCOFLUSH = 1;  
-  TCIOFLUSH = 2;  
+  TCIFLUSH = 0;
+  TCOFLUSH = 1;
+  TCIOFLUSH = 2;
 { values for the action argument to tcflow()  }
-  TCOOFF = 0;  
-  TCOON = 1;  
-  TCIOFF = 2;  
-  TCION = 3;  
+  TCOOFF = 0;
+  TCOON = 1;
+  TCIOFF = 2;
+  TCION = 3;
 { control characters  }
-  VINTR = 0;  
-  VQUIT = 1;  
-  VERASE = 2;  
-  VKILL = 3;  
-  VEOF = 4;  
-  VEOL = 5;  
-  VSTART = 7;  
-  VSTOP = 8;  
-  VSUSP = 9;  
-  VMIN = 4;  
-  VTIME = 5;  
-  VEOL2 = 6;  
-  VDSUSP = 10;  
-  VREPRINT = 11;  
-  VDISCRD = 12;  
-  VWERSE = 13;  
-  VLNEXT = 14;  
+  VINTR = 0;
+  VQUIT = 1;
+  VERASE = 2;
+  VKILL = 3;
+  VEOF = 4;
+  VEOL = 5;
+  VSTART = 7;
+  VSTOP = 8;
+  VSUSP = 9;
+  VMIN = 4;
+  VTIME = 5;
+  VEOL2 = 6;
+  VDSUSP = 10;
+  VREPRINT = 11;
+  VDISCRD = 12;
+  VWERSE = 13;
+  VLNEXT = 14;
 { 5.4 compatability  }
-  VSTRT = VSTART;  
+  VSTRT = VSTART;
 
 const
-  B0 = $00000000;  
-  B50 = $00000001;  
-  B75 = $00000002;  
-  B110 = $00000003;  
-  B134 = $00000004;  
-  B150 = $00000005;  
-  B200 = $00000006;  
-  B300 = $00000007;  
-  B600 = $00000008;  
-  B1200 = $00000009;  
-  B1800 = $0000000a;  
-  B2400 = $0000000b;  
-  B4800 = $0000000c;  
-  B9600 = $0000000d;  
-  B19200 = $0000000e;  
-  B38400 = $0000000f;  
-  EXTA = B19200;  
-  EXTB = B38400;  
+  B0 = $00000000;
+  B50 = $00000001;
+  B75 = $00000002;
+  B110 = $00000003;
+  B134 = $00000004;
+  B150 = $00000005;
+  B200 = $00000006;
+  B300 = $00000007;
+  B600 = $00000008;
+  B1200 = $00000009;
+  B1800 = $0000000a;
+  B2400 = $0000000b;
+  B4800 = $0000000c;
+  B9600 = $0000000d;
+  B19200 = $0000000e;
+  B38400 = $0000000f;
+  EXTA = B19200;
+  EXTB = B38400;
 { _ALL_SOURCE  }
 { c_iflag bits  }
 
 const
-  IGNBRK = $00000001;  
-  BRKINT = $00000002;  
-  IGNPAR = $00000004;  
-  PARMRK = $00000008;  
-  INPCK = $00000010;  
-  ISTRIP = $00000020;  
-  INLCR = $00000040;  
-  IGNCR = $00000080;  
-  ICRNL = $00000100;  
-  IXON = $00000200;  
-  IXOFF = $00000400;  
+  IGNBRK = $00000001;
+  BRKINT = $00000002;
+  IGNPAR = $00000004;
+  PARMRK = $00000008;
+  INPCK = $00000010;
+  ISTRIP = $00000020;
+  INLCR = $00000040;
+  IGNCR = $00000080;
+  ICRNL = $00000100;
+  IXON = $00000200;
+  IXOFF = $00000400;
 const
-  IUCLC = $00000800;  
+  IUCLC = $00000800;
 
 const
-  IXANY = $00001000;  
-  IMAXBEL = $00010000;  
+  IXANY = $00001000;
+  IMAXBEL = $00010000;
 { c_oflag bits  }
 
 const
-  OPOST = $00000001;  
+  OPOST = $00000001;
 const
-  OLCUC = $00000002;  
+  OLCUC = $00000002;
 
 const
-  ONLCR = $00000004;  
-  OCRNL = $00000008;  
-  ONOCR = $00000010;  
-  ONLRET = $00000020;  
-  OFILL = $00000040;  
-  OFDEL = $00000080;  
-  CRDLY = $00000300;  
+  ONLCR = $00000004;
+  OCRNL = $00000008;
+  ONOCR = $00000010;
+  ONLRET = $00000020;
+  OFILL = $00000040;
+  OFDEL = $00000080;
+  CRDLY = $00000300;
 //  CR0 = $00000000;
 //  CR1 = $00000100;
 //  CR2 = $00000200;
 //  CR3 = $00000300;
-  TABDLY = $00000c00;  
+  TABDLY = $00000c00;
 //  TAB0 = $00000000;
 //  TAB1 = $00000400;
 //  TAB2 = $00000800;
 //  TAB3 = $00000c00;
-  BSDLY = $00001000;  
+  BSDLY = $00001000;
 //  BS0 = $00000000;
 //  BS1 = $00001000;
-  FFDLY = $00002000;  
+  FFDLY = $00002000;
 //  FF0 = $00000000;
 //  FF1 = $00002000;
-  NLDLY = $00004000;  
+  NLDLY = $00004000;
 //  NL0 = $00000000;
 //  NL1 = $00004000;
-  VTDLY = $00008000;  
-  VT0 = $00000000;  
-  VT1 = $00008000;  
-  DLY_MASK = ((((NLDLY or CRDLY) or TABDLY) or BSDLY) or VTDLY) or FFDLY;  
+  VTDLY = $00008000;
+  VT0 = $00000000;
+  VT1 = $00008000;
+  DLY_MASK = ((((NLDLY or CRDLY) or TABDLY) or BSDLY) or VTDLY) or FFDLY;
 { expand tabs to spaces added     	 }
-  OXTABS = $00040000;  
+  OXTABS = $00040000;
 { on 08/05/92.                          }
 { discard EOT's (^D) on output    	 }
-  ONOEOT = $00080000;  
+  ONOEOT = $00080000;
 { added on 08/05/92.                    }
 { c_cflag bits  }
 
 const
-  _CBAUD = $0000000f;  
+  _CBAUD = $0000000f;
   CBAUD = _CBAUD;
   CSIZE = $00000030;
-  CS5 = $00000000;  
-  CS6 = $00000010;  
-  CS7 = $00000020;  
-  CS8 = $00000030;  
-  CSTOPB = $00000040;  
-  CREAD = $00000080;  
-  PARENB = $00000100;  
-  PARODD = $00000200;  
-  HUPCL = $00000400;  
-  CLOCAL = $00000800;  
-  _CIBAUD = $000f0000;  
-  _IBSHIFT = 16;  
-  CIBAUD = _CIBAUD;  
-  IBSHIFT = _IBSHIFT;  
-  PAREXT = $00100000;  
+  CS5 = $00000000;
+  CS6 = $00000010;
+  CS7 = $00000020;
+  CS8 = $00000030;
+  CSTOPB = $00000040;
+  CREAD = $00000080;
+  PARENB = $00000100;
+  PARODD = $00000200;
+  HUPCL = $00000400;
+  CLOCAL = $00000800;
+  _CIBAUD = $000f0000;
+  _IBSHIFT = 16;
+  CIBAUD = _CIBAUD;
+  IBSHIFT = _IBSHIFT;
+  PAREXT = $00100000;
 { c_lflag bits  }
 
 const
-  ISIG = $00000001;  
-  ICANON = $00000002;  
+  ISIG = $00000001;
+  ICANON = $00000002;
 
 const
-  XCASE = $00000004;  
+  XCASE = $00000004;
 
 const
 //  ECHO = $00000008;
-  ECHOE = $00000010;  
-  ECHOK = $00000020;  
-  ECHONL = $00000040;  
-  NOFLSH = $00000080;  
+  ECHOE = $00000010;
+  ECHOK = $00000020;
+  ECHONL = $00000040;
+  NOFLSH = $00000080;
 //  TOSTOP = $00010000;
-  ECHOCTL = $00020000;  
-  ECHOPRT = $00040000;  
-  ECHOKE = $00080000;  
+  ECHOCTL = $00020000;
+  ECHOPRT = $00040000;
+  ECHOKE = $00080000;
 //  FLUSHO = $00100000;
 { use alternate WERASE    	 }
-  ALTWERASE = $00400000;  
+  ALTWERASE = $00400000;
 { algorithm, added ALTWERASE    }
 { on 08/05/92.                  }
 //  PENDIN = $20000000;
 { ALL_SOURCE  }
 
 const
-  IEXTEN = $00200000;  
+  IEXTEN = $00200000;
 

rtl/aix/unxfunc.inc

@@ -84,7 +84,7 @@ begin
     exit;
   assign(ft,GetTimeZoneFile);
 {$push}
-{$I-}  
+{$I-}
   reset(ft);
   if IOResult=0 then
     close(ft)

rtl/amicommon/lineinfo.pp

@@ -119,7 +119,7 @@ type
 
 { We use static variable so almost no stack is required, and is thus
   more safe when an error has occurred in the program }
-{$WARNING This code is not thread-safe, and needs improvement }  
+{$WARNING This code is not thread-safe, and needs improvement }
 var
   e          : TExeFile;
   stabcnt,              { amount of stabs }
@@ -360,7 +360,7 @@ begin
 
   if not OpenStabs(pointer(addr)) then
     exit;
-  
+
   { correct the value to the correct address in the file }
   { processaddress is set in OpenStabs                   }
   addr := dword(addr - e.processaddress);
@@ -374,7 +374,7 @@ begin
 {$ifdef DEBUG_LINEINFO}
   writeln(stderr,'Addr: ',hexstr(addr,sizeof(addr)*2));
 {$endif DEBUG_LINEINFO}
- 
+
   fillchar(funcstab,sizeof(tstab),0);
   fillchar(filestab,sizeof(tstab),0);
   fillchar(dirstab,sizeof(tstab),0);

rtl/amicommon/osdebug.inc

@@ -13,7 +13,7 @@
 
  **********************************************************************}
 
-{ Basic system-specific debug facility. Logs to the primary log source, which is 
+{ Basic system-specific debug facility. Logs to the primary log source, which is
   usually the serial port or where the serial log is redirected to (eg. RamDebug
   on MorphOS) We could also use some barely-documented RawDoFmt() blackmagic here
   specifying "1" as PutChProc pointer, but it doesn't really matter, because

rtl/amiga/m68k/legacyexec.inc

@@ -65,17 +65,17 @@ var
 begin
   CreateMsgPort:=nil;
   sigbit := AllocSignal(-1);
-  if sigbit = -1 then 
+  if sigbit = -1 then
     exit;
 
   msgPort := execAllocMem(sizeof(TMsgPort),MEMF_CLEAR);
-  if not assigned(msgPort) then 
+  if not assigned(msgPort) then
     begin
       FreeSignal(sigbit);
       exit;
     end;
 
-  with msgPort^ do 
+  with msgPort^ do
     begin
       mp_Node.ln_Name := nil;
       mp_Node.ln_Pri := 0;
@@ -123,7 +123,7 @@ end;
 procedure DeleteIORequest(IOReq: PIORequest); public name '_fpc_amiga_deleteiorequest';
 begin
   if assigned(IOReq) then
-    with IOReq^ do 
+    with IOReq^ do
       begin
         io_Message.mn_Node.ln_Type := $FF;
         io_Message.mn_ReplyPort := PMsgPort(PtrUInt(-1));

rtl/android/aarch64/sysnr.inc

@@ -1,5 +1,5 @@
 // Available syscalls for arm64-android.
-// This file is autogenerated by the genandroidsyscalls.py script. 
+// This file is autogenerated by the genandroidsyscalls.py script.
 // Script location: https://svn.freepascal.org/svn/fpcbuild/scripts/android
 
 const

rtl/android/arm/sysnr.inc

@@ -1,5 +1,5 @@
 // Available syscalls for arm-android.
-// This file is autogenerated by the genandroidsyscalls.py script. 
+// This file is autogenerated by the genandroidsyscalls.py script.
 // Script location: https://svn.freepascal.org/svn/fpcbuild/scripts/android
 
 const

rtl/android/i386/sysnr.inc

@@ -1,5 +1,5 @@
 // Available syscalls for x86-android.
-// This file is autogenerated by the genandroidsyscalls.py script. 
+// This file is autogenerated by the genandroidsyscalls.py script.
 // Script location: https://svn.freepascal.org/svn/fpcbuild/scripts/android
 
 const
@@ -235,70 +235,70 @@ const
   syscall_nr_copy_file_range = 377;
   syscall_nr_preadv2 = 378;
   syscall_nr_pwritev2 = 379;
-  syscall_nr_pkey_mprotect = 380;    
-  syscall_nr_pkey_alloc = 381;    
-  syscall_nr_pkey_free = 382;    
-  syscall_nr_statx = 383;    
-  syscall_nr_arch_prctl = 384;    
-  syscall_nr_io_pgetevents = 385;    
-  syscall_nr_rseq = 386;    
-  syscall_nr_semget = 393;    
-  syscall_nr_semctl = 394;    
-  syscall_nr_shmget = 395;    
-  syscall_nr_shmctl = 396;    
-  syscall_nr_shmat = 397;    
-  syscall_nr_shmdt = 398;    
-  syscall_nr_msgget = 399;    
-  syscall_nr_msgsnd = 400;    
-  syscall_nr_msgrcv = 401;    
-  syscall_nr_msgctl = 402;    
-  syscall_nr_clock_gettime64 = 403;    
-  syscall_nr_clock_settime64 = 404;    
-  syscall_nr_clock_adjtime64 = 405;    
-  syscall_nr_clock_getres_time64 = 406;    
-  syscall_nr_clock_nanosleep_time64 = 407;    
-  syscall_nr_timer_gettime64 = 408;    
-  syscall_nr_timer_settime64 = 409;    
-  syscall_nr_timerfd_gettime64 = 410;    
-  syscall_nr_timerfd_settime64 = 411;    
-  syscall_nr_utimensat_time64 = 412;    
-  syscall_nr_pselect6_time64 = 413;    
-  syscall_nr_ppoll_time64 = 414;    
-  syscall_nr_io_pgetevents_time64 = 416;    
-  syscall_nr_recvmmsg_time64 = 417;    
-  syscall_nr_mq_timedsend_time64 = 418;    
-  syscall_nr_mq_timedreceive_time64 = 419;    
-  syscall_nr_semtimedop_time64 = 420;    
-  syscall_nr_rt_sigtimedwait_time64 = 421;    
-  syscall_nr_futex_time64 = 422;    
-  syscall_nr_sched_rr_get_interval_time64 = 423;    
-  syscall_nr_pidfd_send_signal = 424;    
-  syscall_nr_io_uring_setup = 425;    
-  syscall_nr_io_uring_enter = 426;    
-  syscall_nr_io_uring_register = 427;    
-  syscall_nr_open_tree = 428;    
-  syscall_nr_move_mount = 429;    
-  syscall_nr_fsopen = 430;    
-  syscall_nr_fsconfig = 431;    
-  syscall_nr_fsmount = 432;    
-  syscall_nr_fspick = 433;    
-  syscall_nr_pidfd_open = 434;    
-  syscall_nr_clone3 = 435;    
-  syscall_nr_close_range = 436;    
-  syscall_nr_openat2 = 437;    
-  syscall_nr_pidfd_getfd = 438;    
-  syscall_nr_faccessat2 = 439;    
-  syscall_nr_process_madvise = 440;    
-  syscall_nr_epoll_pwait2 = 441;    
-  syscall_nr_mount_setattr = 442;    
-  syscall_nr_quotactl_fd = 443;    
-  syscall_nr_landlock_create_ruleset = 444;    
-  syscall_nr_landlock_add_rule = 445;    
-  syscall_nr_landlock_restrict_self = 446;    
-  syscall_nr_memfd_secret = 447;    
-  syscall_nr_process_mrelease = 448;    
-  syscall_nr_futex_waitv = 449;    
-  syscall_nr_set_mempolicy_home_node = 450;    
+  syscall_nr_pkey_mprotect = 380;
+  syscall_nr_pkey_alloc = 381;
+  syscall_nr_pkey_free = 382;
+  syscall_nr_statx = 383;
+  syscall_nr_arch_prctl = 384;
+  syscall_nr_io_pgetevents = 385;
+  syscall_nr_rseq = 386;
+  syscall_nr_semget = 393;
+  syscall_nr_semctl = 394;
+  syscall_nr_shmget = 395;
+  syscall_nr_shmctl = 396;
+  syscall_nr_shmat = 397;
+  syscall_nr_shmdt = 398;
+  syscall_nr_msgget = 399;
+  syscall_nr_msgsnd = 400;
+  syscall_nr_msgrcv = 401;
+  syscall_nr_msgctl = 402;
+  syscall_nr_clock_gettime64 = 403;
+  syscall_nr_clock_settime64 = 404;
+  syscall_nr_clock_adjtime64 = 405;
+  syscall_nr_clock_getres_time64 = 406;
+  syscall_nr_clock_nanosleep_time64 = 407;
+  syscall_nr_timer_gettime64 = 408;
+  syscall_nr_timer_settime64 = 409;
+  syscall_nr_timerfd_gettime64 = 410;
+  syscall_nr_timerfd_settime64 = 411;
+  syscall_nr_utimensat_time64 = 412;
+  syscall_nr_pselect6_time64 = 413;
+  syscall_nr_ppoll_time64 = 414;
+  syscall_nr_io_pgetevents_time64 = 416;
+  syscall_nr_recvmmsg_time64 = 417;
+  syscall_nr_mq_timedsend_time64 = 418;
+  syscall_nr_mq_timedreceive_time64 = 419;
+  syscall_nr_semtimedop_time64 = 420;
+  syscall_nr_rt_sigtimedwait_time64 = 421;
+  syscall_nr_futex_time64 = 422;
+  syscall_nr_sched_rr_get_interval_time64 = 423;
+  syscall_nr_pidfd_send_signal = 424;
+  syscall_nr_io_uring_setup = 425;
+  syscall_nr_io_uring_enter = 426;
+  syscall_nr_io_uring_register = 427;
+  syscall_nr_open_tree = 428;
+  syscall_nr_move_mount = 429;
+  syscall_nr_fsopen = 430;
+  syscall_nr_fsconfig = 431;
+  syscall_nr_fsmount = 432;
+  syscall_nr_fspick = 433;
+  syscall_nr_pidfd_open = 434;
+  syscall_nr_clone3 = 435;
+  syscall_nr_close_range = 436;
+  syscall_nr_openat2 = 437;
+  syscall_nr_pidfd_getfd = 438;
+  syscall_nr_faccessat2 = 439;
+  syscall_nr_process_madvise = 440;
+  syscall_nr_epoll_pwait2 = 441;
+  syscall_nr_mount_setattr = 442;
+  syscall_nr_quotactl_fd = 443;
+  syscall_nr_landlock_create_ruleset = 444;
+  syscall_nr_landlock_add_rule = 445;
+  syscall_nr_landlock_restrict_self = 446;
+  syscall_nr_memfd_secret = 447;
+  syscall_nr_process_mrelease = 448;
+  syscall_nr_futex_waitv = 449;
+  syscall_nr_set_mempolicy_home_node = 450;
 
 // The following syscalls are blocked by SECCOMP starting from Android 8.
 // Do not use them, unless you know what you are doing.

rtl/android/jvm/java_sys_android.inc

@@ -1,4 +1,4 @@
-  JLObject = class external 'java.lang' name 'Object' 
+  JLObject = class external 'java.lang' name 'Object'
   public
     constructor create(); overload;
   strict protected
@@ -18,7 +18,7 @@
     procedure wait(para1: jlong; para2: jint); overload; virtual; final;  // throws java.lang.InterruptedException
   end;
 
-  JISerializable = interface external 'java.io' name 'Serializable' 
+  JISerializable = interface external 'java.io' name 'Serializable'
   end;
 
   JLAbstractStringBuilder = class abstract external 'java.lang' name 'AbstractStringBuilder' (JLObject)
@@ -46,27 +46,27 @@
     function offsetByCodePoints(para1: jint; para2: jint): jint; overload; virtual;
   end;
 
-  JLAppendable = interface external 'java.lang' name 'Appendable' 
+  JLAppendable = interface external 'java.lang' name 'Appendable'
     function append(para1: jchar): JLAppendable; overload;  // throws java.io.IOException
     function append(para1: JLCharSequence): JLAppendable; overload;  // throws java.io.IOException
     function append(para1: JLCharSequence; para2: jint; para3: jint): JLAppendable; overload;  // throws java.io.IOException
   end;
 
-  JLCharSequence = interface external 'java.lang' name 'CharSequence' 
+  JLCharSequence = interface external 'java.lang' name 'CharSequence'
     function length(): jint; overload;
     function charAt(para1: jint): jchar; overload;
     function subSequence(para1: jint; para2: jint): JLCharSequence; overload;
     function toString(): JLString; overload;
   end;
 
-  JLCloneable = interface external 'java.lang' name 'Cloneable' 
+  JLCloneable = interface external 'java.lang' name 'Cloneable'
   end;
 
-  JLComparable = interface external 'java.lang' name 'Comparable' 
+  JLComparable = interface external 'java.lang' name 'Comparable'
     function compareTo(para1: JLObject): jint; overload;
   end;
 
-  JLIterable = interface external 'java.lang' name 'Iterable' 
+  JLIterable = interface external 'java.lang' name 'Iterable'
     function iterator(): JUIterator; overload;
   end;
 
@@ -132,7 +132,7 @@
     class function scalb(para1: jfloat; para2: jint): jfloat; static; overload;
   end;
 
-  JLReadable = interface external 'java.lang' name 'Readable' 
+  JLReadable = interface external 'java.lang' name 'Readable'
     function read(para1: JNCharBuffer): jint; overload;  // throws java.io.IOException
   end;
 
@@ -215,7 +215,7 @@
     procedure remove(); overload; virtual;
   end;
 
-  JLRAnnotatedElement = interface external 'java.lang.reflect' name 'AnnotatedElement' 
+  JLRAnnotatedElement = interface external 'java.lang.reflect' name 'AnnotatedElement'
     function getAnnotation(para1: JLClass): JLAAnnotation; overload;
     function getAnnotations(): Arr1JLAAnnotation; overload;
     function getDeclaredAnnotations(): Arr1JLAAnnotation; overload;
@@ -248,11 +248,11 @@
     class procedure setShort(para1: JLObject; para2: jint; para3: jshort); static; overload;  // throws java.lang.IllegalArgumentException, java.lang.ArrayIndexOutOfBoundsException
   end;
 
-  JLRGenericDeclaration = interface external 'java.lang.reflect' name 'GenericDeclaration' 
+  JLRGenericDeclaration = interface external 'java.lang.reflect' name 'GenericDeclaration'
     function getTypeParameters(): Arr1JLRTypeVariable; overload;
   end;
 
-  JLRMember = interface external 'java.lang.reflect' name 'Member' 
+  JLRMember = interface external 'java.lang.reflect' name 'Member'
     const
       &PUBLIC = 0;
       DECLARED = 1;
@@ -262,7 +262,7 @@
     function isSynthetic(): jboolean; overload;
   end;
 
-  JLRType = interface external 'java.lang.reflect' name 'Type' 
+  JLRType = interface external 'java.lang.reflect' name 'Type'
   end;
 
   JNBuffer = class abstract external 'java.nio' name 'Buffer' (JLObject)
@@ -606,24 +606,24 @@
     class function copyOfRange(var para1: array of JLObject; para2: jint; para3: jint; para4: JLClass): Arr1JLObject; static; overload;
   end;
 
-  JUComparator = interface external 'java.util' name 'Comparator' 
+  JUComparator = interface external 'java.util' name 'Comparator'
     function compare(para1: JLObject; para2: JLObject): jint; overload;
     function equals(para1: JLObject): jboolean; overload;
   end;
 
-  JUIterator = interface external 'java.util' name 'Iterator' 
+  JUIterator = interface external 'java.util' name 'Iterator'
     function hasNext(): jboolean; overload;
     function next(): JLObject; overload;
     procedure remove(); overload;
   end;
 
-  JUMap = interface external 'java.util' name 'Map' 
+  JUMap = interface external 'java.util' name 'Map'
     type
       InnerEntry = interface;
       Arr1InnerEntry = array of InnerEntry;
       Arr2InnerEntry = array of Arr1InnerEntry;
       Arr3InnerEntry = array of Arr2InnerEntry;
-      InnerEntry = interface external 'java.util' name 'Entry' 
+      InnerEntry = interface external 'java.util' name 'Entry'
         function equals(para1: JLObject): jboolean; overload;
         function getKey(): JLObject; overload;
         function getValue(): JLObject; overload;

rtl/android/mips64/sysnr.inc

@@ -1,5 +1,5 @@
 // Available syscalls for mips64-android.
-// This file is autogenerated by the genandroidsyscalls.py script. 
+// This file is autogenerated by the genandroidsyscalls.py script.
 // Script location: https://svn.freepascal.org/svn/fpcbuild/scripts/android
 
 const

rtl/android/mipsel/sysnr.inc

@@ -1,5 +1,5 @@
 // Available syscalls for mips-android.
-// This file is autogenerated by the genandroidsyscalls.py script. 
+// This file is autogenerated by the genandroidsyscalls.py script.
 // Script location: https://svn.freepascal.org/svn/fpcbuild/scripts/android
 
 const

rtl/android/x86_64/sysnr.inc

@@ -1,5 +1,5 @@
 // Available syscalls for x86_64-android.
-// This file is autogenerated by the genandroidsyscalls.py script. 
+// This file is autogenerated by the genandroidsyscalls.py script.
 // Script location: https://svn.freepascal.org/svn/fpcbuild/scripts/android
 
 const

rtl/arm/arm.inc

@@ -1346,7 +1346,7 @@ end;
 procedure barrier; assembler; nostackframe;
 asm
   // manually encode the instructions to avoid bootstrap and -march external
-  // assembler settings 
+  // assembler settings
 {$ifdef CPUARM_HAS_DMB}
   .long 0xf57ff05f  // dmb sy
 {$else CPUARM_HAS_DMB}
@@ -1398,7 +1398,7 @@ asm
 {$else CPUARM_HAS_DMB}
 {$ifdef CPUARMV6}
   mov r0, #0
-  .long 0xee070fba  // mcr 15, 0, r0, cr7, cr10, {5} 
+  .long 0xee070fba  // mcr 15, 0, r0, cr7, cr10, {5}
 {$else CPUARMV6}
 {$ifdef SYSTEM_HAS_KUSER_MEMORY_BARRIER}
   stmfd r13!, {lr}

rtl/arm/cpu.pp

@@ -63,7 +63,7 @@ unit cpu;
         auxv: PElf32AuxiliaryVector;
       begin
         psysinfo := 0;
-{$ifndef NO_ELF_SUPPORT} 
+{$ifndef NO_ELF_SUPPORT}
         ep := envp;
         while ep^ <> nil do
           Inc(ep);
@@ -82,7 +82,7 @@ unit cpu;
             end;
             Inc(auxv);
           end;
-{$endif ndef NO_ELF_SUPPORT} 
+{$endif ndef NO_ELF_SUPPORT}
       end;
 
 

rtl/arm/mathu.inc

@@ -153,7 +153,7 @@ const
                    _VFP_ENABLE_UM or
                    _VFP_ENABLE_PM or
                    _VFP_ENABLE_DM;    { mask for all flags     }
-                   
+
   _VFP_ROUNDINGMODE_MASK_SHIFT = 22;
   _VFP_ROUNDINGMODE_MASK = 3 shl _VFP_ROUNDINGMODE_MASK_SHIFT;
 
@@ -188,7 +188,7 @@ function VFPCw2RoundingMode(cw: dword): TFPURoundingMode;
   end;
 
 
-function GetRoundMode: TFPURoundingMode; 
+function GetRoundMode: TFPURoundingMode;
   begin
     result:=VFPCw2RoundingMode(VFP_GetCW);
   end;

rtl/atari/sysdir.inc

@@ -70,7 +70,7 @@ begin
       if (newdrive <> curdrive) then
         begin
           { verify if the drive we have to set actually exist.
-            not doing so may corrupt TOS internal structures, 
+            not doing so may corrupt TOS internal structures,
             according to docs. (KB) }
           drives:=gemdos_dsetdrv(curdrive);
           if (drives and (1 shl newdrive)) = 0 then

rtl/atari/sysfile.inc

@@ -71,7 +71,7 @@ var
   dosResult: longint;
 begin
   do_write:=0;
-  if (len<=0) or (h=-1) then 
+  if (len<=0) or (h=-1) then
     exit;
 
   dosResult:=gemdos_fwrite(h, len, addr);
@@ -92,10 +92,10 @@ begin
   if (len<=0) or (h=-1) then exit;
 
   dosResult:=gemdos_fread(h, len, addr);
-  if dosResult<0 then 
+  if dosResult<0 then
     begin
       Error2InOutRes(dosResult);
-    end 
+    end
   else
     do_read:=dosResult;
 end;

rtl/atari/sysutils.pp

@@ -159,7 +159,7 @@ end;
 function FileWrite(Handle: THandle; const Buffer; Count: LongInt): LongInt;
 begin
   FileWrite:=-1;
-  if (Count<=0) then 
+  if (Count<=0) then
     exit;
 
   FileWrite:=gemdos_fwrite(handle, count, @buffer);

rtl/avr/setjump.inc

@@ -18,7 +18,7 @@ function fpc_setjmp(var S : jmp_buf) : shortint;assembler;[Public, alias : 'FPC_
   asm
     mov r26,r24
     mov r27,r25
-{$ifndef CPUAVR_16_REGS}   
+{$ifndef CPUAVR_16_REGS}
     st x+,r1
     st x+,r2
     st x+,r3
@@ -34,13 +34,13 @@ function fpc_setjmp(var S : jmp_buf) : shortint;assembler;[Public, alias : 'FPC_
     st x+,r13
     st x+,r14
     st x+,r15
-{$endif CPUAVR_16_REGS}       
+{$endif CPUAVR_16_REGS}
     st x+,r16
     st x+,r17
-{$ifdef CPUAVR_16_REGS}   
+{$ifdef CPUAVR_16_REGS}
     st x+,r18
     st x+,r19
-{$endif CPUAVR_16_REGS}   
+{$endif CPUAVR_16_REGS}
     st x+,r28
     st x+,r29
 
@@ -71,7 +71,7 @@ procedure fpc_longjmp(var S : jmp_buf;value : shortint);assembler;[Public, alias
   asm
     mov r26,r24
     mov r27,r25
-{$ifndef CPUAVR_16_REGS}   
+{$ifndef CPUAVR_16_REGS}
     ld r1,x+
     ld r2,x+
     ld r3,x+
@@ -87,31 +87,31 @@ procedure fpc_longjmp(var S : jmp_buf;value : shortint);assembler;[Public, alias
     ld r13,x+
     ld r14,x+
     ld r15,x+
-{$endif CPUAVR_16_REGS}       
+{$endif CPUAVR_16_REGS}
     ld r16,x+
     ld r17,x+
-{$ifdef CPUAVR_16_REGS}   
+{$ifdef CPUAVR_16_REGS}
     ld r18,x+
     ld r19,x+
-{$endif CPUAVR_16_REGS}   
+{$endif CPUAVR_16_REGS}
     ld r28,x+
     ld r29,x+
 
     // restore stack pointer
     ld r18,x+
     ld r19,x+
-{$ifdef CPUAVR_16_REGS}   
+{$ifdef CPUAVR_16_REGS}
     in r16,63
-{$else CPUAVR_16_REGS}   
+{$else CPUAVR_16_REGS}
     in r0,63
-{$endif CPUAVR_16_REGS}   
+{$endif CPUAVR_16_REGS}
     cli
     out 62,r19
-{$ifdef CPUAVR_16_REGS}   
+{$ifdef CPUAVR_16_REGS}
     out	63,r16
-{$else CPUAVR_16_REGS}   
+{$else CPUAVR_16_REGS}
     out	63,r0
-{$endif CPUAVR_16_REGS}   
+{$endif CPUAVR_16_REGS}
     out	61,r18
 
     // restore return address

rtl/avr/setjumph.inc

@@ -16,13 +16,13 @@
 
 type
    jmp_buf = packed record
-{$ifndef CPUAVR_16_REGS}   
+{$ifndef CPUAVR_16_REGS}
      r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,
-{$endif CPUAVR_16_REGS}   
+{$endif CPUAVR_16_REGS}
      r16,r17,
-{$ifdef CPUAVR_16_REGS}   
+{$ifdef CPUAVR_16_REGS}
      r18,r19,
-{$endif CPUAVR_16_REGS}   
+{$endif CPUAVR_16_REGS}
      r28,r29,splo,sphi,pclo,pchi : byte;
 {$ifdef CPUAVR_3_BYTE_PC}
      pchighest : byte

rtl/beos/baseunix.pp

@@ -46,8 +46,8 @@ Uses UnixType;
   {$i bunxh.inc}		{ Functions}
 {$ENDIF}
 
-function fpgeterrno:longint; 
-procedure fpseterrno(err:longint); 
+function fpgeterrno:longint;
+procedure fpseterrno(err:longint);
 
 {$ifndef ver1_0}
 property errno : cint read fpgeterrno write fpseterrno;
@@ -58,9 +58,9 @@ property errno : cint read fpgeterrno write fpseterrno;
 {$ifdef FPC_USE_LIBC}
 {$ifdef beos}
 function  fpsettimeofday(tp:ptimeval;tzp:ptimezone):cint;
-Function fpFlock (var fd : text; mode : longint) : cint; 
-Function fpFlock (var fd : File; mode : longint) : cint; 
-Function fpFlock (fd, mode : longint) : cint; 
+Function fpFlock (var fd : text; mode : longint) : cint;
+Function fpFlock (var fd : File; mode : longint) : cint;
+Function fpFlock (fd, mode : longint) : cint;
 Function  FpNanoSleep  (req : ptimespec;rem : ptimespec):cint;
 {$endif}
 {$endif}
@@ -118,12 +118,12 @@ procedure fpseterrno(err:longint); external name 'FPC_SYS_SETERRNO';
 function intgeterrno:longint; external name 'FPC_SYS_GETERRNO';
 procedure intseterrno(err:longint); external name 'FPC_SYS_SETERRNO';
 
-function fpgeterrno:longint; 
+function fpgeterrno:longint;
 begin
   fpgeterrno:=intgeterrno;
 end;
 
-procedure fpseterrno(err:longint); 
+procedure fpseterrno(err:longint);
 begin
   intseterrno(err);
 end;
@@ -135,19 +135,19 @@ begin
   fpsettimeofday := settimeofday(tp, tzp);
 end;
 
-Function fpFlock (var fd : File; mode : longint) : cint; 
+Function fpFlock (var fd : File; mode : longint) : cint;
 begin
-  {$warning TODO BeOS fpFlock implementation}  
+  {$warning TODO BeOS fpFlock implementation}
 end;
 
-Function fpFlock (var fd : Text; mode : longint) : cint; 
+Function fpFlock (var fd : Text; mode : longint) : cint;
 begin
-  {$warning TODO BeOS fpFlock implementation}  
+  {$warning TODO BeOS fpFlock implementation}
 end;
 
-Function fpFlock (fd, mode : longint) : cint; 
+Function fpFlock (fd, mode : longint) : cint;
 begin
-  {$warning TODO BeOS fpFlock implementation}  
+  {$warning TODO BeOS fpFlock implementation}
 end;
 
 function snooze(microseconds : bigtime_t) : status_t; cdecl; external 'root' name 'snooze';

rtl/beos/bethreads.pp

@@ -306,12 +306,12 @@ Uses
             { No recursive mutex support :/ }
             res := pthread_mutex_init(@CS,NIL);
         end
-      else 
+      else
         res:= pthread_mutex_init(@CS,NIL);
       pthread_mutexattr_destroy(@MAttr);
       if res <> 0 then
         runerror(6);
-    end;                           
+    end;
 
     procedure BeEnterCriticalSection(var CS);
       begin
@@ -377,7 +377,7 @@ Function BeInitThreads : Boolean;
 begin
 {$ifdef DEBUG_MT}
   Writeln('Entering InitThreads.');
-{$endif}  
+{$endif}
 {$ifndef dynpthreads}
   Result:=True;
 {$else}
@@ -406,10 +406,10 @@ type
          FManualReset: Boolean;
          FEventSection: TPthreadMutex;
 	end;
-     plocaleventstate = ^tbasiceventstate;  
+     plocaleventstate = ^tbasiceventstate;
 //     peventstate=pointer;
 
-Const 
+Const
 	wrSignaled = 0;
 	wrTimeout  = 1;
 	wrAbandoned= 2;
@@ -528,7 +528,7 @@ begin
     AllocateThreadVars     :=@BeAllocateThreadVars;
     ReleaseThreadVars      :=@BeReleaseThreadVars;
 {$endif}
-    BasicEventCreate       :=@intBasicEventCreate;       
+    BasicEventCreate       :=@intBasicEventCreate;
     BasicEventDestroy      :=@intBasicEventDestroy;
     BasicEventResetEvent   :=@intBasicEventResetEvent;
     BasicEventSetEvent     :=@intBasicEventSetEvent;

rtl/beos/classes.pp

@@ -34,14 +34,14 @@ interface
 uses
   System.SysUtils,
   System.RtlConsts,
-  System.Types,  
+  System.Types,
   System.TypInfo,
   System.SortBase;
 {$ELSE FPC_DOTTEDUNITS}
 uses
   sysutils,
   rtlconsts,
-  types,  
+  types,
   typinfo,
   sortbase;
 {$ENDIF FPC_DOTTEDUNITS}

rtl/beos/errno.inc

@@ -156,7 +156,7 @@ const
   ESTALE          = B_POSIX_ERROR_BASE + 40;
   EOVERFLOW       = B_POSIX_ERROR_BASE + 41;
   EMSGSIZE        = B_POSIX_ERROR_BASE + 42;
-  EOPNOTSUPP      = B_POSIX_ERROR_BASE + 43;                      
+  EOPNOTSUPP      = B_POSIX_ERROR_BASE + 43;
   ENOTSOCK        = B_POSIX_ERROR_BASE + 44;
 
   ENOMEM       = B_NO_MEMORY;

rtl/beos/i386/sighnd.inc

@@ -30,7 +30,7 @@ begin
         // fp_status always here under BeOS and x86 CPU
         // (fp_status is not behind a pointer in the BeOS context record)
         FpuState:=ucontext^.xregs.state.old_format.fp_status;
-            
+
         if (FpuState and FPU_ExceptionMask) <> 0 then
           begin
             { first check the more precise options }
@@ -86,7 +86,7 @@ begin
   if res<>0 then
   begin
     HandleErrorAddrFrame(res, pointer(ucontext^.eip),
-                              pointer(ucontext^.ebp));    
+                              pointer(ucontext^.ebp));
   end;
 end;
 

rtl/beos/ossysc.inc

@@ -118,7 +118,7 @@ begin
   args.param[3] := flags;
   args.param[4] := cint(mode);
   args.param[5] := 0;               { close on execute flag }
-  fpopen:= SysCall(syscall_nr_open, args);   
+  fpopen:= SysCall(syscall_nr_open, args);
 {Begin
  Fpopen:=do_syscall(syscall_nr_open,TSysParam(path),TSysParam(flags),TSysParam(mode));
 }
@@ -159,7 +159,7 @@ var
 
 begin
   args.param[1] := fd;
-  args.param[2] := cint(offset and $FFFFFFFF);      
+  args.param[2] := cint(offset and $FFFFFFFF);
   args.param[3] := cint((offset shr 32) and $FFFFFFFF);
   args.param[4] := whence;
   { we currently only support seeks upto 32-bit in length }
@@ -175,15 +175,15 @@ type
   twstat = packed record
 {00}   filler : array[1..3] of longint;
 {12}   newmode : mode_t;     { chmod mode_t parameter }
-{16}   unknown1 : longint;  
-{20}   newuser : uid_t;      { chown uid_t parameter  } 
+{16}   unknown1 : longint;
+{20}   newuser : uid_t;      { chown uid_t parameter  }
 {24}   newgroup : gid_t;     { chown gid_t parameter  }
 {28}   trunc_offset : off_t; { ftrucnate parameter    }
 {36}   unknown2 : array[1..2] of longint;
-{44}   utime_param: int64;  
+{44}   utime_param: int64;
 {52}   unknown3 : array[1..2] of longint;
   end;
-  
+
 function Fpftruncate(fd : cint; flength : off_t): cint; [public, alias : 'FPC_SYSC_FTRUNCATE'];
 var
   args: SysCallArgs;
@@ -206,7 +206,7 @@ end;
 
 const
   B_OS_NAME_LENGTH = 32;
-  B_PAGE_SIZE = 4096;  
+  B_PAGE_SIZE = 4096;
 
 const
   B_NO_LOCK       = 0;
@@ -226,7 +226,7 @@ const
 
 type
   area_id   = Longint;
-  
+
 function create_area(name : PAnsiChar; var addr : longint;
   addr_typ : longint; size : longint; lock_type: longint; protection : longint): area_id;
 var
@@ -256,7 +256,7 @@ begin
   Str(len, s);
   WriteLn(s);
   myheapstart:=start;
-{$IFDEF FPC_USE_LIBC}  
+{$IFDEF FPC_USE_LIBC}
   heap_handle := create_area('fpcheap',myheapstart,0,len,0,3);//!!
 {$ELSE}
   heap_handle := create_area('fpcheap',longint(myheapstart),0,len,0,3);//!!
@@ -328,7 +328,7 @@ begin
    end
   else
    begin
-     fpwrite := -1; 
+     fpwrite := -1;
      errno := errorcode;
    end;
 {begin
@@ -934,7 +934,7 @@ extern _IMPEXP_ROOT status_t  get_nth_image_symbol(image_id imid, int32 index,
                   void **ptr);
 }
 
-// 
+//
 {$ifdef FPC_USE_LIBC}
 
 // private; use the macros, below
@@ -993,7 +993,7 @@ end;
        args.param[3] := cint(@info);
        args.param[4] := cint(sizeof(image_info));
        get_next_image_info := SysCall(syscall_nr_get_next_image_info, args);
-   end;       
+   end;
 
     function load_image(argc : longint; argv : PPAnsiChar; envp : PPAnsiChar): thread_id;
      var
@@ -1005,7 +1005,7 @@ end;
        args.param[3] := cint(envp);
        load_image := SysCall(syscall_nr_load_image, args);
      end;
-    
+
     function get_system_info(var info: system_info): status_t;
      var
       args: SysCallArgs;
@@ -1045,7 +1045,7 @@ end;
        args.param[5] := cint(@info);
        fs_stat_dev := SysCall(syscall_nr_statfs, args);
      end;
-     
+
 {$endif}
 
 

rtl/beos/ostypes.inc

@@ -13,7 +13,7 @@
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 
  **********************************************************************}
- 
+
 {***********************************************************************}
 {                         POSIX STRUCTURES                              }
 {***********************************************************************}
@@ -28,7 +28,7 @@ Type
   end;
   ptimezone =^timezone;
   TTimeZone = timezone;
-  
+
   rusage = packed record
         ru_utime    : timeval;          { user time used }
         ru_stime    : timeval;          { system time used }
@@ -77,10 +77,10 @@ CONST                		// OS specific parameters for general<fd,sig>set behaviou
 //   SIG_MAXSIG      = 32;    //128;	// highest signal version
    FD_MAXFDSET	   = 1024;
 //   wordsinsigset   = 4;		// words in sigset_t
-   ln2bitsinword   = 5;         { 32bit : ln(32)/ln(2)=5 } 
+   ln2bitsinword   = 5;         { 32bit : ln(32)/ln(2)=5 }
    ln2bitmask	   = 2 shl ln2bitsinword - 1;
-   wordsinfdset    = FD_MAXFDSET DIV BITSINWORD;        // words in fdset_t   
-   wordsinsigset   = SIG_MAXSIG  DIV BITSINWORD;      
+   wordsinfdset    = FD_MAXFDSET DIV BITSINWORD;        // words in fdset_t
+   wordsinsigset   = SIG_MAXSIG  DIV BITSINWORD;
 
 TYPE
    { system information services }
@@ -129,7 +129,7 @@ TYPE
    stat = packed record
       st_dev:longint;     {"device" that this file resides on}
       st_ino:int64;       {this file's inode #, unique per device}
-      st_mode:dword;      {mode bits (rwx for user, group, etc)}      
+      st_mode:dword;      {mode bits (rwx for user, group, etc)}
       st_nlink:longint;   {number of hard links to this file}
       st_uid:dword;       {user id of the owner of this file}
       st_gid:dword;       {group id of the owner of this file}
@@ -141,7 +141,7 @@ TYPE
       st_ctime:longint;   {last change time, not creation time}
       crtime:longint;  {creation time}
    end;
-   
+
    TStat = stat;
    pStat = ^stat;
 
@@ -215,7 +215,7 @@ TYPE
  TTms= tms;
  pTms= ^tms;
 
- TFDSetEl  = Cardinal; 
+ TFDSetEl  = Cardinal;
  TFDSet    = ARRAY[0..(FD_MAXFDSET div 32)-1] of TFDSetEl;
  pFDSet    = ^TFDSet;
 
@@ -264,11 +264,11 @@ CONST
     WNOHANG   =          1;     { don't block waiting               }
     WUNTRACED =          2;     { report status of stopped children }
 
-Type 
+Type
         TRLimit  = record
                      rlim_cur,               { current (soft) limit }
           	     rlim_max : TRLim;     { maximum value for rlim_cur }
-		    end;	
+		    end;
         PRLimit  = ^TRLimit;
 
  iovec = record
@@ -276,7 +276,7 @@ Type
 	    iov_len  : size_t;
 	   end;
   tiovec=iovec;
-  piovec=^tiovec;		
+  piovec=^tiovec;
 
 
     {*************************************************************************}
@@ -334,7 +334,7 @@ const
    B_SYSTEM_IMAGE  = 4;
 type
     image_info = packed record
-     id      : image_id;   
+     id      : image_id;
      _type   : longint;
      sequence: longint;
      init_order: longint;
@@ -354,7 +354,7 @@ type
      text_size: longint;
      data_size: longint;
     end;
-    
+
 (*----- symbol types and functions ------------------------*)
 
 const B_SYMBOL_TYPE_DATA = $1;

rtl/beos/ptypes.inc

@@ -71,11 +71,11 @@ type
     size_t   = cuint32;         { as defined in the C standard}
     TSize    = size_t;
     pSize    = ^size_t;
-    psize_t   = pSize;		
+    psize_t   = pSize;
 
     ssize_t  = cint32;          { used by function for returning number of bytes }
     TsSize   = ssize_t;
-    psSize   = ^ssize_t;		
+    psSize   = ^ssize_t;
 
     uid_t    = cuint32;         { used for user ID type        }
     TUid     = Uid_t;
@@ -90,7 +90,7 @@ type
     // TTime    = time_t;    // Not allowed in system unit, -> unixtype
     pTime    = ^time_t;
     ptime_t =  ^time_t;
-    
+
     wchar_t   = cint32;
     pwchar_t  = ^wchar_t;
 
@@ -110,9 +110,9 @@ type
   end;
   ptimespec= ^timespec;
   Ttimespec= timespec;
-  
+
   pthread_t = culong;
-  
+
   sched_param = record
     __sched_priority: cint;
   end;
@@ -152,7 +152,7 @@ type
     __padding: array[0..48-1-sizeof(_pthread_fastlock)-sizeof(pointer)-sizeof(clonglong)] of byte;
     __align: clonglong;
   end;
-    
+
   pthread_condattr_t = record
     __dummy: cint;
   end;
@@ -172,7 +172,7 @@ type
     __lockkind: cint;
     __pshared: cint;
   end;
-  
+
   sem_t = record
      __sem_lock: _pthread_fastlock;
      __sem_value: cint;
@@ -188,7 +188,7 @@ CONST
     _PTHREAD_MUTEX_RECURSIVE_NP  = 1;
     _PTHREAD_MUTEX_ERRORCHECK_NP = 2;
     _PTHREAD_MUTEX_ADAPTIVE_NP   = 3;
-  
+
     _PTHREAD_MUTEX_NORMAL     = _PTHREAD_MUTEX_TIMED_NP;
     _PTHREAD_MUTEX_RECURSIVE  = _PTHREAD_MUTEX_RECURSIVE_NP;
     _PTHREAD_MUTEX_ERRORCHECK = _PTHREAD_MUTEX_ERRORCHECK_NP;
@@ -205,8 +205,8 @@ CONST
     PATH_MAX = 1024;    {255}   { Maximum number of bytes in pathname }
 
     SYS_NMLN = 32;              {BSD utsname struct limit}
-    
-    SIG_MAXSIG = 32; //128;	// highest signal version  // BeOS  
+
+    SIG_MAXSIG = 32; //128;	// highest signal version  // BeOS
 
 const
   { For getting/setting priority }

rtl/beos/settimeo.inc

@@ -22,7 +22,7 @@
 {$ifdef FPC_USE_LIBC}
 function stime (t:ptime_t):cint; cdecl; external name 'stime';
 {$else}
-function stime (t:ptime_t):cint; 
+function stime (t:ptime_t):cint;
 begin
  stime:=do_SysCall(Syscall_nr_stime,TSysParam(t));
 end;

rtl/beos/signal.inc

@@ -16,7 +16,7 @@
 Const   { For sending a signal }
 
   SA_NOCLDSTOP = 1;
-  
+
   // does not exist under BeOS i think !
   SA_ONSTACK   = $001; { take signal on signal stack }
   SA_RESTART   = $002; { restart system call on signal return }
@@ -32,10 +32,10 @@ Const   { For sending a signal }
 
 {BeOS Checked}
 {
-   The numbering of signals for BeOS attempts to maintain 
-   some consistency with UN*X conventions so that things 
+   The numbering of signals for BeOS attempts to maintain
+   some consistency with UN*X conventions so that things
    like "kill -9" do what you expect.
-}   
+}
 
   SIG_DFL = 0 ;
   SIG_IGN = 1 ;
@@ -64,7 +64,7 @@ Const   { For sending a signal }
   SIGKILLTHR = 21;
   SIGTRAP    = 22;
   SIGBUS     = SIGSEGV;
-  
+
 {
    Signal numbers 23-32 are currently free but may be used in future
    releases.  Use them at your own peril (if you do use them, at least
@@ -80,7 +80,7 @@ const
  * those in mcontext_t.
  }
 
-type 
+type
   packed_fp_stack = packed record
     st0 : array[0..9] of byte;
     st1 : array[0..9] of byte;
@@ -88,10 +88,10 @@ type
     st3 : array[0..9] of byte;
     st4 : array[0..9] of byte;
     st5 : array[0..9] of byte;
-    st6 : array[0..9] of byte;    
-    st7 : array[0..9] of byte;    
+    st6 : array[0..9] of byte;
+    st7 : array[0..9] of byte;
   end;
-  
+
   packed_mmx_regs = packed record
     mm0 : array[0..9] of byte;
     mm1 : array[0..9] of byte;
@@ -99,10 +99,10 @@ type
     mm3 : array[0..9] of byte;
     mm4 : array[0..9] of byte;
     mm5 : array[0..9] of byte;
-    mm6 : array[0..9] of byte;    
-    mm7 : array[0..9] of byte;    
+    mm6 : array[0..9] of byte;
+    mm7 : array[0..9] of byte;
   end;
-  
+
   old_extended_regs = packed record
     fp_control 	: word;
     _reserved1 	: word;
@@ -122,7 +122,7 @@ type
         1 : (mmx	: packed_mmx_regs);
     end;
   end;
-  
+
   fp_stack = record
     st0 : array[0..9] of byte;
     _reserved_42_47 : array[0..5] of byte;
@@ -136,12 +136,12 @@ type
     _reserved_106_111 : array[0..5] of byte;
     st5 : array[0..9] of byte;
     _reserved_122_127 : array[0..5] of byte;
-    st6 : array[0..9] of byte;    
+    st6 : array[0..9] of byte;
     _reserved_138_143 : array[0..5] of byte;
-    st7 : array[0..9] of byte;        
+    st7 : array[0..9] of byte;
     _reserved_154_159 : array[0..5] of byte;
   end;
-  
+
   mmx_regs = record
     mm0 : array[0..9] of byte;
     _reserved_42_47 : array[0..5] of byte;
@@ -155,12 +155,12 @@ type
     _reserved_106_111 : array[0..5] of byte;
     mm5 : array[0..9] of byte;
     _reserved_122_127 : array[0..5] of byte;
-    mm6 : array[0..9] of byte;    
+    mm6 : array[0..9] of byte;
     _reserved_138_143 : array[0..5] of byte;
-    mm7 : array[0..9] of byte;    
+    mm7 : array[0..9] of byte;
     _reserved_154_159 : array[0..5] of byte;
   end;
-  
+
   xmmx_regs = record
     xmm0 : array [0..15] of byte;
     xmm1 : array [0..15] of byte;
@@ -171,7 +171,7 @@ type
     xmm6 : array [0..15] of byte;
     xmm7 : array [0..15] of byte;
   end;
-  
+
   new_extended_regs = record
     fp_control 	: word;
     fp_status 	: word;
@@ -193,16 +193,16 @@ type
     xmmx : xmmx_regs;
     _reserved_288_511 : array[0..223] of byte;
   end;
-  
+
   extended_regs = record
     state : record
       case byte of
   	    0 : (old_format : old_extended_regs);
-  	    1 : (new_format : new_extended_regs);  	  
+  	    1 : (new_format : new_extended_regs);
   	end;
   	format	: Cardinal;
   end;
-  
+
   vregs = record
     eip 	: Cardinal;
     eflags 	: cardinal;
@@ -215,7 +215,7 @@ type
     xregs	: extended_regs;
     _reserved_2 : array[0..2] of Cardinal;
   end;
-  
+
   Pvregs = ^vregs;
 
   sigset_t = array[0..3] of Longint;
@@ -261,7 +261,7 @@ type
        fpr_ex_sw    : cardinal;
        fpr_pad      : array[0..63] of AnsiChar;
        end;
-       
+
   SignalHandler   = Procedure(Sig : Longint);cdecl;
   PSignalHandler  = ^SignalHandler;
   SignalRestorer  = Procedure;cdecl;

rtl/beos/suuid.inc

@@ -1,4 +1,4 @@
-Const 
+Const
   RandomDevice  = '/dev/urandom';
 
 
@@ -7,7 +7,7 @@ Function GetURandomBytes(Var Buf; NBytes : Integer) : Boolean;
 Var
   fd,I : Integer;
   P : PByte;
-  
+
 begin
   P:=@Buf;
   fd:=FileOpen(RandomDevice,fmOpenRead);
@@ -22,7 +22,7 @@ begin
           Inc(P,I);
           Dec(NBytes,I);
           end;
-        end;  
+        end;
     Finally
       FileClose(Fd);
     end;
@@ -33,6 +33,6 @@ Function SysCreateGUID(out GUID : TGUID) : Integer;
 
 begin
   if not GetUrandomBytes(Guid,SizeOf(GUID)) then
-    GetRandomBytes(GUID,SizeOf(Guid));  
-  Result:=0;    
+    GetRandomBytes(GUID,SizeOf(Guid));
+  Result:=0;
 end;

rtl/beos/syscall.inc

@@ -16,12 +16,12 @@
 
  **********************************************************************}
 
-// Under BeOS, we use stdcall for this line because the default calling convention in 1.9 
+// Under BeOS, we use stdcall for this line because the default calling convention in 1.9
 // is register instead of stdcall. But assembler is already written, so i used the stdcall
 // calling convention !
 function Do_SysCall( callnr : longint; var regs : SysCallArgs ): longint; stdcall; assembler; [public, alias : 'FPC_SYSCALL'];
 {
-  This routine sets up the parameters on the stack, all the parameters 
+  This routine sets up the parameters on the stack, all the parameters
   are in reverse order on the stack (like C parameter passing).
 }
 asm
@@ -30,7 +30,7 @@ asm
   movl  24(%eax),%ebx
   pushl %ebx
   movl  20(%eax),%ebx
-  pushl %ebx 
+  pushl %ebx
   movl  16(%eax),%ebx
   pushl %ebx
   movl  12(%eax),%ebx
@@ -47,7 +47,7 @@ asm
   addl  $28,%esp
 end;
 
-// Under BeOS, we use stdcall for this line because the default calling convention in 1.9 
+// Under BeOS, we use stdcall for this line because the default calling convention in 1.9
 // is register instead of stdcall. But assembler is already written, so i used the stdcall
 // calling convention ! Maybe don't needed here. But to be sure...
 Function SysCall( callnr:longint;var args : SysCallArgs ):longint; stdcall;

rtl/beos/syscallh.inc

@@ -24,7 +24,7 @@ Type
 // 64-bit machines don't have only 64-bit params.
 
   TSysParam  = longint;
-  
+
 type
      SysCallArgs = packed record
        param: array[1..8] of longint; // cint but not defined in unix.pp
@@ -33,7 +33,7 @@ type
 {$IFDEF FPC_USE_LIBC}
 //var
 //  Errno : cint;
-  
+
 {$else}
 //var
 //  Errno : cint;
@@ -43,6 +43,6 @@ procedure sys_call; external name 'sys_call'; // BeOS
 //begin
 //end;
 
-  
+
 //function Do_SysCall( callnr : longint; var regs : SysCallArgs ): longint; external name 'FPC_SYSCALL';//forward;
 //Function SysCall( callnr:longint;var args : SysCallArgs ):longint; external name 'sys_call';//forward;

rtl/beos/sysnr.inc

@@ -13,10 +13,10 @@ const
       syscall_nr_kget_tzfilename = $AF;
       syscall_nr_get_next_image_info = $3C;
 
-const           
+const
       syscall_nr_exit   		= $3F;
-      syscall_nr_chdir  		= $57; 
-      syscall_nr_mkdir  		= $1E; 
+      syscall_nr_chdir  		= $57;
+      syscall_nr_mkdir  		= $1E;
       syscall_nr_unlink 		= $27;
       syscall_nr_rmdir  		= $60;
       syscall_nr_close  		= $01;

rtl/beos/termios.inc

@@ -182,7 +182,7 @@ CRTSCTS		= RTSFLOW or CTSFLOW;
  * the letter "I" and look like they belong in the
  * input flag.
  }
- 
+
 {
   c_lflag - local modes
 }
@@ -205,7 +205,7 @@ EV_RING			= $0001;
 EV_BREAK		= $0002;
 EV_CARRIER		= $0004;
 EV_CARRIERLOST	= $0008;
- 
+
 {
  * Commands passed to tcsetattr() for setting the termios structure.
 }
@@ -215,7 +215,7 @@ CONST
         TCSANOW         = $01;             { make change immediate }
         TCSADRAIN       = $02;             { drain output, then change }
         TCSAFLUSH       = $04;             { drain output, flush input }
-        
+
         // TCASOFT undefined under BeOS
         TCSASOFT        = $10;           { flag - don't alter h.w. state }
 
@@ -293,7 +293,7 @@ struct winsize {
 	                                                { 127-124 compat }
 
 // BeOS values
-		TIOCGETA		= $8000;		
+		TIOCGETA		= $8000;
 		TIOCSETA		= TIOCGETA + 1;
 		TIOCSETAF		= TIOCGETA + 2;
 		TIOCSETAW		= TIOCGETA + 3;
@@ -308,11 +308,11 @@ struct winsize {
 		TIOCGWINSZ		= TIOCGETA + 12;
 		TIOCSWINSZ		= TIOCGETA + 13;
 		TCVTIME			= TIOCGETA + 14;
-		
-		
+
+
 //		TIOCTIMESTAMP 	= TCVTIME;
 // end BeOS values
-(*		      
+(*
 //        TIOCSBRK         =IOCTLVOID+$7400+ 123;         { set break bit }
         TIOCCBRK         =IOCTLVOID+$7400+ 122;         { clear break bit }
 //        TIOCSDTR         =IOCTLVOID+$7400+ 121;         { set data terminal ready }
@@ -417,7 +417,7 @@ struct winsize {
 
 {
   According to posix/sys/ioctl.h
-  /* these currently work only on sockets */	
+  /* these currently work only on sockets */
 }
 	FIONBIO  = $be000000;
 	FIONREAD = $be000001;

rtl/beos/termiosproc.inc

@@ -46,7 +46,7 @@ end;
 Procedure CFSetISpeed(var tios:TermIOS;speed:Cardinal);
 begin
   // field unused under BeOS
-  tios.c_ixxxxx:=speed; 
+  tios.c_ixxxxx:=speed;
 end;
 
 

rtl/beos/tthread.inc

@@ -287,14 +287,14 @@ end;
   What follows, is a short description on my implementation of TThread.
   Most information can also be found by reading the source and accompanying
   comments.
-  
+
   A thread is created using BeginThread, which in turn calls
   pthread_create. So the threads here are always posix threads.
   Posix doesn't define anything for suspending threads as this is
   inherintly unsafe. Just don't suspend threads at points they cannot
   control. Therefore, I didn't implement .Suspend() if its called from
   outside the threads execution flow (except on Linux _without_ NPTL).
-  
+
   The implementation for .suspend uses a semaphore, which is initialized
   at thread creation. If the thread tries to suspend itself, we simply
   let it wait on the semaphore until it is unblocked by someone else
@@ -305,7 +305,7 @@ end;
   are possible.
   1) the system has the LinuxThreads pthread implementation
   2) the system has NPTL as the pthread implementation.
-  
+
   In the first case, each thread is a process on its own, which as far as
   know actually violates posix with respect to signal handling.
   But we can detect this case, because getpid(2) will
@@ -316,10 +316,10 @@ end;
   PID across all threads, which is detected, and TThread.Suspend() does
   nothing in that case. This should probably be changed, but I know of
   no way to suspend a thread when using NPTL.
-  
+
   If the symbol LINUX is not defined, then the unimplemented
   function SuspendThread is called.
-  
+
   Johannes Berg <[email protected]>, Sunday, November 16 2003
 }
 

rtl/beos/unxconst.inc

@@ -60,8 +60,8 @@ CONST
   STAT_ISUID  = $0800; {0004000 }
   STAT_ISGID  = $0400; {0002000 }
   STAT_ISVTX  = $0200; {0001000}
-    
-    
+
+
     STAT_IRUSR =  %0100000000;     { Read permission for owner   }
     STAT_IWUSR =  %0010000000;     { Write permission for owner  }
     STAT_IXUSR =  %0001000000;     { Exec  permission for owner  }

rtl/beos/unxfunc.inc

@@ -47,7 +47,7 @@ end;
 
 // can't have oldfpccall here, linux doesn't need it.
 Function AssignPipe(var pipe_in,pipe_out:cint):cint; [public, alias : 'FPC_SYSC_ASSIGNPIPE'];
-{ 
+{
   Sets up a pair of file variables, which act as a pipe. The first one can
   be read from, the second one can be written to.
   If the operation was unsuccesful, linuxerror is set.

rtl/bsd/bsd.pas

@@ -3,7 +3,7 @@ Unit BSD;
 {$ENDIF FPC_DOTTEDUNITS}
 {
    This file is part of the Free Pascal run time library.
-   (c) 2005 by Marco van de Voort member of the 
+   (c) 2005 by Marco van de Voort member of the
    Free Pascal development team.
    Original kqueue implementation converted by Ales Katona 30.01.2006
 
@@ -11,8 +11,8 @@ Unit BSD;
    for details about the copyright.
 
    This unit is meant to contain all BSD specific routines. Not all
-   routines might be implemented on all BSD platforms. 
- 
+   routines might be implemented on all BSD platforms.
+
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY;without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
@@ -58,20 +58,20 @@ const
   EV_DELETE       = $0002;  { delete event from kq  }
   EV_ENABLE       = $0004;  { enable event  }
   EV_DISABLE      = $0008;  { disable event (not reported)  }
-  
+
 { flags  }
   EV_ONESHOT      = $0010;  { only report one occurrence  }
   EV_CLEAR        = $0020;  { clear event state after reporting  }
   EV_SYSFLAGS     = $F000;  { reserved by system  }
   EV_FLAG1        = $2000;  { filter-specific flag  }
-  
+
 { returned values  }
   EV_EOF          = $8000;  { EOF detected  }
   EV_ERROR        = $4000;  { error, data contains errno  }
-  
+
 { data/hint flags for EVFILT_READ|WRITE, shared with userspace   }
   NOTE_LOWAT      = $0001;  { low water mark  }
-  
+
 { data/hint flags for EVFILT_VNODE, shared with userspace  }
   NOTE_DELETE     = $0001;  { vnode was removed  }
   NOTE_WRITE      = $0002;  { data contents changed  }
@@ -80,19 +80,19 @@ const
   NOTE_LINK       = $0010;  { link count changed  }
   NOTE_RENAME     = $0020;  { vnode was renamed  }
   NOTE_REVOKE     = $0040;  { vnode access was revoked  }
-  
+
 { data/hint flags for EVFILT_PROC, shared with userspace   }
   NOTE_EXIT       = $80000000;  { process exited  }
   NOTE_FORK       = $40000000;  { process forked  }
   NOTE_EXEC       = $20000000;  { process exec'd  }
   NOTE_PCTRLMASK  = $f0000000;  { mask for hint bits  }
   NOTE_PDATAMASK  = $000fffff;  { mask for pid  }
-  
+
 { additional flags for EVFILT_PROC  }
   NOTE_TRACK      = $00000001;  { follow across forks  }
   NOTE_TRACKERR   = $00000002;  { could not track child  }
   NOTE_CHILD      = $00000004;  { am a child process  }
-  
+
 { data/hint flags for EVFILT_NETDEV, shared with userspace  }
   NOTE_LINKUP     = $0001;  { link is up  }
   NOTE_LINKDOWN   = $0002;  { link is down  }
@@ -110,7 +110,7 @@ type
   end;
 
 function kqueue: cint; extdecl;
-  
+
 function kevent(kq: cint; ChangeList: PKEvent; nChanged: cint;
                   EventList: PKevent; nEvents: cint; Timeout: PTimeSpec): cint; extdecl;
 

rtl/bsd/ossysc.inc

@@ -83,7 +83,7 @@ begin
     Fplseek:=do_syscall(syscall_nr___syscall,syscall_nr_lseek,TSysParam(fd),0,Offset,whence);
     {$endif}
   {$else}
-    {$ifdef freebsd}    
+    {$ifdef freebsd}
     Fplseek:=do_syscall(syscall_nr___syscall,syscall_nr_lseek,0,TSysParam(fd),
     {$else}
     Fplseek:=do_syscall(syscall_nr___syscall,syscall_nr_lseek,0,TSysParam(fd),0,
@@ -130,7 +130,7 @@ begin
   Fpmmap:=pointer(ptruint(do_syscall(syscall_nr_mmap,TSysParam(Start),Len,Prot,Flags,fd,
  {$else}
   Fpmmap:=pointer(ptruint(do_syscall(syscall_nr_mmap,TSysParam(Start),Len,Prot,Flags,fd,0,
- {$endif} 
+ {$endif}
          {$ifdef FPC_BIG_ENDIAN}    hi(offst),lo(offst){$endif}
          {$ifdef FPC_LITTLE_ENDIAN} lo(offst),hi(offst){$endif}
          )));

rtl/bsd/ostypes.inc

@@ -329,7 +329,7 @@ TYPE
  TTms= tms;
  pTms= ^tms;
 
- TFDSetEl  = Cardinal; 
+ TFDSetEl  = Cardinal;
  TFDSet    = ARRAY[0..(FD_MAXFDSET div 32)-1] of TFDSetEl;
  pFDSet    = ^TFDSet;
 
@@ -554,7 +554,7 @@ Type
         TRLimit  = record
                      rlim_cur,               { current (soft) limit }
           	     rlim_max : TRLim;     { maximum value for rlim_cur }
-		    end;	
+		    end;
         PRLimit  = ^TRLimit;
 
   iovec = record
@@ -562,7 +562,7 @@ Type
 	    iov_len  : size_t;
 	   end;
   tiovec=iovec;
-  piovec=^tiovec;		
+  piovec=^tiovec;
 
 CONST
  { Constants for MMAP }

rtl/bsd/suuid.inc

@@ -15,7 +15,7 @@
 
  **********************************************************************}
 
-{$IF DEFINED(FREEBSD) AND NOT DEFINED(FREEBSD4)} 
+{$IF DEFINED(FREEBSD) AND NOT DEFINED(FREEBSD4)}
 {$IFDEF FPC_USE_LIBC}
 
 function cuuidgen(p:PGUID;x:cint):cint; external clib name 'uuidgen';
@@ -34,12 +34,12 @@ Function SysCreateGUID(out GUID : TGUID) : Integer;
 begin
  result:=0;
  if cuuidgen(@guid,1)=-1 then
-    GetRandomBytes(GUID,SizeOf(Guid));  
+    GetRandomBytes(GUID,SizeOf(Guid));
 end;
 
 {$ELSE}
 
-Const 
+Const
   RandomDevice  = '/dev/urandom';
 
 
@@ -48,7 +48,7 @@ Function GetURandomBytes(Var Buf; NBytes : Integer) : Boolean;
 Var
   fd,I : Integer;
   P : PByte;
-  
+
 begin
   P:=@Buf;
   fd:=FileOpen(RandomDevice,fmOpenRead or fmShareDenyNone);
@@ -63,7 +63,7 @@ begin
           Inc(P,I);
           Dec(NBytes,I);
           end;
-        end;  
+        end;
     Finally
       FileClose(Fd);
     end;
@@ -74,7 +74,7 @@ Function SysCreateGUID(out GUID : TGUID) : Integer;
 
 begin
   if not GetUrandomBytes(Guid,SizeOf(GUID)) then
-    GetRandomBytes(GUID,SizeOf(Guid));  
-  Result:=0;    
+    GetRandomBytes(GUID,SizeOf(Guid));
+  Result:=0;
 end;
 {$ENDIF}

rtl/darwin/errno.inc

@@ -285,7 +285,7 @@
     { Identifier removed }
        ESysEIDRM = 90;
     { No message of desired type }
-       ESysENOMSG = 91;   
+       ESysENOMSG = 91;
     { Illegal byte sequence }
        ESysEILSEQ = 92;
     { Attribute not found }

rtl/darwin/errnostr.inc

@@ -122,4 +122,4 @@ const
         'llegal byte sequence',                                  { EILSEQ }
         'Attribute not found'                                      { ENOATTR }
 );
- 
+

rtl/darwin/extres_multiarch.inc

@@ -547,7 +547,7 @@ begin
 
   tot:=ptr^.idcountsize;
   ptr:=GetResInfoPtr(ResHeader,ptr^.subptr);
-  
+
   if Other<>nil then
   begin
     otarr:=InternalFindResource(Other,ResourceName,ResourceType);

rtl/darwin/sysctlh.inc

@@ -368,7 +368,7 @@
        VM_METER = 1;
     { struct loadavg  }
        VM_LOADAVG = 2;
-    {  Note: "3" was skipped sometime ago and should probably remain unused 
+    {  Note: "3" was skipped sometime ago and should probably remain unused
              to avoid any new entry from being accepted by older kernels...}
     { struct loadavg with mach factor }
        VM_MACHFACTOR = 4;

rtl/darwin/termios.inc

@@ -569,8 +569,8 @@ Type
 
 
 // from /usr/include/sys/iocomm.h
-  { parameter length, at most 13 bits } 
-  IOCPARM_MASK = $1fff; 
+  { parameter length, at most 13 bits }
+  IOCPARM_MASK = $1fff;
 
   {  max size of ioctl args  }
   IOCPARM_MAX = IOCPARM_MASK + 1;

rtl/darwin/x86/sig_x86.inc

@@ -8,13 +8,13 @@
    * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
    *
    * @APPLE_LICENSE_HEADER_START@
-   * 
+   *
    * The contents of this file constitute Original Code as defined in and
    * are subject to the Apple Public Source License Version 1.1 (the
    * "License").  You may not use this file except in compliance with the
    * License.  Please obtain a copy of the License at
    * http://www.apple.com/publicsource and read it before using this file.
-   * 
+   *
    * This Original Code and all software distributed under the License are
    * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
    * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
@@ -22,34 +22,34 @@
    * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
    * License for the specific language governing rights and limitations
    * under the License.
-   * 
+   *
    * @APPLE_LICENSE_HEADER_END@
     }
   {
    * @OSF_COPYRIGHT@
     }
-  { 
+  {
    * Mach Operating System
    * Copyright (c) 1991,1990,1989 Carnegie Mellon University
    * All Rights Reserved.
-   * 
+   *
    * Permission to use, copy, modify and distribute this software and its
    * documentation is hereby granted, provided that both the copyright
    * notice and this permission notice appear in all copies of the
    * software, derivative works or modified versions, and any portions
    * thereof, and that both notices appear in supporting documentation.
-   * 
+   *
    * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
    * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
    * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
-   * 
+   *
    * Carnegie Mellon requests users of this software to return to
-   * 
+   *
    *  Software Distribution Coordinator  or  [email protected]
    *  School of Computer Science
    *  Carnegie Mellon University
    *  Pittsburgh PA 15213-3890
-   * 
+   *
    * any improvements or extensions that they make and grant Carnegie Mellon
    * the rights to redistribute these changes.
     }
@@ -69,8 +69,8 @@
    *				calls.  This structure should never
    *				change.
    *
-   *	i386_float_state	exported to use threads for access to 
-   *				floating point registers. Try not to 
+   *	i386_float_state	exported to use threads for access to
+   *				floating point registers. Try not to
    *				change this one, either.
    *
     }
@@ -78,10 +78,10 @@
 
 {
   const
-     i386_THREAD_STATE = 1;     
-     i386_FLOAT_STATE = 2;     
-     i386_EXCEPTION_STATE = 3;     
-     THREAD_STATE_NONE = 4;     
+     i386_THREAD_STATE = 1;
+     i386_FLOAT_STATE = 2;
+     i386_EXCEPTION_STATE = 3;
+     THREAD_STATE_NONE = 4;
 }
   {
    * Main thread state consists of
@@ -142,17 +142,17 @@
     }
 
   const
-     USER_CODE_SELECTOR = $0017;     
-     USER_DATA_SELECTOR = $001f;     
-     KERN_CODE_SELECTOR = $0008;     
-     KERN_DATA_SELECTOR = $0010;     
-     FP_PREC_24B = 0;     
-     FP_PREC_53B = 2;     
-     FP_PREC_64B = 3;     
-     FP_RND_NEAR = 0;     
-     FP_RND_DOWN = 1;     
-     FP_RND_UP = 2;     
-     FP_CHOP = 3;     
+     USER_CODE_SELECTOR = $0017;
+     USER_DATA_SELECTOR = $001f;
+     KERN_CODE_SELECTOR = $0008;
+     KERN_DATA_SELECTOR = $0010;
+     FP_PREC_24B = 0;
+     FP_PREC_53B = 2;
+     FP_PREC_64B = 3;
+     FP_RND_NEAR = 0;
+     FP_RND_DOWN = 1;
+     FP_RND_UP = 2;
+     FP_CHOP = 3;
 
   type
 
@@ -290,13 +290,13 @@
           xmm_reg : array[0..15] of byte;
        end;
 
-  { 
+  {
    * Floating point state.
     }
   { number of chars worth of data from fpu_fcw  }
 
   const
-     FP_STATE_BYTES = 512;     
+     FP_STATE_BYTES = 512;
   { For legacy reasons we need to leave the hw_state as char bytes  }
   { x87 FPU control word  }
   { x87 FPU status word  }

rtl/dragonfly/ptypes.inc

@@ -22,7 +22,7 @@
 {$I ctypes.inc}
 {$packrecords c}
 
-const 
+const
     SEM_SAFE=255;
 type
 
@@ -125,7 +125,7 @@ type
    pthread_key_t        = cint;
    pthread_rwlock_t     = ^pthread_rwlock_t_rec;
    pthread_rwlockattr_t = ^pthread_rwlockattr_t_rec;
-  
+
    psem_t = ^sem_t;
    ppsem_t= ^psem_t;
    semid_t= pointer;
@@ -173,7 +173,7 @@ type
 
 Const
      MNAMELEN   = 80;
-     MFSNAMELEN = 16;	
+     MFSNAMELEN = 16;
 
 Type TStatFS = Record
         spare2       : clong;          { placeholder }
@@ -199,7 +199,7 @@ Type TStatFS = Record
         fspares2     : cshort;         { unused spare }
         fspares3     : clong;          { unused spare }
         fspares4     : clong;          { unused spare }
-     end; 
+     end;
      PStatFS=^TStatFS;
 
   mbstate_t = record

rtl/dragonfly/sysnr.inc

@@ -29,7 +29,7 @@ const
  syscall_nr_chmod                       =  15;
  syscall_nr_chown                       =  16;
  syscall_nr_break                       =  17;
- syscall_nr_getfsstat                   =  18;  
+ syscall_nr_getfsstat                   =  18;
                                         {  19  is old lseek }
  syscall_nr_getpid                      =  20;
  syscall_nr_mount                       =  21;

rtl/dragonfly/termios.inc

@@ -322,9 +322,9 @@ struct winsize {
  	FIONBIO          = IOCTLWRITE+$46600+126;     { set/clear non-blocking i/o }
  	FIOASYNC         = IOCTLWRITE+$46600+125;     { set/clear async i/o }
  	FIOSETOWN        = IOCTLWRITE+$46600+124;     { set owner }
- 	FIOGETOWN        = IOCTLREAD +$46600+123;     { get owner }  
- 	FIODTYPE         = IOCTLREAD +$46600+122;     { get d_flags type part }         
- 	FIOGETLBA        = IOCTLREAD +$46600+121;     { get start blk # }                 
+ 	FIOGETOWN        = IOCTLREAD +$46600+123;     { get owner }
+ 	FIODTYPE         = IOCTLREAD +$46600+122;     { get d_flags type part }
+ 	FIOGETLBA        = IOCTLREAD +$46600+121;     { get start blk # }
 
 {
  * Defaults on "first" open.

rtl/dragonfly/termiosproc.inc

@@ -31,7 +31,7 @@ begin
   case OptAct of
   {the three constants TIOCSETA, TIOCSETAW and TIOCSETAF are
    unsigned values above $80000000, so that they give range check errors
-   on 32-bit systems 
+   on 32-bit systems
    Solved by using TIoCtlRequest type for FpIOCtl second parameter }
    TCSANOW   : nr:=TIOCSETA;
    TCSADRAIN : nr:=TIOCSETAW;
@@ -107,7 +107,7 @@ begin
   TCDrain:=fpIOCtl(fd,TIOCDRAIN,nil); {Should set timeout to 1 first?}
 end;
 
-const 
+const
    _POSIX_VDISABLE = $ff;
 
 Function TCFlow(fd,act:cint):cint; {$ifdef VER2_0}inline;{$endif}
@@ -123,12 +123,12 @@ begin
      TCIOFF :  begin
 	         if tcgetattr(fd, term) = -1 then
                         exit(-1);
-                 if act=TCIOFF then  
+                 if act=TCIOFF then
                    tmp:=VSTOP
                  else
                    tmp:=VSTART;
                  c:=term.c_cc[tmp];
-                 if (c <> _POSIX_VDISABLE) and 
+                 if (c <> _POSIX_VDISABLE) and
 			(fpwrite(fd, c, sizeof(c)) = -1) then
                    exit (-1);
                 TCFlow:=0;

rtl/dragonfly/x86_64/si_c.inc

@@ -2,13 +2,13 @@
 Type
     TCleanup = procedure; cdecl;
 
-var 
+var
   environ : PPAnsiChar; cvar; public  name '__environ';
   progname: PAnsiChar = #0#0; cvar; public name '__progname';
   dynamic : PAnsiChar;  external name '_DYNAMIC'; // #pragma weak
 
 procedure atexit(prc:TCleanup); cdecl external name 'atexit';
-procedure cleanup(prc:TCleanup); cdecl external name 'cleanup';			
+procedure cleanup(prc:TCleanup); cdecl external name 'cleanup';
 procedure init_tls; cdecl; external name 'init_tls';
 procedure fini; cdecl; external name '_fini';
 procedure init; cdecl; external name '_init';
@@ -19,8 +19,8 @@ function  main(nrarg:longint;pp:PPAnsiChar;env:PPAnsiChar):longint; cdecl; exter
  procedure cmcleanup; cdecl; external name '_mcleanup';
  procedure monstratup(p,p2:pointer); cdecl; external name 'monstartup';
 
-var 
- eprol:longint; external name 'eprol'; 
+var
+ eprol:longint; external name 'eprol';
  etext:longint; external name 'etext';
 {$endif}
 
@@ -31,7 +31,7 @@ var argc: longint;
     env : PPAnsiChar;
     s   : PAnsiChar;
 begin
-  argc:=plongint(ap)^; 
+  argc:=plongint(ap)^;
   argv:=PPAnsiChar(ap[1]);
   env:=	PPAnsiChar(ap[2+argc]);
   environ:=env;
@@ -44,7 +44,7 @@ begin
           if s^='/' then
             progname:=@s[1];
           inc(s);
-	end; 
+	end;
     end;
   if assigned(PAnsiChar(@dynamic)) then // I suspect this is a trick to find
 				    // out runtime if we are shared
@@ -59,13 +59,13 @@ begin
   atexit(@fini);
   {$ifdef GCRT}
     monstartup(@eprol,@etext);
-  {$endif} 
+  {$endif}
   init;
   {$ifdef GCRT}
    asm
     eprol:
    end;
-  {$endif} 
+  {$endif}
 
   libc_exit(main(argc,argv,env)); // doesn't return
  asm
@@ -75,7 +75,7 @@ begin
     .section ".note.ABI-tag", "a"
     .align 4
     .long 10
-    .long 4 
+    .long 4
     .long  1
     .asciz "DragonFly"
     .align 4

rtl/dragonfly/x86_64/signal.inc

@@ -173,7 +173,7 @@ type sigset_t = array[0..3] of Longint;
     Sa_Mask     : TSigSet;
   end;
   PSigActionRec = ^SigActionRec;
-  
+
 
   pstack_t = ^stack_t;
   stack_t = record

rtl/embedded/arm/allwinner_a20.pp

@@ -111,7 +111,7 @@ unit allwinner_a20;
 
     var
       _stack_top: record end; external name '_stack_top';
-      
+
     procedure _FPC_start; assembler; nostackframe;
       label
         _start;

rtl/embedded/arm/lm3fury.pp

@@ -1,6 +1,6 @@
 {
 Register definitions and utility code for stellaris
-Preliminary startup code 
+Preliminary startup code
 Geoffrey Barton 2010 08 01  [email protected]
 based on stm32f103 created by Jeppe Johansen 2009 - [email protected]
 }
@@ -132,7 +132,7 @@ interrupt_vectors:
   .long 0
   .long PendingSV_interrupt
   .long SysTick_interrupt
-  
+
   .long GPIO_Port_A_Interrupt
   .long GPIO_Port_B_Interrupt
   .long GPIO_Port_C_Interrupt
@@ -177,7 +177,7 @@ interrupt_vectors:
   .long 0
   .long 0
   .long Hibernation_Module_Interrupt
-  
+
   .weak NMI_interrupt
   .weak Hardfault_interrupt
   .weak MemManage_interrupt
@@ -221,7 +221,7 @@ interrupt_vectors:
   .weak Timer_3B_Interrupt
   .weak I2C1_Interrupt
   .weak Hibernation_Module_Interrupt
-  
+
   .set NMI_interrupt, Startup
   .set Hardfault_interrupt, Startup
   .set MemManage_interrupt, Startup
@@ -265,7 +265,7 @@ interrupt_vectors:
   .set Timer_3B_Interrupt, Startup
   .set I2C1_Interrupt, Startup
   .set Hibernation_Module_Interrupt, Startup
-  
+
   .text
 end;
 

rtl/embedded/arm/lm3tempest.pp

@@ -1,6 +1,6 @@
 {
 Register definitions and utility code for stellaris
-Preliminary startup code 
+Preliminary startup code
 Geoffrey Barton 2010 08 01  [email protected]
 based on stm32f103 created by Jeppe Johansen 2009 - [email protected]
 }
@@ -19,9 +19,9 @@ unit lm3tempest;
       PeripheralBase 	= $40000000;
       PPBbase		= $E0000fff;
       APBbase 		= PeripheralBase;
-      
+
 {$ifdef highspeedports}
-      portAoffset=APBbase+$58000;     
+      portAoffset=APBbase+$58000;
       portBoffset=APBbase+$59000;
       portCoffset=APBbase+$5A000;
       portDoffset=APBbase+$5B000;
@@ -30,9 +30,9 @@ unit lm3tempest;
       portGoffset=APBbase+$5E000;
       portHoffset=APBbase+$5F000;
       portJoffset=APBbase+$60000;
-      
+
 {$else}
-      portAoffset=APBbase+$4000;     
+      portAoffset=APBbase+$4000;
       portBoffset=APBbase+$5000;
       portCoffset=APBbase+$6000;
       portDoffset=APBbase+$7000;
@@ -43,7 +43,7 @@ unit lm3tempest;
       portJoffset=APBbase+$3d000;
 {$endif}
       sysconoffset=APBbase+$fe000;
-      
+
     type
       TgpioPort=record
         data:array[0..255] of dword;dir,_is,ibe,iev,im,ris,mis,icr,
@@ -74,7 +74,7 @@ unit lm3tempest;
     //  rcgc0			:dword absolute (sysconoffset+$100);
    //   rcgc1			:dword absolute (sysconoffset+$104);
     //  rcgc2			:dword absolute (sysconoffset+$108);
-	
+
   implementation
 
 procedure NMI_interrupt; external name 'NMI_interrupt';
@@ -164,7 +164,7 @@ interrupt_vectors:
   .long 0
   .long PendingSV_interrupt
   .long SysTick_interrupt
-  
+
   .long GPIO_Port_A_Interrupt
   .long GPIO_Port_B_Interrupt
   .long GPIO_Port_C_Interrupt
@@ -220,7 +220,7 @@ interrupt_vectors:
   .long I2S0_Interrupt
   .long EPI_Interrupt
   .long GPIO_Port_J_Interrupt
-  
+
   .weak NMI_interrupt
   .weak Hardfault_interrupt
   .weak MemManage_interrupt
@@ -285,7 +285,7 @@ interrupt_vectors:
   .weak I2S0_Interrupt
   .weak EPI_Interrupt
   .weak GPIO_Port_J_Interrupt
-  
+
   .set NMI_interrupt, haltproc
   .set Hardfault_interrupt, haltproc
   .set MemManage_interrupt, haltproc
@@ -350,7 +350,7 @@ interrupt_vectors:
   .set I2S0_Interrupt, haltproc
   .set EPI_Interrupt, haltproc
   .set GPIO_Port_J_Interrupt, haltproc
-  
+
   .text
 end;
 

rtl/embedded/arm/lm4f120.pp

@@ -10,7 +10,7 @@ const
  ROM_Base               = $01000000;
  SRAM_Base              = $20000000;
  Bitband_Base           = $22000000;
- 
+
  // FiRM Peripherals
  Watchdog0_Base         = $40000000;
  Watchdog1_Base         = $40001000;
@@ -30,7 +30,7 @@ const
  UART5_Base             = $40011000;
  UART6_Base             = $40012000;
  UART7_Base             = $40013000;
- 
+
  // Peripherals
  I2C0_Base              = $40020000;
  I2C1_Base              = $40021000;

rtl/embedded/arm/lpc1768.pp

@@ -969,7 +969,7 @@ Const
 Var
  LPC_SC                : TSCRegisters  Absolute (LPC_SC_BASE);
   LPC_SCB    : TSCBRegisters Absolute (LPC_SCB_BASE);
- 
+
  LPC_GPIO0             : TGPIORegisters Absolute (LPC_GPIO0_BASE);
  LPC_GPIO1             : TGPIORegisters Absolute (LPC_GPIO1_BASE);
  LPC_GPIO2             : TGPIORegisters Absolute (LPC_GPIO2_BASE);
@@ -1094,7 +1094,7 @@ interrupt_vectors:
   .long 0
   .long PendingSV_interrupt
   .long SysTick_interrupt
-  
+
   .long Watchdog_Interrupt
   .long Timer0_Interrupt
   .long Timer1_Interrupt
@@ -1130,7 +1130,7 @@ interrupt_vectors:
   .long PLL1_Interrupt
   .long USBActivity_Interrupt
   .long CanActivity_Interrupt
-  
+
   .weak NMI_interrupt
   .weak Hardfault_interrupt
   .weak MemManage_interrupt
@@ -1175,7 +1175,7 @@ interrupt_vectors:
   .weak PLL1_Interrupt
   .weak USBActivity_Interrupt
   .weak CanActivity_Interrupt
-  
+
     .set NMI_interrupt, Startup
   .set Hardfault_interrupt, Startup
   .set MemManage_interrupt, Startup
@@ -1220,7 +1220,7 @@ interrupt_vectors:
   .set PLL1_Interrupt, Startup
   .set USBActivity_Interrupt, Startup
   .set CanActivity_Interrupt, Startup
-  
+
   .text
 end;
 

rtl/embedded/arm/raspi2.pp

@@ -59,7 +59,7 @@ begin
             nop
         end;
     end;
-end; 
+end;
 
 procedure PUT32(Address: DWord; Value: DWord); inline;
 VAR
@@ -142,7 +142,7 @@ begin
     PUT32(AUX_MU_IER_REG, 0);
     PUT32(AUX_MU_IIR_REG, $C6);
     PUT32(AUX_MU_BAUD_REG, 270);
-    
+
     ra := GET32(GPFSEL1);
     ra := ra AND (not (7 shl 12)); // gpio14
     ra := ra OR (2 shl 12);  // alt5
@@ -151,7 +151,7 @@ begin
 
     PUT32(GPFSEL1, ra);
     PUT32(GPPUD, 0);
-    
+
     Dummy(500);
 
     PUT32(GPPUDCLK0, ((1 shl 14) OR (1 shl 15)));

rtl/embedded/arm/rp2040.pp

@@ -8,11 +8,11 @@ interface
 
 type
   TIRQn_Enum = (
-    NonMaskableInt_IRQn = -14,        
-    HardFault_IRQn = -13,             
-    SVC_IRQn    = -5,                 
-    PendSV_IRQn = -2,                 
-    SysTick_IRQn = -1,                
+    NonMaskableInt_IRQn = -14,
+    HardFault_IRQn = -13,
+    SVC_IRQn    = -5,
+    PendSV_IRQn = -2,
+    SysTick_IRQn = -1,
     TIMER_IRQ_0 = 0,
     TIMER_IRQ_1 = 1,
     TIMER_IRQ_2 = 2,

rtl/embedded/arm/samd51p19a.pp

@@ -3,7 +3,7 @@ unit samd51p19a;
 {$ENDIF FPC_DOTTEDUNITS}
 (*
   Copyright (c) 2020 Microchip Technology Inc.
-                   
+
   Licensed under the Apache License, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   You may obtain a copy of the Licence at
@@ -320,7 +320,7 @@ type
     BASEADDR     : longWord;             //0034 Descriptor Memory Section Base Address
     WRBADDR      : longWord;             //0038 Write-Back Memory Section Base Address
     RESERVED3    : longWord;
-    CHANNEL      : array[0..31] of TDMAC_CHANNEL_Registers;  //0040 
+    CHANNEL      : array[0..31] of TDMAC_CHANNEL_Registers;  //0040
   end;
 
   TDMAC_DESCRIPTOR_Registers = record
@@ -400,7 +400,7 @@ type
     INTSTATUS    : longWord;             //0014 Interrupt Status
     BUSYCH       : longWord;             //0018 Busy Channels
     READYUSR     : longWord;             //001C Ready Users
-    CHANNEL      : array[0..31] of TEVSYS_CHANNEL_Registers;  //0020 
+    CHANNEL      : array[0..31] of TEVSYS_CHANNEL_Registers;  //0020
     USER         : array[0..66] of longWord; //0120 User Multiplexer n
   end;
 
@@ -433,7 +433,7 @@ type
   end;
 
   THMATRIXB_Registers = record
-    PRS          : array[0..15] of THMATRIXB_PRS_Registers;  //0080 
+    PRS          : array[0..15] of THMATRIXB_PRS_Registers;  //0080
   end;
 
   TICM_Registers = record
@@ -555,7 +555,7 @@ type
     DFLLMUL      : longWord;             //0028 DFLL48M Multiplier
     DFLLSYNC     : byte;                 //002C DFLL48M Synchronization
     RESERVED3    : array[1..3] of byte;
-    DPLL         : array[0..1] of TOSCCTRL_DPLL_Registers;  //0030 
+    DPLL         : array[0..1] of TOSCCTRL_DPLL_Registers;  //0030
   end;
 
   TOSC32KCTRL_Registers = record
@@ -662,7 +662,7 @@ type
   end;
 
   TPORT_Registers = record
-    GROUP        : array[0..3] of TPORT_GROUP_Registers;  //0000 
+    GROUP        : array[0..3] of TPORT_GROUP_Registers;  //0000
   end;
 
   TPUKCC_Registers = record
@@ -1153,7 +1153,7 @@ type
     DESCADD      : longWord;             //0024 Descriptor Address
     PADCAL       : word;                 //0028 USB PAD Calibration
     RESERVED9    : array[1..214] of byte;
-    HOST_PIPE    : array[0..7] of TUSB_HOST_PIPE_Registers;  //0100 
+    HOST_PIPE    : array[0..7] of TUSB_HOST_PIPE_Registers;  //0100
   end;
 
   TUSBHOST_Registers = record
@@ -1182,15 +1182,15 @@ type
     DESCADD      : longWord;             //0024 Descriptor Address
     PADCAL       : word;                 //0028 USB PAD Calibration
     RESERVED9    : array[1..214] of byte;
-    HOST_PIPE    : array[0..7] of TUSB_HOST_PIPE_Registers;  //0100 
+    HOST_PIPE    : array[0..7] of TUSB_HOST_PIPE_Registers;  //0100
   end;
 
   TUSB_DESCRIPTORDEVICE_Registers = record
-    HOST_DESC_BANK : array[0..1] of TUSB_HOST_DESC_BANK_Registers;  //0000 
+    HOST_DESC_BANK : array[0..1] of TUSB_HOST_DESC_BANK_Registers;  //0000
   end;
 
   TUSB_DESCRIPTORHOST_Registers = record
-    HOST_DESC_BANK : array[0..1] of TUSB_HOST_DESC_BANK_Registers;  //0000 
+    HOST_DESC_BANK : array[0..1] of TUSB_HOST_DESC_BANK_Registers;  //0000
   end;
 
   TWDT_Registers = record

rtl/embedded/arm/sc32442b.pp

@@ -23,7 +23,7 @@ unit sc32442b;
       REFRESH: longword 	absolute $48000024;
       BANKSIZE: longword 	absolute $48000028;
       MRSRB6: longword 		absolute $4800002C;
-    
+
     { USB Host Controller }
       HcRevision: longword 			absolute $49000000;
       HcControl: longword 				absolute $49000004;
@@ -48,7 +48,7 @@ unit sc32442b;
       HcRhStatus: longword				absolute $49000050;
       HcRhPortStatus1: longword		absolute $49000054;
       HcRhPortStatus2: longword		absolute $49000058;
-    
+
     { Interrupt controller }
       SRCPND: longword			absolute $4A000000;
       INTMOD: longword			absolute $4A000004;
@@ -58,7 +58,7 @@ unit sc32442b;
       INTOFFSET: longword		absolute $4A000014;
       SUBSRCPND: longword		absolute $4A000018;
       INTSUBMSK: longword		absolute $4A00001C;
-    
+
     type
      TDMA = packed record
       DISRC,
@@ -71,14 +71,14 @@ unit sc32442b;
       DCDST,
       DMASKTRIG: longword;
     end;
-    
+
    var
     { DMA }
     DMA0: TDMA	absolute $4B000000;
     DMA1: TDMA	absolute $4B000040;
     DMA2: TDMA	absolute $4B000080;
     DMA3: TDMA	absolute $4B0000C0;
-    
+
     { Clock and power }
     LOCKTIME: longword	absolute $4C000000;
     MPLLCON: longword		absolute $4C000004;
@@ -87,7 +87,7 @@ unit sc32442b;
     CLKSLOW: longword		absolute $4C000010;
     CLKDIVN: longword		absolute $4C000014;
     CAMDIVN: longword		absolute $4C000018;
-    
+
     { LCD Controller }
     LCDCON1: longword		absolute $4D000000;
     LCDCON2: longword		absolute $4D000004;
@@ -106,7 +106,7 @@ unit sc32442b;
     LCDSRCPND: longword	absolute $4D000058;
     LCDINTMSK: longword	absolute $4D00005C;
     TCONSEL: longword		absolute $4D000060;
-    
+
     { NAND Flash }
     NFCONF: longword		absolute $4E000000;
     NFCONT: longword		absolute $4E000004;
@@ -124,7 +124,7 @@ unit sc32442b;
     NFSECC2: longword		absolute $4E000034;
     NFSBLK: longword		absolute $4E000038;
     NFEBLK: longword		absolute $4E00003C;
-    
+
     type
      TUART = packed record
       ULCON,
@@ -144,7 +144,7 @@ unit sc32442b;
     UART0: TUART		absolute $50000000;
     UART1: TUART		absolute $50004000;
     UART2: TUART		absolute $50008000;
-    
+
    type
      TPWMTimer = packed record
       TCNTB,
@@ -157,7 +157,7 @@ unit sc32442b;
     TCFG1: longword 		absolute $51000004;
     TCON: longword 		absolute $51000008;
     PWMTimer: array[0..4] of TPWMTimer absolute $5100000C;
-    
+
     { USB Device }
     FUNC_ADDR_REG: byte		absolute $52000140;
     PWR_REG: byte				absolute $52000144;
@@ -205,26 +205,26 @@ unit sc32442b;
     EP4_DMA_TTC_L: byte		absolute $52000264;
     EP4_DMA_TTC_M: byte		absolute $52000268;
     EP4_DMA_TTC_H: byte		absolute $5200026C;
-    
+
     { Watchdog timer }
     WTCON: longword		absolute $53000000;
     WTDAT: longword		absolute $53000004;
     WTCNT: longword		absolute $53000008;
-    
+
     { I2C }
     IICCON: longword		absolute $54000000;
     IICSTAT: longword		absolute $54000004;
     IICADD: longword		absolute $54000008;
     IICDS: longword		absolute $5400000C;
     IICLC: longword		absolute $54000010;
-    
+
     { I2S }
     IISCON: longword		absolute $55000000;
     IISMOD: longword		absolute $55000004;
     IISPSR: longword		absolute $55000008;
     IISFCON: longword		absolute $5500000C;
     IISFIFO: longword		absolute $55000010;
-    
+
    type
      TGPIO = packed record
       CON,
@@ -259,7 +259,7 @@ unit sc32442b;
     GSTATUS3: longword	absolute $560000B8;
     GSTATUS4: longword	absolute $560000BC;
     MSLCON: longword		absolute $560000CC;
-    
+
     { RTC }
     RTCCON: byte		absolute $57000040;
     TICNT: byte			absolute $57000044;
@@ -278,7 +278,7 @@ unit sc32442b;
     BCDMON: byte		absolute $57000084;
     BCDYEAR: byte		absolute $57000088;
     RTCLBAT: byte		absolute $5700006C;
-    
+
     { AD converter }
     ADCCON: longword		absolute $58000000;
     ADCTSC: longword		absolute $58000004;
@@ -286,7 +286,7 @@ unit sc32442b;
     ADCDAT0: longword		absolute $5800000C;
     ADCDAT1: longword		absolute $58000010;
     ADCUPDN: longword		absolute $58000014;
-    
+
    type
      TSPI = packed record
       SPCON,
@@ -300,7 +300,7 @@ unit sc32442b;
     { SPI }
     SPI0: TSPI		absolute $59000000;
     SPI1: TSPI		absolute $59000020;
-    
+
     { SD Interface }
     SDICON: longword		absolute $5A000000;
     SDIPRE: longword		absolute $5A000004;
@@ -328,7 +328,7 @@ unit sc32442b;
     procedure DataAbortHandler; external name 'DataAbortHandler';
     procedure IRQHandler; external name 'IRQHandler';
     procedure FIQHandler; external name 'FIQHandler';
-        
+
     procedure DefaultExceptionHandler; assembler; nostackframe;
       asm
       .Lloop:
@@ -386,7 +386,7 @@ unit sc32442b;
         .weak DataAbortHandler
         .weak IRQHandler
         .weak FIQHandler
-        
+
         .set UndefinedInstrHandler, DefaultExceptionHandler
         .set SWIHandler, DefaultExceptionHandler
         .set PrefetchAbortHandler, DefaultExceptionHandler

rtl/embedded/arm/stm32f10x_conn.pp

@@ -509,7 +509,7 @@ interrupt_vectors:
    .long 0
    .long PendingSV_interrupt
    .long SysTick_interrupt
-   
+
    .long Window_Watchdog_interrupt
    .long PVD_through_EXTI_Line_detection_interrupt
    .long Tamper_interrupt
@@ -578,7 +578,7 @@ interrupt_vectors:
    .long CAN2_RX1_interrupt
    .long CAN2_SCE_interrupt
    .long USB_On_The_Go_FS_global_interrupt
-   
+
    .weak NMI_interrupt
    .weak Hardfault_interrupt
    .weak MemManage_interrupt
@@ -588,7 +588,7 @@ interrupt_vectors:
    .weak DebugMonitor_interrupt
    .weak PendingSV_interrupt
    .weak SysTick_interrupt
-   
+
    .weak Window_Watchdog_interrupt
    .weak PVD_through_EXTI_Line_detection_interrupt
    .weak Tamper_interrupt
@@ -651,7 +651,7 @@ interrupt_vectors:
    .weak CAN2_SCE_interrupt
    .weak USB_On_The_Go_FS_global_interrupt
 
-   
+
    .set NMI_interrupt, HaltProc
    .set Hardfault_interrupt, HaltProc
    .set MemManage_interrupt, HaltProc
@@ -723,7 +723,7 @@ interrupt_vectors:
    .set CAN2_RX1_interrupt, HaltProc
    .set CAN2_SCE_interrupt, HaltProc
    .set USB_On_The_Go_FS_global_interrupt, HaltProc
-   
+
    .text
 end;
 

rtl/embedded/arm/stm32f10x_hd.pp

@@ -328,7 +328,7 @@ type
   OBR,
   WRPR: longword;
  end;
- 
+
  TFSMC_Bank1 = record
   BCR1 : longword;
   BTR1 : longword;
@@ -562,7 +562,7 @@ interrupt_vectors:
    .long 0
    .long PendingSV_interrupt
    .long SysTick_interrupt
-   
+
    .long Window_watchdog_interrupt
    .long PVD_through_EXTI_Line_detection_interrupt
    .long Tamper_interrupt
@@ -623,7 +623,7 @@ interrupt_vectors:
    .long DMA2_Channel2_global_interrupt
    .long DMA2_Channel3_global_interrupt
    .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
-   
+
    .weak NMI_interrupt
    .weak Hardfault_interrupt
    .weak MemManage_interrupt
@@ -633,7 +633,7 @@ interrupt_vectors:
    .weak DebugMonitor_interrupt
    .weak PendingSV_interrupt
    .weak SysTick_interrupt
-   
+
    .weak Window_watchdog_interrupt
    .weak PVD_through_EXTI_Line_detection_interrupt
    .weak Tamper_interrupt
@@ -695,7 +695,7 @@ interrupt_vectors:
    .weak DMA2_Channel3_global_interrupt
    .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
 
-   
+
    .set NMI_interrupt, HaltProc
    .set Hardfault_interrupt, HaltProc
    .set MemManage_interrupt, HaltProc
@@ -766,7 +766,7 @@ interrupt_vectors:
    .set DMA2_Channel2_global_interrupt, HaltProc
    .set DMA2_Channel3_global_interrupt, HaltProc
    .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc
-   
+
    .text
 end;
 

rtl/embedded/arm/stm32f10x_ld.pp

@@ -508,7 +508,7 @@ interrupt_vectors:
    .long 0
    .long PendingSV_interrupt
    .long SysTick_interrupt
-   
+
    .long Window_watchdog_interrupt
    .long PVD_through_EXTI_Line_detection_interrupt
    .long Tamper_interrupt
@@ -569,7 +569,7 @@ interrupt_vectors:
    .long DMA2_Channel2_global_interrupt
    .long DMA2_Channel3_global_interrupt
    .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
-   
+
    .weak NMI_interrupt
    .weak Hardfault_interrupt
    .weak MemManage_interrupt
@@ -579,7 +579,7 @@ interrupt_vectors:
    .weak DebugMonitor_interrupt
    .weak PendingSV_interrupt
    .weak SysTick_interrupt
-   
+
    .weak Window_watchdog_interrupt
    .weak PVD_through_EXTI_Line_detection_interrupt
    .weak Tamper_interrupt
@@ -641,7 +641,7 @@ interrupt_vectors:
    .weak DMA2_Channel3_global_interrupt
    .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
 
-   
+
    .set NMI_interrupt, HaltProc
    .set Hardfault_interrupt, HaltProc
    .set MemManage_interrupt, HaltProc
@@ -712,7 +712,7 @@ interrupt_vectors:
    .set DMA2_Channel2_global_interrupt, HaltProc
    .set DMA2_Channel3_global_interrupt, HaltProc
    .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc
-   
+
    .text
 end;
 

rtl/embedded/arm/stm32f10x_md.pp

@@ -508,7 +508,7 @@ interrupt_vectors:
    .long 0
    .long PendingSV_interrupt
    .long SysTick_interrupt
-   
+
    .long Window_watchdog_interrupt
    .long PVD_through_EXTI_Line_detection_interrupt
    .long Tamper_interrupt
@@ -569,7 +569,7 @@ interrupt_vectors:
    .long DMA2_Channel2_global_interrupt
    .long DMA2_Channel3_global_interrupt
    .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
-   
+
    .weak NMI_interrupt
    .weak Hardfault_interrupt
    .weak MemManage_interrupt
@@ -579,7 +579,7 @@ interrupt_vectors:
    .weak DebugMonitor_interrupt
    .weak PendingSV_interrupt
    .weak SysTick_interrupt
-   
+
    .weak Window_watchdog_interrupt
    .weak PVD_through_EXTI_Line_detection_interrupt
    .weak Tamper_interrupt
@@ -641,7 +641,7 @@ interrupt_vectors:
    .weak DMA2_Channel3_global_interrupt
    .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
 
-   
+
    .set NMI_interrupt, HaltProc
    .set Hardfault_interrupt, HaltProc
    .set MemManage_interrupt, HaltProc
@@ -712,7 +712,7 @@ interrupt_vectors:
    .set DMA2_Channel2_global_interrupt, HaltProc
    .set DMA2_Channel3_global_interrupt, HaltProc
    .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc
-   
+
    .text
 end;
 

rtl/embedded/arm/stm32f10x_xl.pp

@@ -328,7 +328,7 @@ type
   OBR,
   WRPR: longword;
  end;
- 
+
  TFSMC_Bank1 = record
   BCR1 : longword;
   BTR1 : longword;
@@ -562,7 +562,7 @@ interrupt_vectors:
    .long 0
    .long PendingSV_interrupt
    .long SysTick_interrupt
-   
+
    .long Window_watchdog_interrupt
    .long PVD_through_EXTI_Line_detection_interrupt
    .long Tamper_interrupt
@@ -623,8 +623,8 @@ interrupt_vectors:
    .long DMA2_Channel2_global_interrupt
    .long DMA2_Channel3_global_interrupt
    .long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
-   
-   
+
+
    .weak NMI_interrupt
    .weak Hardfault_interrupt
    .weak MemManage_interrupt
@@ -634,7 +634,7 @@ interrupt_vectors:
    .weak DebugMonitor_interrupt
    .weak PendingSV_interrupt
    .weak SysTick_interrupt
-   
+
    .weak Window_watchdog_interrupt
    .weak PVD_through_EXTI_Line_detection_interrupt
    .weak Tamper_interrupt
@@ -696,7 +696,7 @@ interrupt_vectors:
    .weak DMA2_Channel3_global_interrupt
    .weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
 
-   
+
    .set NMI_interrupt, HaltProc
    .set Hardfault_interrupt, HaltProc
    .set MemManage_interrupt, HaltProc
@@ -767,7 +767,7 @@ interrupt_vectors:
    .set DMA2_Channel2_global_interrupt, HaltProc
    .set DMA2_Channel3_global_interrupt, HaltProc
    .set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc
-   
+
    .text
 end;
 

rtl/embedded/arm/stm32f429.pp

@@ -376,7 +376,7 @@ interrupt_vectors:
    .long LTDC_interrupt
    .long LTDC_ERR_interrupt
    .long DMA2D_interrupt
-   
+
    .weak NMI_interrupt
    .weak Hardfault_interrupt
    .weak MemManage_interrupt
@@ -475,7 +475,7 @@ interrupt_vectors:
    .weak LTDC_interrupt
    .weak LTDC_ERR_interrupt
    .weak DMA2D_interrupt
-   
+
    .set NMI_interrupt, HaltProc
    .set Hardfault_interrupt, HaltProc
    .set MemManage_interrupt, HaltProc

rtl/embedded/avr/at90can128.pp

@@ -59,9 +59,9 @@ var
   UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register t Bytes
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
@@ -156,7 +156,7 @@ var
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // CAN
   CANGCON : byte absolute $00+$D8; // CAN General Control Register
   CANGSTA : byte absolute $00+$D9; // CAN General Status Register
@@ -300,8 +300,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable

rtl/embedded/avr/at90can32.pp

@@ -63,9 +63,9 @@ var
   UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register t Bytes
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
@@ -156,7 +156,7 @@ var
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // CAN
   CANGCON : byte absolute $00+$D8; // CAN General Control Register
   CANGSTA : byte absolute $00+$D9; // CAN General Status Register
@@ -300,8 +300,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable

rtl/embedded/avr/at90can64.pp

@@ -59,9 +59,9 @@ var
   UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register t Bytes
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
@@ -156,7 +156,7 @@ var
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // CAN
   CANGCON : byte absolute $00+$D8; // CAN General Control Register
   CANGSTA : byte absolute $00+$D9; // CAN General Status Register
@@ -300,8 +300,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable

rtl/embedded/avr/at90pwm1.pp

@@ -14,61 +14,61 @@ var
   // BOOT_LOAD
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   // PSC0
-  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register 
+  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register
   PFRC0B : byte absolute $00+$DD; // PSC 0 Input B Control
   PFRC0A : byte absolute $00+$DC; // PSC 0 Input A Control
   PCTL0 : byte absolute $00+$DB; // PSC 0 Control Register
   PCNF0 : byte absolute $00+$DA; // PSC 0 Configuration Register
-  OCR0RB : word absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register 
-  OCR0SB : word absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register 
-  OCR0RA : word absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register 
-  OCR0SA : word absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register 
+  OCR0RB : word absolute $00+$D8; // Output Compare RB Register
+  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register
+  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register
+  OCR0SB : word absolute $00+$D6; // Output Compare SB Register
+  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register
+  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register
+  OCR0RA : word absolute $00+$D4; // Output Compare RA Register
+  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register
+  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register
+  OCR0SA : word absolute $00+$D2; // Output Compare SA Register
+  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register
+  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register
   PSOC0 : byte absolute $00+$D0; // PSC0 Synchro and Output Configuration
   PIM0 : byte absolute $00+$A1; // PSC0 Interrupt Mask Register
   PIFR0 : byte absolute $00+$A0; // PSC0 Interrupt Flag Register
   // PSC2
-  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register 
+  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register
   PFRC2B : byte absolute $00+$FD; // PSC 2 Input B Control
   PFRC2A : byte absolute $00+$FC; // PSC 2 Input B Control
   PCTL2 : byte absolute $00+$FB; // PSC 2 Control Register
   PCNF2 : byte absolute $00+$FA; // PSC 2 Configuration Register
-  OCR2RB : word absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register 
-  OCR2SB : word absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register 
-  OCR2RA : word absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register 
-  OCR2SA : word absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register 
+  OCR2RB : word absolute $00+$F8; // Output Compare RB Register
+  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register
+  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register
+  OCR2SB : word absolute $00+$F6; // Output Compare SB Register
+  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register
+  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register
+  OCR2RA : word absolute $00+$F4; // Output Compare RA Register
+  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register
+  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register
+  OCR2SA : word absolute $00+$F2; // Output Compare SA Register
+  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register
+  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register
   POM2 : byte absolute $00+$F1; // PSC 2 Output Matrix
   PSOC2 : byte absolute $00+$F0; // PSC2 Synchro and Output Configuration
   PIM2 : byte absolute $00+$A5; // PSC2 Interrupt Mask Register
   PIFR2 : byte absolute $00+$A4; // PSC2 Interrupt Flag Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   GPIOR3 : byte absolute $00+$3B; // General Purpose IO Register 3
   GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2
@@ -116,8 +116,8 @@ var
   ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
   DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0
-  AMP0CSR : byte absolute $00+$76; // 
-  AMP1CSR : byte absolute $00+$77; // 
+  AMP0CSR : byte absolute $00+$76; //
+  AMP1CSR : byte absolute $00+$77; //
   // SPI
   SPCR : byte absolute $00+$4C; // SPI Control Register
   SPSR : byte absolute $00+$4D; // SPI Status Register
@@ -139,9 +139,9 @@ var
   AC2CON : byte absolute $00+$AF; // Analog Comparator 2 Control Register
   ACSR : byte absolute $00+$50; // Analog Comparator Status Register
   // PSC1
-  PICR1 : word absolute $00+$EE; // PSC 1 Input Capture Register 
-  PICR1L : byte absolute $00+$EE; // PSC 1 Input Capture Register 
-  PICR1H : byte absolute $00+$EE+1; // PSC 1 Input Capture Register 
+  PICR1 : word absolute $00+$EE; // PSC 1 Input Capture Register
+  PICR1L : byte absolute $00+$EE; // PSC 1 Input Capture Register
+  PICR1H : byte absolute $00+$EE+1; // PSC 1 Input Capture Register
   PFRC1B : byte absolute $00+$ED; // PSC 1 Input B Control
   PFRC1A : byte absolute $00+$EC; // PSC 1 Input B Control
   PCTL1 : byte absolute $00+$EB; // PSC 1 Control Register
@@ -267,8 +267,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -311,7 +311,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // GTCCR
   TSM = 7; // Timer/Counter Synchronization Mode
@@ -336,8 +336,8 @@ const
   ICES1 = 6; // Input Capture 1 Edge Select
   CS1 = 0; // Prescaler source of Timer/Counter 1
   // TCCR1C
-  FOC1A = 7; // 
-  FOC1B = 6; // 
+  FOC1A = 7; //
+  FOC1B = 6; //
   // GTCCR
   PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
   // ADMUX
@@ -352,22 +352,22 @@ const
   ADIE = 3; // ADC Interrupt Enable
   ADPS = 0; // ADC  Prescaler Select Bits
   // DIDR1
-  ACMP0D = 5; // 
-  AMP0PD = 4; // 
-  AMP0ND = 3; // 
-  ADC10D = 2; // 
-  ADC9D = 1; // 
-  ADC8D = 0; // 
+  ACMP0D = 5; //
+  AMP0PD = 4; //
+  AMP0ND = 3; //
+  ADC10D = 2; //
+  ADC9D = 1; //
+  ADC8D = 0; //
   // AMP0CSR
-  AMP0EN = 7; // 
-  AMP0IS = 6; // 
-  AMP0G = 4; // 
-  AMP0TS = 0; // 
+  AMP0EN = 7; //
+  AMP0IS = 6; //
+  AMP0G = 4; //
+  AMP0TS = 0; //
   // AMP1CSR
-  AMP1EN = 7; // 
-  AMP1IS = 6; // 
-  AMP1G = 4; // 
-  AMP1TS = 0; // 
+  AMP1EN = 7; //
+  AMP1IS = 6; //
+  AMP1G = 4; //
+  AMP1TS = 0; //
   // SPCR
   SPIE = 7; // SPI Interrupt Enable
   SPE = 6; // SPI Enable
@@ -461,7 +461,7 @@ procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt
 procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
 procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
 procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B
-procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14 
+procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14
 procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
 procedure TIMER0_COMP_A_ISR; external name 'TIMER0_COMP_A_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
 procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow
@@ -476,8 +476,8 @@ procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 25 Watchdog Timeout Int
 procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 26 EEPROM Ready
 procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 27 Timer Counter 0 Compare Match B
 procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 28 External Interrupt Request 3
-procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29 
-procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30 
+procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29
+procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 31 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90pwm161.pp

@@ -38,32 +38,32 @@ var
   ADCSRB : byte absolute $00+$27; // ADC Control and Status Register B
   DIDR0 : byte absolute $00+$77; // Digital Input Disable Register 0
   DIDR1 : byte absolute $00+$78; // Digital Input Disable Register 0
-  AMP0CSR : byte absolute $00+$79; // 
+  AMP0CSR : byte absolute $00+$79; //
   // ANALOG_COMPARATOR
   AC3CON : byte absolute $00+$7F; // Analog Comparator3 Control Register
   AC1CON : byte absolute $00+$7D; // Analog Comparator 1 Control Register
   AC2CON : byte absolute $00+$7E; // Analog Comparator 2 Control Register
   ACSR : byte absolute $00+$20; // Analog Comparator Status Register
-  AC3ECON : byte absolute $00+$7C; // 
-  AC2ECON : byte absolute $00+$7B; // 
-  AC1ECON : byte absolute $00+$7A; // 
+  AC3ECON : byte absolute $00+$7C; //
+  AC2ECON : byte absolute $00+$7B; //
+  AC1ECON : byte absolute $00+$7A; //
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$88; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$83; // 
+  CLKPR : byte absolute $00+$83; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   GPIOR2 : byte absolute $00+$3B; // General Purpose IO Register 2
   GPIOR1 : byte absolute $00+$3A; // General Purpose IO Register 1
   GPIOR0 : byte absolute $00+$39; // General Purpose IO Register 0
   PLLCSR : byte absolute $00+$87; // PLL Control And Status Register
   PRR : byte absolute $00+$86; // Power Reduction Register
-  CLKCSR : byte absolute $00+$84; // 
-  CLKSELR : byte absolute $00+$85; // 
+  CLKCSR : byte absolute $00+$84; //
+  CLKSELR : byte absolute $00+$85; //
   BGCCR : byte absolute $00+$81; // BandGap Current Calibration Register
   BGCRR : byte absolute $00+$80; // BandGap Resistor Calibration Register
   // EEPROM
@@ -73,25 +73,25 @@ var
   EEDR : byte absolute $00+$3D; // EEPROM Data Register
   EECR : byte absolute $00+$3C; // EEPROM Control Register
   // PSC0
-  PICR0 : word absolute $00+$68; // PSC 0 Input Capture Register 
-  PICR0L : byte absolute $00+$68; // PSC 0 Input Capture Register 
-  PICR0H : byte absolute $00+$68+1; // PSC 0 Input Capture Register 
+  PICR0 : word absolute $00+$68; // PSC 0 Input Capture Register
+  PICR0L : byte absolute $00+$68; // PSC 0 Input Capture Register
+  PICR0H : byte absolute $00+$68+1; // PSC 0 Input Capture Register
   PFRC0B : byte absolute $00+$63; // PSC 0 Input B Control
   PFRC0A : byte absolute $00+$62; // PSC 0 Input A Control
   PCTL0 : byte absolute $00+$32; // PSC 0 Control Register
   PCNF0 : byte absolute $00+$31; // PSC 0 Configuration Register
-  OCR0RB : word absolute $00+$44; // Output Compare RB Register 
-  OCR0RBL : byte absolute $00+$44; // Output Compare RB Register 
-  OCR0RBH : byte absolute $00+$44+1; // Output Compare RB Register 
-  OCR0SB : word absolute $00+$42; // Output Compare SB Register 
-  OCR0SBL : byte absolute $00+$42; // Output Compare SB Register 
-  OCR0SBH : byte absolute $00+$42+1; // Output Compare SB Register 
-  OCR0RA : word absolute $00+$4A; // Output Compare RA Register 
-  OCR0RAL : byte absolute $00+$4A; // Output Compare RA Register 
-  OCR0RAH : byte absolute $00+$4A+1; // Output Compare RA Register 
-  OCR0SA : word absolute $00+$60; // Output Compare SA Register 
-  OCR0SAL : byte absolute $00+$60; // Output Compare SA Register 
-  OCR0SAH : byte absolute $00+$60+1; // Output Compare SA Register 
+  OCR0RB : word absolute $00+$44; // Output Compare RB Register
+  OCR0RBL : byte absolute $00+$44; // Output Compare RB Register
+  OCR0RBH : byte absolute $00+$44+1; // Output Compare RB Register
+  OCR0SB : word absolute $00+$42; // Output Compare SB Register
+  OCR0SBL : byte absolute $00+$42; // Output Compare SB Register
+  OCR0SBH : byte absolute $00+$42+1; // Output Compare SB Register
+  OCR0RA : word absolute $00+$4A; // Output Compare RA Register
+  OCR0RAL : byte absolute $00+$4A; // Output Compare RA Register
+  OCR0RAH : byte absolute $00+$4A+1; // Output Compare RA Register
+  OCR0SA : word absolute $00+$60; // Output Compare SA Register
+  OCR0SAL : byte absolute $00+$60; // Output Compare SA Register
+  OCR0SAH : byte absolute $00+$60+1; // Output Compare SA Register
   PSOC0 : byte absolute $00+$6A; // PSC0 Synchro and Output Configuration
   PIM0 : byte absolute $00+$2F; // PSC0 Interrupt Mask Register
   PIFR0 : byte absolute $00+$30; // PSC0 Interrupt Flag Register
@@ -103,18 +103,18 @@ var
   PCTL2 : byte absolute $00+$36; // PSC 2 Control Register
   PCNF2 : byte absolute $00+$35; // PSC 2 Configuration Register
   PCNFE2 : byte absolute $00+$70; // PSC 2 Enhanced Configuration Register
-  OCR2RB : word absolute $00+$48; // Output Compare RB Register 
-  OCR2RBL : byte absolute $00+$48; // Output Compare RB Register 
-  OCR2RBH : byte absolute $00+$48+1; // Output Compare RB Register 
-  OCR2SB : word absolute $00+$46; // Output Compare SB Register 
-  OCR2SBL : byte absolute $00+$46; // Output Compare SB Register 
-  OCR2SBH : byte absolute $00+$46+1; // Output Compare SB Register 
-  OCR2RA : word absolute $00+$4E; // Output Compare RA Register 
-  OCR2RAL : byte absolute $00+$4E; // Output Compare RA Register 
-  OCR2RAH : byte absolute $00+$4E+1; // Output Compare RA Register 
-  OCR2SA : word absolute $00+$64; // Output Compare SA Register 
-  OCR2SAL : byte absolute $00+$64; // Output Compare SA Register 
-  OCR2SAH : byte absolute $00+$64+1; // Output Compare SA Register 
+  OCR2RB : word absolute $00+$48; // Output Compare RB Register
+  OCR2RBL : byte absolute $00+$48; // Output Compare RB Register
+  OCR2RBH : byte absolute $00+$48+1; // Output Compare RB Register
+  OCR2SB : word absolute $00+$46; // Output Compare SB Register
+  OCR2SBL : byte absolute $00+$46; // Output Compare SB Register
+  OCR2SBH : byte absolute $00+$46+1; // Output Compare SB Register
+  OCR2RA : word absolute $00+$4E; // Output Compare RA Register
+  OCR2RAL : byte absolute $00+$4E; // Output Compare RA Register
+  OCR2RAH : byte absolute $00+$4E+1; // Output Compare RA Register
+  OCR2SA : word absolute $00+$64; // Output Compare SA Register
+  OCR2SAL : byte absolute $00+$64; // Output Compare SA Register
+  OCR2SAH : byte absolute $00+$64+1; // Output Compare SA Register
   POM2 : byte absolute $00+$6F; // PSC 2 Output Matrix
   PSOC2 : byte absolute $00+$6E; // PSC2 Synchro and Output Configuration
   PIM2 : byte absolute $00+$33; // PSC2 Interrupt Mask Register
@@ -184,7 +184,7 @@ const
   ADSSEN = 4; // ADC Single Shot Enable on PSC's Synchronisation Signals
   ADTS = 0; // ADC Auto Trigger Sources
   // DIDR0
-  ADC7D = 7; // 
+  ADC7D = 7; //
   ADC6D = 6; // ADC7 Digital input Disable
   ADC5D = 5; // ADC5 Digital input Disable
   ADC4D = 4; // ADC4 Digital input Disable
@@ -193,16 +193,16 @@ const
   ADC1D = 1; // ADC1 Digital input Disable
   ADC0D = 0; // ADC0 Digital input Disable
   // DIDR1
-  ACMP1MD = 3; // 
-  AMP0POSD = 2; // 
-  ADC10D = 1; // 
-  ADC9D = 0; // 
+  ACMP1MD = 3; //
+  AMP0POSD = 2; //
+  ADC10D = 1; //
+  ADC9D = 0; //
   // AMP0CSR
-  AMP0EN = 7; // 
-  AMP0IS = 6; // 
-  AMP0G = 4; // 
-  AMP0GS = 3; // 
-  AMP0TS = 0; // 
+  AMP0EN = 7; //
+  AMP0IS = 6; //
+  AMP0G = 4; //
+  AMP0GS = 3; //
+  AMP0TS = 0; //
   // AC3CON
   AC3EN = 7; // Analog Comparator3 Enable Bit
   AC3IE = 6; // Analog Comparator 3 Interrupt Enable Bit
@@ -260,8 +260,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -278,7 +278,7 @@ const
   GPIOR01 = 1; // General Purpose IO Register 0 bit 1
   GPIOR00 = 0; // General Purpose IO Register 0 bit 0
   // PLLCSR
-  PLLF = 2; // 
+  PLLF = 2; //
   PLLE = 1; // PLL Enable
   PLOCK = 0; // PLL Lock Detector
   // PRR
@@ -296,9 +296,9 @@ const
   CSUT = 4; // Clock Start up Time
   CKSEL = 0; // Clock Source Select
   // BGCCR
-  BGCC = 0; // 
+  BGCC = 0; //
   // BGCRR
-  BGCR = 0; // 
+  BGCR = 0; //
   // EECR
   NVMBSY = 7; // None Volatile Busy Memory Busy
   EEPAGE = 6; // EEPROM Page Access
@@ -353,8 +353,8 @@ const
   PEOP0 = 0; // End of PSC0 Interrupt
   // PICR2H
   PCST2 = 7; // PSC 2 Capture Software Trigger Bit
-  PICR21 = 2; // 
-  PICR2 = 0; // 
+  PICR21 = 2; //
+  PICR2 = 0; //
   // PFRC2B
   PCAE2B = 7; // PSC 2 Capture Enable Input Part B
   PISEL2B = 6; // PSC 2 Input Select for Part B
@@ -384,12 +384,12 @@ const
   PCLKSEL2 = 1; // PSC 2 Input Clock Select
   POME2 = 0; // PSC 2 Output Matrix Enable
   // PCNFE2
-  PASDLK2 = 5; // 
-  PBFM21 = 4; // 
-  PELEV2A1 = 3; // 
-  PELEV2B1 = 2; // 
-  PISEL2A1 = 1; // 
-  PISEL2B1 = 0; // 
+  PASDLK2 = 5; //
+  PBFM21 = 4; //
+  PELEV2A1 = 3; //
+  PELEV2B1 = 2; //
+  PISEL2A1 = 1; //
+  PISEL2B1 = 0; //
   // POM2
   POMV2B = 4; // Output Matrix Output B Ramps
   POMV2A = 0; // Output Matrix Output A Ramps

rtl/embedded/avr/at90pwm216.pp

@@ -31,13 +31,13 @@ var
   DACON : byte absolute $00+$AA; // DAC Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   GPIOR3 : byte absolute $00+$3B; // General Purpose IO Register 3
   GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2
@@ -85,8 +85,8 @@ var
   ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
   DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0
-  AMP0CSR : byte absolute $00+$76; // 
-  AMP1CSR : byte absolute $00+$77; // 
+  AMP0CSR : byte absolute $00+$76; //
+  AMP1CSR : byte absolute $00+$77; //
   // USART
   UDR : byte absolute $00+$C6; // USART I/O Data Register
   UCSRA : byte absolute $00+$C0; // USART Control and Status register A
@@ -111,48 +111,48 @@ var
   EEDR : byte absolute $00+$40; // EEPROM Data Register
   EECR : byte absolute $00+$3F; // EEPROM Control Register
   // PSC0
-  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register 
+  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register
   PFRC0B : byte absolute $00+$DD; // PSC 0 Input B Control
   PFRC0A : byte absolute $00+$DC; // PSC 0 Input A Control
   PCTL0 : byte absolute $00+$DB; // PSC 0 Control Register
   PCNF0 : byte absolute $00+$DA; // PSC 0 Configuration Register
-  OCR0RB : word absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register 
-  OCR0SB : word absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register 
-  OCR0RA : word absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register 
-  OCR0SA : word absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register 
+  OCR0RB : word absolute $00+$D8; // Output Compare RB Register
+  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register
+  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register
+  OCR0SB : word absolute $00+$D6; // Output Compare SB Register
+  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register
+  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register
+  OCR0RA : word absolute $00+$D4; // Output Compare RA Register
+  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register
+  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register
+  OCR0SA : word absolute $00+$D2; // Output Compare SA Register
+  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register
+  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register
   PSOC0 : byte absolute $00+$D0; // PSC0 Synchro and Output Configuration
   PIM0 : byte absolute $00+$A1; // PSC0 Interrupt Mask Register
   PIFR0 : byte absolute $00+$A0; // PSC0 Interrupt Flag Register
   // PSC2
-  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register 
+  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register
   PFRC2B : byte absolute $00+$FD; // PSC 2 Input B Control
   PFRC2A : byte absolute $00+$FC; // PSC 2 Input B Control
   PCTL2 : byte absolute $00+$FB; // PSC 2 Control Register
   PCNF2 : byte absolute $00+$FA; // PSC 2 Configuration Register
-  OCR2RB : word absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register 
-  OCR2SB : word absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register 
-  OCR2RA : word absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register 
-  OCR2SA : word absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register 
+  OCR2RB : word absolute $00+$F8; // Output Compare RB Register
+  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register
+  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register
+  OCR2SB : word absolute $00+$F6; // Output Compare SB Register
+  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register
+  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register
+  OCR2RA : word absolute $00+$F4; // Output Compare RA Register
+  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register
+  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register
+  OCR2SA : word absolute $00+$F2; // Output Compare SA Register
+  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register
+  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register
   POM2 : byte absolute $00+$F1; // PSC 2 Output Matrix
   PSOC2 : byte absolute $00+$F0; // PSC2 Synchro and Output Configuration
   PIM2 : byte absolute $00+$A5; // PSC2 Interrupt Mask Register
@@ -233,8 +233,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -277,7 +277,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // GTCCR
   TSM = 7; // Timer/Counter Synchronization Mode
@@ -302,8 +302,8 @@ const
   ICES1 = 6; // Input Capture 1 Edge Select
   CS1 = 0; // Prescaler source of Timer/Counter 1
   // TCCR1C
-  FOC1A = 7; // 
-  FOC1B = 6; // 
+  FOC1A = 7; //
+  FOC1B = 6; //
   // GTCCR
   PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
   // ADMUX
@@ -318,22 +318,22 @@ const
   ADIE = 3; // ADC Interrupt Enable
   ADPS = 0; // ADC  Prescaler Select Bits
   // DIDR1
-  ACMP0D = 5; // 
-  AMP0PD = 4; // 
-  AMP0ND = 3; // 
-  ADC10D = 2; // 
-  ADC9D = 1; // 
-  ADC8D = 0; // 
+  ACMP0D = 5; //
+  AMP0PD = 4; //
+  AMP0ND = 3; //
+  ADC10D = 2; //
+  ADC9D = 1; //
+  ADC8D = 0; //
   // AMP0CSR
-  AMP0EN = 7; // 
-  AMP0IS = 6; // 
-  AMP0G = 4; // 
-  AMP0TS = 0; // 
+  AMP0EN = 7; //
+  AMP0IS = 6; //
+  AMP0G = 4; //
+  AMP0TS = 0; //
   // AMP1CSR
-  AMP1EN = 7; // 
-  AMP1IS = 6; // 
-  AMP1G = 4; // 
-  AMP1TS = 0; // 
+  AMP1EN = 7; //
+  AMP1IS = 6; //
+  AMP1G = 4; //
+  AMP1TS = 0; //
   // UCSRA
   RXC = 7; // USART Receive Complete
   TXC = 6; // USART Transmitt Complete
@@ -505,7 +505,7 @@ procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt
 procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
 procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
 procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B
-procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14 
+procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14
 procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
 procedure TIMER0_COMP_A_ISR; external name 'TIMER0_COMP_A_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
 procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow
@@ -520,8 +520,8 @@ procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 25 Watchdog Timeout Int
 procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 26 EEPROM Ready
 procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 27 Timer Counter 0 Compare Match B
 procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 28 External Interrupt Request 3
-procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29 
-procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30 
+procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29
+procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 31 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90pwm2b.pp

@@ -31,13 +31,13 @@ var
   DACON : byte absolute $00+$AA; // DAC Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   GPIOR3 : byte absolute $00+$3B; // General Purpose IO Register 3
   GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2
@@ -85,8 +85,8 @@ var
   ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
   DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0
-  AMP0CSR : byte absolute $00+$76; // 
-  AMP1CSR : byte absolute $00+$77; // 
+  AMP0CSR : byte absolute $00+$76; //
+  AMP1CSR : byte absolute $00+$77; //
   // USART
   UDR : byte absolute $00+$C6; // USART I/O Data Register
   UCSRA : byte absolute $00+$C0; // USART Control and Status register A
@@ -111,48 +111,48 @@ var
   EEDR : byte absolute $00+$40; // EEPROM Data Register
   EECR : byte absolute $00+$3F; // EEPROM Control Register
   // PSC0
-  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register 
+  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register
   PFRC0B : byte absolute $00+$DD; // PSC 0 Input B Control
   PFRC0A : byte absolute $00+$DC; // PSC 0 Input A Control
   PCTL0 : byte absolute $00+$DB; // PSC 0 Control Register
   PCNF0 : byte absolute $00+$DA; // PSC 0 Configuration Register
-  OCR0RB : word absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register 
-  OCR0SB : word absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register 
-  OCR0RA : word absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register 
-  OCR0SA : word absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register 
+  OCR0RB : word absolute $00+$D8; // Output Compare RB Register
+  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register
+  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register
+  OCR0SB : word absolute $00+$D6; // Output Compare SB Register
+  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register
+  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register
+  OCR0RA : word absolute $00+$D4; // Output Compare RA Register
+  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register
+  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register
+  OCR0SA : word absolute $00+$D2; // Output Compare SA Register
+  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register
+  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register
   PSOC0 : byte absolute $00+$D0; // PSC0 Synchro and Output Configuration
   PIM0 : byte absolute $00+$A1; // PSC0 Interrupt Mask Register
   PIFR0 : byte absolute $00+$A0; // PSC0 Interrupt Flag Register
   // PSC2
-  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register 
+  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register
   PFRC2B : byte absolute $00+$FD; // PSC 2 Input B Control
   PFRC2A : byte absolute $00+$FC; // PSC 2 Input B Control
   PCTL2 : byte absolute $00+$FB; // PSC 2 Control Register
   PCNF2 : byte absolute $00+$FA; // PSC 2 Configuration Register
-  OCR2RB : word absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register 
-  OCR2SB : word absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register 
-  OCR2RA : word absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register 
-  OCR2SA : word absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register 
+  OCR2RB : word absolute $00+$F8; // Output Compare RB Register
+  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register
+  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register
+  OCR2SB : word absolute $00+$F6; // Output Compare SB Register
+  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register
+  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register
+  OCR2RA : word absolute $00+$F4; // Output Compare RA Register
+  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register
+  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register
+  OCR2SA : word absolute $00+$F2; // Output Compare SA Register
+  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register
+  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register
   POM2 : byte absolute $00+$F1; // PSC 2 Output Matrix
   PSOC2 : byte absolute $00+$F0; // PSC2 Synchro and Output Configuration
   PIM2 : byte absolute $00+$A5; // PSC2 Interrupt Mask Register
@@ -233,8 +233,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -277,7 +277,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // GTCCR
   TSM = 7; // Timer/Counter Synchronization Mode
@@ -302,8 +302,8 @@ const
   ICES1 = 6; // Input Capture 1 Edge Select
   CS1 = 0; // Prescaler source of Timer/Counter 1
   // TCCR1C
-  FOC1A = 7; // 
-  FOC1B = 6; // 
+  FOC1A = 7; //
+  FOC1B = 6; //
   // GTCCR
   PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
   // ADMUX
@@ -318,22 +318,22 @@ const
   ADIE = 3; // ADC Interrupt Enable
   ADPS = 0; // ADC  Prescaler Select Bits
   // DIDR1
-  ACMP0D = 5; // 
-  AMP0PD = 4; // 
-  AMP0ND = 3; // 
-  ADC10D = 2; // 
-  ADC9D = 1; // 
-  ADC8D = 0; // 
+  ACMP0D = 5; //
+  AMP0PD = 4; //
+  AMP0ND = 3; //
+  ADC10D = 2; //
+  ADC9D = 1; //
+  ADC8D = 0; //
   // AMP0CSR
-  AMP0EN = 7; // 
-  AMP0IS = 6; // 
-  AMP0G = 4; // 
-  AMP0TS = 0; // 
+  AMP0EN = 7; //
+  AMP0IS = 6; //
+  AMP0G = 4; //
+  AMP0TS = 0; //
   // AMP1CSR
-  AMP1EN = 7; // 
-  AMP1IS = 6; // 
-  AMP1G = 4; // 
-  AMP1TS = 0; // 
+  AMP1EN = 7; //
+  AMP1IS = 6; //
+  AMP1G = 4; //
+  AMP1TS = 0; //
   // UCSRA
   RXC = 7; // USART Receive Complete
   TXC = 6; // USART Transmitt Complete
@@ -507,7 +507,7 @@ procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt
 procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
 procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
 procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B
-procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14 
+procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14
 procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
 procedure TIMER0_COMP_A_ISR; external name 'TIMER0_COMP_A_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
 procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow
@@ -522,8 +522,8 @@ procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 25 Watchdog Timeout Int
 procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 26 EEPROM Ready
 procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 27 Timer Counter 0 Compare Match B
 procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 28 External Interrupt Request 3
-procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29 
-procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30 
+procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29
+procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 31 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90pwm3.pp

@@ -43,8 +43,8 @@ var
   MCUSR: byte absolute $54;  // MCU Status Register
   MCUCR: byte absolute $55;  // MCU Control Register
   SPMCSR: byte absolute $57;  // Store Program Memory Control Register
-  SP: word absolute $5D;  // Stack Pointer 
-  SPL: byte absolute $5D;  // Stack Pointer 
+  SP: word absolute $5D;  // Stack Pointer
+  SPL: byte absolute $5D;  // Stack Pointer
   SPH: byte absolute $5E;  // Stack Pointer ;
   SREG: byte absolute $5F;  // Status Register
   WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
@@ -123,28 +123,28 @@ var
   PCTL0: byte absolute $DB;  // PSC 0 Control Register
   PFRC0A: byte absolute $DC;  // PSC 0 Input A Control
   PFRC0B: byte absolute $DD;  // PSC 0 Input B Control
-  PICR0: word absolute $DE;  // PSC 0 Input Capture Register 
-  PICR0L: byte absolute $DE;  // PSC 0 Input Capture Register 
+  PICR0: word absolute $DE;  // PSC 0 Input Capture Register
+  PICR0L: byte absolute $DE;  // PSC 0 Input Capture Register
   PICR0H: byte absolute $DF;  // PSC 0 Input Capture Register ;
   PSOC1: byte absolute $E0;  // PSC1 Synchro and Output Configuration
-  OCR1SA: word absolute $E2;  // Output Compare SA Register 
-  OCR1SAL: byte absolute $E2;  // Output Compare SA Register 
+  OCR1SA: word absolute $E2;  // Output Compare SA Register
+  OCR1SAL: byte absolute $E2;  // Output Compare SA Register
   OCR1SAH: byte absolute $E3;  // Output Compare SA Register ;
-  OCR1RA: word absolute $E4;  // Output Compare RA Register 
-  OCR1RAL: byte absolute $E4;  // Output Compare RA Register 
+  OCR1RA: word absolute $E4;  // Output Compare RA Register
+  OCR1RAL: byte absolute $E4;  // Output Compare RA Register
   OCR1RAH: byte absolute $E5;  // Output Compare RA Register ;
-  OCR1SB: word absolute $E6;  // Output Compare SB Register 
-  OCR1SBL: byte absolute $E6;  // Output Compare SB Register 
+  OCR1SB: word absolute $E6;  // Output Compare SB Register
+  OCR1SBL: byte absolute $E6;  // Output Compare SB Register
   OCR1SBH: byte absolute $E7;  // Output Compare SB Register ;
-  OCR1RB: word absolute $E8;  // Output Compare RB Register 
-  OCR1RBL: byte absolute $E8;  // Output Compare RB Register 
+  OCR1RB: word absolute $E8;  // Output Compare RB Register
+  OCR1RBL: byte absolute $E8;  // Output Compare RB Register
   OCR1RBH: byte absolute $E9;  // Output Compare RB Register ;
   PCNF1: byte absolute $EA;  // PSC 1 Configuration Register
   PCTL1: byte absolute $EB;  // PSC 1 Control Register
   PFRC1A: byte absolute $EC;  // PSC 1 Input B Control
   PFRC1B: byte absolute $ED;  // PSC 1 Input B Control
-  PICR1: word absolute $EE;  // PSC 1 Input Capture Register 
-  PICR1L: byte absolute $EE;  // PSC 1 Input Capture Register 
+  PICR1: word absolute $EE;  // PSC 1 Input Capture Register
+  PICR1L: byte absolute $EE;  // PSC 1 Input Capture Register
   PICR1H: byte absolute $EF;  // PSC 1 Input Capture Register ;
   PSOC2: byte absolute $F0;  // PSC2 Synchro and Output Configuration
   POM2: byte absolute $F1;  // PSC 2 Output Matrix
@@ -164,8 +164,8 @@ var
   PCTL2: byte absolute $FB;  // PSC 2 Control Register
   PFRC2A: byte absolute $FC;  // PSC 2 Input B Control
   PFRC2B: byte absolute $FD;  // PSC 2 Input B Control
-  PICR2: word absolute $FE;  // PSC 2 Input Capture Register 
-  PICR2L: byte absolute $FE;  // PSC 2 Input Capture Register 
+  PICR2: word absolute $FE;  // PSC 2 Input Capture Register
+  PICR2L: byte absolute $FE;  // PSC 2 Input Capture Register
   PICR2H: byte absolute $FF;  // PSC 2 Input Capture Register ;
 
 const
@@ -398,14 +398,14 @@ const
   PRPSC1 = $06;
   PRPSC2 = $07;
   // Oscillator Calibration Value
-  OSCCAL0 = $00;  // Oscillator Calibration 
-  OSCCAL1 = $01;  // Oscillator Calibration 
-  OSCCAL2 = $02;  // Oscillator Calibration 
-  OSCCAL3 = $03;  // Oscillator Calibration 
-  OSCCAL4 = $04;  // Oscillator Calibration 
-  OSCCAL5 = $05;  // Oscillator Calibration 
-  OSCCAL6 = $06;  // Oscillator Calibration 
-  OSCCAL7 = $07;  // Oscillator Calibration 
+  OSCCAL0 = $00;  // Oscillator Calibration
+  OSCCAL1 = $01;  // Oscillator Calibration
+  OSCCAL2 = $02;  // Oscillator Calibration
+  OSCCAL3 = $03;  // Oscillator Calibration
+  OSCCAL4 = $04;  // Oscillator Calibration
+  OSCCAL5 = $05;  // Oscillator Calibration
+  OSCCAL6 = $06;  // Oscillator Calibration
+  OSCCAL7 = $07;  // Oscillator Calibration
   // External Interrupt Control Register A
   ISC00 = $00;  // External Interrupt Sense Control Bit
   ISC01 = $01;  // External Interrupt Sense Control Bit
@@ -772,7 +772,7 @@ const
   PELEV0B = $05;
   PISEL0B = $06;
   PCAE0B = $07;
-  // PSC 0 Input Capture Register 
+  // PSC 0 Input Capture Register
   PICR00 = $00;  // PSC 0 Input Capture Bytes
   PICR01 = $01;  // PSC 0 Input Capture Bytes
   PICR02 = $02;  // PSC 0 Input Capture Bytes
@@ -911,7 +911,7 @@ const
   PELEV2B = $05;
   PISEL2B = $06;
   PCAE2B = $07;
-  // PSC 2 Input Capture Register 
+  // PSC 2 Input Capture Register
   PICR20 = $00;  // PSC 2 Input Capture Bytes
   PICR21 = $01;  // PSC 2 Input Capture Bytes
   PICR22 = $02;  // PSC 2 Input Capture Bytes
@@ -939,7 +939,7 @@ procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt
 procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
 procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
 procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B
-procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14 
+procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14
 procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
 procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
 procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow
@@ -954,8 +954,8 @@ procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 25 Watchdog Timeout Int
 procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 26 EEPROM Ready
 procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 27 Timer Counter 0 Compare Match B
 procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 28 External Interrupt Request 3
-procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29 
-procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30 
+procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29
+procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 31 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90pwm316.pp

@@ -35,13 +35,13 @@ var
   DACON : byte absolute $00+$AA; // DAC Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   GPIOR3 : byte absolute $00+$3B; // General Purpose IO Register 3
   GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2
@@ -89,8 +89,8 @@ var
   ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
   DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0
-  AMP0CSR : byte absolute $00+$76; // 
-  AMP1CSR : byte absolute $00+$77; // 
+  AMP0CSR : byte absolute $00+$76; //
+  AMP1CSR : byte absolute $00+$77; //
   // USART
   UDR : byte absolute $00+$C6; // USART I/O Data Register
   UCSRA : byte absolute $00+$C0; // USART Control and Status register A
@@ -115,71 +115,71 @@ var
   EEDR : byte absolute $00+$40; // EEPROM Data Register
   EECR : byte absolute $00+$3F; // EEPROM Control Register
   // PSC0
-  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register 
+  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register
   PFRC0B : byte absolute $00+$DD; // PSC 0 Input B Control
   PFRC0A : byte absolute $00+$DC; // PSC 0 Input A Control
   PCTL0 : byte absolute $00+$DB; // PSC 0 Control Register
   PCNF0 : byte absolute $00+$DA; // PSC 0 Configuration Register
-  OCR0RB : word absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register 
-  OCR0SB : word absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register 
-  OCR0RA : word absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register 
-  OCR0SA : word absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register 
+  OCR0RB : word absolute $00+$D8; // Output Compare RB Register
+  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register
+  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register
+  OCR0SB : word absolute $00+$D6; // Output Compare SB Register
+  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register
+  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register
+  OCR0RA : word absolute $00+$D4; // Output Compare RA Register
+  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register
+  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register
+  OCR0SA : word absolute $00+$D2; // Output Compare SA Register
+  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register
+  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register
   PSOC0 : byte absolute $00+$D0; // PSC0 Synchro and Output Configuration
   PIM0 : byte absolute $00+$A1; // PSC0 Interrupt Mask Register
   PIFR0 : byte absolute $00+$A0; // PSC0 Interrupt Flag Register
   // PSC1
-  PICR1 : word absolute $00+$EE; // PSC 1 Input Capture Register 
-  PICR1L : byte absolute $00+$EE; // PSC 1 Input Capture Register 
-  PICR1H : byte absolute $00+$EE+1; // PSC 1 Input Capture Register 
+  PICR1 : word absolute $00+$EE; // PSC 1 Input Capture Register
+  PICR1L : byte absolute $00+$EE; // PSC 1 Input Capture Register
+  PICR1H : byte absolute $00+$EE+1; // PSC 1 Input Capture Register
   PFRC1B : byte absolute $00+$ED; // PSC 1 Input B Control
   PFRC1A : byte absolute $00+$EC; // PSC 1 Input B Control
   PCTL1 : byte absolute $00+$EB; // PSC 1 Control Register
   PCNF1 : byte absolute $00+$EA; // PSC 1 Configuration Register
-  OCR1RB : word absolute $00+$E8; // Output Compare RB Register 
-  OCR1RBL : byte absolute $00+$E8; // Output Compare RB Register 
-  OCR1RBH : byte absolute $00+$E8+1; // Output Compare RB Register 
-  OCR1SB : word absolute $00+$E6; // Output Compare SB Register 
-  OCR1SBL : byte absolute $00+$E6; // Output Compare SB Register 
-  OCR1SBH : byte absolute $00+$E6+1; // Output Compare SB Register 
-  OCR1RA : word absolute $00+$E4; // Output Compare RA Register 
-  OCR1RAL : byte absolute $00+$E4; // Output Compare RA Register 
-  OCR1RAH : byte absolute $00+$E4+1; // Output Compare RA Register 
-  OCR1SA : word absolute $00+$E2; // Output Compare SA Register 
-  OCR1SAL : byte absolute $00+$E2; // Output Compare SA Register 
-  OCR1SAH : byte absolute $00+$E2+1; // Output Compare SA Register 
+  OCR1RB : word absolute $00+$E8; // Output Compare RB Register
+  OCR1RBL : byte absolute $00+$E8; // Output Compare RB Register
+  OCR1RBH : byte absolute $00+$E8+1; // Output Compare RB Register
+  OCR1SB : word absolute $00+$E6; // Output Compare SB Register
+  OCR1SBL : byte absolute $00+$E6; // Output Compare SB Register
+  OCR1SBH : byte absolute $00+$E6+1; // Output Compare SB Register
+  OCR1RA : word absolute $00+$E4; // Output Compare RA Register
+  OCR1RAL : byte absolute $00+$E4; // Output Compare RA Register
+  OCR1RAH : byte absolute $00+$E4+1; // Output Compare RA Register
+  OCR1SA : word absolute $00+$E2; // Output Compare SA Register
+  OCR1SAL : byte absolute $00+$E2; // Output Compare SA Register
+  OCR1SAH : byte absolute $00+$E2+1; // Output Compare SA Register
   PSOC1 : byte absolute $00+$E0; // PSC1 Synchro and Output Configuration
   PIM1 : byte absolute $00+$A3; // PSC1 Interrupt Mask Register
   PIFR1 : byte absolute $00+$A2; // PSC1 Interrupt Flag Register
   // PSC2
-  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register 
+  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register
   PFRC2B : byte absolute $00+$FD; // PSC 2 Input B Control
   PFRC2A : byte absolute $00+$FC; // PSC 2 Input B Control
   PCTL2 : byte absolute $00+$FB; // PSC 2 Control Register
   PCNF2 : byte absolute $00+$FA; // PSC 2 Configuration Register
-  OCR2RB : word absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register 
-  OCR2SB : word absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register 
-  OCR2RA : word absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register 
-  OCR2SA : word absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register 
+  OCR2RB : word absolute $00+$F8; // Output Compare RB Register
+  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register
+  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register
+  OCR2SB : word absolute $00+$F6; // Output Compare SB Register
+  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register
+  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register
+  OCR2RA : word absolute $00+$F4; // Output Compare RA Register
+  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register
+  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register
+  OCR2SA : word absolute $00+$F2; // Output Compare SA Register
+  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register
+  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register
   POM2 : byte absolute $00+$F1; // PSC 2 Output Matrix
   PSOC2 : byte absolute $00+$F0; // PSC2 Synchro and Output Configuration
   PIM2 : byte absolute $00+$A5; // PSC2 Interrupt Mask Register
@@ -260,8 +260,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -304,7 +304,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // GTCCR
   TSM = 7; // Timer/Counter Synchronization Mode
@@ -329,8 +329,8 @@ const
   ICES1 = 6; // Input Capture 1 Edge Select
   CS1 = 0; // Prescaler source of Timer/Counter 1
   // TCCR1C
-  FOC1A = 7; // 
-  FOC1B = 6; // 
+  FOC1A = 7; //
+  FOC1B = 6; //
   // GTCCR
   PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
   // ADMUX
@@ -345,22 +345,22 @@ const
   ADIE = 3; // ADC Interrupt Enable
   ADPS = 0; // ADC  Prescaler Select Bits
   // DIDR1
-  ACMP0D = 5; // 
-  AMP0PD = 4; // 
-  AMP0ND = 3; // 
-  ADC10D = 2; // 
-  ADC9D = 1; // 
-  ADC8D = 0; // 
+  ACMP0D = 5; //
+  AMP0PD = 4; //
+  AMP0ND = 3; //
+  ADC10D = 2; //
+  ADC9D = 1; //
+  ADC8D = 0; //
   // AMP0CSR
-  AMP0EN = 7; // 
-  AMP0IS = 6; // 
-  AMP0G = 4; // 
-  AMP0TS = 0; // 
+  AMP0EN = 7; //
+  AMP0IS = 6; //
+  AMP0G = 4; //
+  AMP0TS = 0; //
   // AMP1CSR
-  AMP1EN = 7; // 
-  AMP1IS = 6; // 
-  AMP1G = 4; // 
-  AMP1TS = 0; // 
+  AMP1EN = 7; //
+  AMP1IS = 6; //
+  AMP1G = 4; //
+  AMP1TS = 0; //
   // UCSRA
   RXC = 7; // USART Receive Complete
   TXC = 6; // USART Transmitt Complete
@@ -577,7 +577,7 @@ procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt
 procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
 procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
 procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B
-procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14 
+procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14
 procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
 procedure TIMER0_COMP_A_ISR; external name 'TIMER0_COMP_A_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
 procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow
@@ -592,8 +592,8 @@ procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 25 Watchdog Timeout Int
 procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 26 EEPROM Ready
 procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 27 Timer Counter 0 Compare Match B
 procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 28 External Interrupt Request 3
-procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29 
-procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30 
+procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29
+procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 31 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90pwm3b.pp

@@ -35,13 +35,13 @@ var
   DACON : byte absolute $00+$AA; // DAC Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   GPIOR3 : byte absolute $00+$3B; // General Purpose IO Register 3
   GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2
@@ -89,8 +89,8 @@ var
   ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
   DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0
-  AMP0CSR : byte absolute $00+$76; // 
-  AMP1CSR : byte absolute $00+$77; // 
+  AMP0CSR : byte absolute $00+$76; //
+  AMP1CSR : byte absolute $00+$77; //
   // USART
   UDR : byte absolute $00+$C6; // USART I/O Data Register
   UCSRA : byte absolute $00+$C0; // USART Control and Status register A
@@ -115,71 +115,71 @@ var
   EEDR : byte absolute $00+$40; // EEPROM Data Register
   EECR : byte absolute $00+$3F; // EEPROM Control Register
   // PSC0
-  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register 
-  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register 
+  PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register
+  PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register
   PFRC0B : byte absolute $00+$DD; // PSC 0 Input B Control
   PFRC0A : byte absolute $00+$DC; // PSC 0 Input A Control
   PCTL0 : byte absolute $00+$DB; // PSC 0 Control Register
   PCNF0 : byte absolute $00+$DA; // PSC 0 Configuration Register
-  OCR0RB : word absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register 
-  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register 
-  OCR0SB : word absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register 
-  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register 
-  OCR0RA : word absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register 
-  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register 
-  OCR0SA : word absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register 
-  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register 
+  OCR0RB : word absolute $00+$D8; // Output Compare RB Register
+  OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register
+  OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register
+  OCR0SB : word absolute $00+$D6; // Output Compare SB Register
+  OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register
+  OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register
+  OCR0RA : word absolute $00+$D4; // Output Compare RA Register
+  OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register
+  OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register
+  OCR0SA : word absolute $00+$D2; // Output Compare SA Register
+  OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register
+  OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register
   PSOC0 : byte absolute $00+$D0; // PSC0 Synchro and Output Configuration
   PIM0 : byte absolute $00+$A1; // PSC0 Interrupt Mask Register
   PIFR0 : byte absolute $00+$A0; // PSC0 Interrupt Flag Register
   // PSC1
-  PICR1 : word absolute $00+$EE; // PSC 1 Input Capture Register 
-  PICR1L : byte absolute $00+$EE; // PSC 1 Input Capture Register 
-  PICR1H : byte absolute $00+$EE+1; // PSC 1 Input Capture Register 
+  PICR1 : word absolute $00+$EE; // PSC 1 Input Capture Register
+  PICR1L : byte absolute $00+$EE; // PSC 1 Input Capture Register
+  PICR1H : byte absolute $00+$EE+1; // PSC 1 Input Capture Register
   PFRC1B : byte absolute $00+$ED; // PSC 1 Input B Control
   PFRC1A : byte absolute $00+$EC; // PSC 1 Input B Control
   PCTL1 : byte absolute $00+$EB; // PSC 1 Control Register
   PCNF1 : byte absolute $00+$EA; // PSC 1 Configuration Register
-  OCR1RB : word absolute $00+$E8; // Output Compare RB Register 
-  OCR1RBL : byte absolute $00+$E8; // Output Compare RB Register 
-  OCR1RBH : byte absolute $00+$E8+1; // Output Compare RB Register 
-  OCR1SB : word absolute $00+$E6; // Output Compare SB Register 
-  OCR1SBL : byte absolute $00+$E6; // Output Compare SB Register 
-  OCR1SBH : byte absolute $00+$E6+1; // Output Compare SB Register 
-  OCR1RA : word absolute $00+$E4; // Output Compare RA Register 
-  OCR1RAL : byte absolute $00+$E4; // Output Compare RA Register 
-  OCR1RAH : byte absolute $00+$E4+1; // Output Compare RA Register 
-  OCR1SA : word absolute $00+$E2; // Output Compare SA Register 
-  OCR1SAL : byte absolute $00+$E2; // Output Compare SA Register 
-  OCR1SAH : byte absolute $00+$E2+1; // Output Compare SA Register 
+  OCR1RB : word absolute $00+$E8; // Output Compare RB Register
+  OCR1RBL : byte absolute $00+$E8; // Output Compare RB Register
+  OCR1RBH : byte absolute $00+$E8+1; // Output Compare RB Register
+  OCR1SB : word absolute $00+$E6; // Output Compare SB Register
+  OCR1SBL : byte absolute $00+$E6; // Output Compare SB Register
+  OCR1SBH : byte absolute $00+$E6+1; // Output Compare SB Register
+  OCR1RA : word absolute $00+$E4; // Output Compare RA Register
+  OCR1RAL : byte absolute $00+$E4; // Output Compare RA Register
+  OCR1RAH : byte absolute $00+$E4+1; // Output Compare RA Register
+  OCR1SA : word absolute $00+$E2; // Output Compare SA Register
+  OCR1SAL : byte absolute $00+$E2; // Output Compare SA Register
+  OCR1SAH : byte absolute $00+$E2+1; // Output Compare SA Register
   PSOC1 : byte absolute $00+$E0; // PSC1 Synchro and Output Configuration
   PIM1 : byte absolute $00+$A3; // PSC1 Interrupt Mask Register
   PIFR1 : byte absolute $00+$A2; // PSC1 Interrupt Flag Register
   // PSC2
-  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register 
-  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register 
+  PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register
+  PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register
   PFRC2B : byte absolute $00+$FD; // PSC 2 Input B Control
   PFRC2A : byte absolute $00+$FC; // PSC 2 Input B Control
   PCTL2 : byte absolute $00+$FB; // PSC 2 Control Register
   PCNF2 : byte absolute $00+$FA; // PSC 2 Configuration Register
-  OCR2RB : word absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register 
-  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register 
-  OCR2SB : word absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register 
-  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register 
-  OCR2RA : word absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register 
-  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register 
-  OCR2SA : word absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register 
-  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register 
+  OCR2RB : word absolute $00+$F8; // Output Compare RB Register
+  OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register
+  OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register
+  OCR2SB : word absolute $00+$F6; // Output Compare SB Register
+  OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register
+  OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register
+  OCR2RA : word absolute $00+$F4; // Output Compare RA Register
+  OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register
+  OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register
+  OCR2SA : word absolute $00+$F2; // Output Compare SA Register
+  OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register
+  OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register
   POM2 : byte absolute $00+$F1; // PSC 2 Output Matrix
   PSOC2 : byte absolute $00+$F0; // PSC2 Synchro and Output Configuration
   PIM2 : byte absolute $00+$A5; // PSC2 Interrupt Mask Register
@@ -260,8 +260,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -304,7 +304,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // GTCCR
   TSM = 7; // Timer/Counter Synchronization Mode
@@ -329,8 +329,8 @@ const
   ICES1 = 6; // Input Capture 1 Edge Select
   CS1 = 0; // Prescaler source of Timer/Counter 1
   // TCCR1C
-  FOC1A = 7; // 
-  FOC1B = 6; // 
+  FOC1A = 7; //
+  FOC1B = 6; //
   // GTCCR
   PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
   // ADMUX
@@ -345,22 +345,22 @@ const
   ADIE = 3; // ADC Interrupt Enable
   ADPS = 0; // ADC  Prescaler Select Bits
   // DIDR1
-  ACMP0D = 5; // 
-  AMP0PD = 4; // 
-  AMP0ND = 3; // 
-  ADC10D = 2; // 
-  ADC9D = 1; // 
-  ADC8D = 0; // 
+  ACMP0D = 5; //
+  AMP0PD = 4; //
+  AMP0ND = 3; //
+  ADC10D = 2; //
+  ADC9D = 1; //
+  ADC8D = 0; //
   // AMP0CSR
-  AMP0EN = 7; // 
-  AMP0IS = 6; // 
-  AMP0G = 4; // 
-  AMP0TS = 0; // 
+  AMP0EN = 7; //
+  AMP0IS = 6; //
+  AMP0G = 4; //
+  AMP0TS = 0; //
   // AMP1CSR
-  AMP1EN = 7; // 
-  AMP1IS = 6; // 
-  AMP1G = 4; // 
-  AMP1TS = 0; // 
+  AMP1EN = 7; //
+  AMP1IS = 6; //
+  AMP1G = 4; //
+  AMP1TS = 0; //
   // UCSRA
   RXC = 7; // USART Receive Complete
   TXC = 6; // USART Transmitt Complete
@@ -579,7 +579,7 @@ procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt
 procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
 procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
 procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B
-procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14 
+procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14
 procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
 procedure TIMER0_COMP_A_ISR; external name 'TIMER0_COMP_A_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
 procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow
@@ -594,8 +594,8 @@ procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 25 Watchdog Timeout Int
 procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 26 EEPROM Ready
 procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 27 Timer Counter 0 Compare Match B
 procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 28 External Interrupt Request 3
-procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29 
-procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30 
+procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29
+procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 31 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90pwm81.pp

@@ -38,32 +38,32 @@ var
   ADCSRB : byte absolute $00+$27; // ADC Control and Status Register B
   DIDR0 : byte absolute $00+$77; // Digital Input Disable Register 0
   DIDR1 : byte absolute $00+$78; // Digital Input Disable Register 0
-  AMP0CSR : byte absolute $00+$79; // 
+  AMP0CSR : byte absolute $00+$79; //
   // ANALOG_COMPARATOR
   AC3CON : byte absolute $00+$7F; // Analog Comparator3 Control Register
   AC1CON : byte absolute $00+$7D; // Analog Comparator 1 Control Register
   AC2CON : byte absolute $00+$7E; // Analog Comparator 2 Control Register
   ACSR : byte absolute $00+$20; // Analog Comparator Status Register
-  AC3ECON : byte absolute $00+$7C; // 
-  AC2ECON : byte absolute $00+$7B; // 
-  AC1ECON : byte absolute $00+$7A; // 
+  AC3ECON : byte absolute $00+$7C; //
+  AC2ECON : byte absolute $00+$7B; //
+  AC1ECON : byte absolute $00+$7A; //
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$88; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$83; // 
+  CLKPR : byte absolute $00+$83; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   GPIOR2 : byte absolute $00+$3B; // General Purpose IO Register 2
   GPIOR1 : byte absolute $00+$3A; // General Purpose IO Register 1
   GPIOR0 : byte absolute $00+$39; // General Purpose IO Register 0
   PLLCSR : byte absolute $00+$87; // PLL Control And Status Register
   PRR : byte absolute $00+$86; // Power Reduction Register
-  CLKCSR : byte absolute $00+$84; // 
-  CLKSELR : byte absolute $00+$85; // 
+  CLKCSR : byte absolute $00+$84; //
+  CLKSELR : byte absolute $00+$85; //
   BGCCR : byte absolute $00+$81; // BandGap Current Calibration Register
   BGCRR : byte absolute $00+$80; // BandGap Resistor Calibration Register
   // EEPROM
@@ -73,25 +73,25 @@ var
   EEDR : byte absolute $00+$3D; // EEPROM Data Register
   EECR : byte absolute $00+$3C; // EEPROM Control Register
   // PSC0
-  PICR0 : word absolute $00+$68; // PSC 0 Input Capture Register 
-  PICR0L : byte absolute $00+$68; // PSC 0 Input Capture Register 
-  PICR0H : byte absolute $00+$68+1; // PSC 0 Input Capture Register 
+  PICR0 : word absolute $00+$68; // PSC 0 Input Capture Register
+  PICR0L : byte absolute $00+$68; // PSC 0 Input Capture Register
+  PICR0H : byte absolute $00+$68+1; // PSC 0 Input Capture Register
   PFRC0B : byte absolute $00+$63; // PSC 0 Input B Control
   PFRC0A : byte absolute $00+$62; // PSC 0 Input A Control
   PCTL0 : byte absolute $00+$32; // PSC 0 Control Register
   PCNF0 : byte absolute $00+$31; // PSC 0 Configuration Register
-  OCR0RB : word absolute $00+$44; // Output Compare RB Register 
-  OCR0RBL : byte absolute $00+$44; // Output Compare RB Register 
-  OCR0RBH : byte absolute $00+$44+1; // Output Compare RB Register 
-  OCR0SB : word absolute $00+$42; // Output Compare SB Register 
-  OCR0SBL : byte absolute $00+$42; // Output Compare SB Register 
-  OCR0SBH : byte absolute $00+$42+1; // Output Compare SB Register 
-  OCR0RA : word absolute $00+$4A; // Output Compare RA Register 
-  OCR0RAL : byte absolute $00+$4A; // Output Compare RA Register 
-  OCR0RAH : byte absolute $00+$4A+1; // Output Compare RA Register 
-  OCR0SA : word absolute $00+$60; // Output Compare SA Register 
-  OCR0SAL : byte absolute $00+$60; // Output Compare SA Register 
-  OCR0SAH : byte absolute $00+$60+1; // Output Compare SA Register 
+  OCR0RB : word absolute $00+$44; // Output Compare RB Register
+  OCR0RBL : byte absolute $00+$44; // Output Compare RB Register
+  OCR0RBH : byte absolute $00+$44+1; // Output Compare RB Register
+  OCR0SB : word absolute $00+$42; // Output Compare SB Register
+  OCR0SBL : byte absolute $00+$42; // Output Compare SB Register
+  OCR0SBH : byte absolute $00+$42+1; // Output Compare SB Register
+  OCR0RA : word absolute $00+$4A; // Output Compare RA Register
+  OCR0RAL : byte absolute $00+$4A; // Output Compare RA Register
+  OCR0RAH : byte absolute $00+$4A+1; // Output Compare RA Register
+  OCR0SA : word absolute $00+$60; // Output Compare SA Register
+  OCR0SAL : byte absolute $00+$60; // Output Compare SA Register
+  OCR0SAH : byte absolute $00+$60+1; // Output Compare SA Register
   PSOC0 : byte absolute $00+$6A; // PSC0 Synchro and Output Configuration
   PIM0 : byte absolute $00+$2F; // PSC0 Interrupt Mask Register
   PIFR0 : byte absolute $00+$30; // PSC0 Interrupt Flag Register
@@ -103,18 +103,18 @@ var
   PCTL2 : byte absolute $00+$36; // PSC 2 Control Register
   PCNF2 : byte absolute $00+$35; // PSC 2 Configuration Register
   PCNFE2 : byte absolute $00+$70; // PSC 2 Enhanced Configuration Register
-  OCR2RB : word absolute $00+$48; // Output Compare RB Register 
-  OCR2RBL : byte absolute $00+$48; // Output Compare RB Register 
-  OCR2RBH : byte absolute $00+$48+1; // Output Compare RB Register 
-  OCR2SB : word absolute $00+$46; // Output Compare SB Register 
-  OCR2SBL : byte absolute $00+$46; // Output Compare SB Register 
-  OCR2SBH : byte absolute $00+$46+1; // Output Compare SB Register 
-  OCR2RA : word absolute $00+$4E; // Output Compare RA Register 
-  OCR2RAL : byte absolute $00+$4E; // Output Compare RA Register 
-  OCR2RAH : byte absolute $00+$4E+1; // Output Compare RA Register 
-  OCR2SA : word absolute $00+$64; // Output Compare SA Register 
-  OCR2SAL : byte absolute $00+$64; // Output Compare SA Register 
-  OCR2SAH : byte absolute $00+$64+1; // Output Compare SA Register 
+  OCR2RB : word absolute $00+$48; // Output Compare RB Register
+  OCR2RBL : byte absolute $00+$48; // Output Compare RB Register
+  OCR2RBH : byte absolute $00+$48+1; // Output Compare RB Register
+  OCR2SB : word absolute $00+$46; // Output Compare SB Register
+  OCR2SBL : byte absolute $00+$46; // Output Compare SB Register
+  OCR2SBH : byte absolute $00+$46+1; // Output Compare SB Register
+  OCR2RA : word absolute $00+$4E; // Output Compare RA Register
+  OCR2RAL : byte absolute $00+$4E; // Output Compare RA Register
+  OCR2RAH : byte absolute $00+$4E+1; // Output Compare RA Register
+  OCR2SA : word absolute $00+$64; // Output Compare SA Register
+  OCR2SAL : byte absolute $00+$64; // Output Compare SA Register
+  OCR2SAH : byte absolute $00+$64+1; // Output Compare SA Register
   POM2 : byte absolute $00+$6F; // PSC 2 Output Matrix
   PSOC2 : byte absolute $00+$6E; // PSC2 Synchro and Output Configuration
   PIM2 : byte absolute $00+$33; // PSC2 Interrupt Mask Register
@@ -184,7 +184,7 @@ const
   ADSSEN = 4; // ADC Single Shot Enable on PSC's Synchronisation Signals
   ADTS = 0; // ADC Auto Trigger Sources
   // DIDR0
-  ADC7D = 7; // 
+  ADC7D = 7; //
   ADC6D = 6; // ADC7 Digital input Disable
   ADC5D = 5; // ADC5 Digital input Disable
   ADC4D = 4; // ADC4 Digital input Disable
@@ -193,16 +193,16 @@ const
   ADC1D = 1; // ADC1 Digital input Disable
   ADC0D = 0; // ADC0 Digital input Disable
   // DIDR1
-  ACMP1MD = 3; // 
-  AMP0POSD = 2; // 
-  ADC10D = 1; // 
-  ADC9D = 0; // 
+  ACMP1MD = 3; //
+  AMP0POSD = 2; //
+  ADC10D = 1; //
+  ADC9D = 0; //
   // AMP0CSR
-  AMP0EN = 7; // 
-  AMP0IS = 6; // 
-  AMP0G = 4; // 
-  AMP0GS = 3; // 
-  AMP0TS = 0; // 
+  AMP0EN = 7; //
+  AMP0IS = 6; //
+  AMP0G = 4; //
+  AMP0GS = 3; //
+  AMP0TS = 0; //
   // AC3CON
   AC3EN = 7; // Analog Comparator3 Enable Bit
   AC3IE = 6; // Analog Comparator 3 Interrupt Enable Bit
@@ -260,8 +260,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -278,7 +278,7 @@ const
   GPIOR01 = 1; // General Purpose IO Register 0 bit 1
   GPIOR00 = 0; // General Purpose IO Register 0 bit 0
   // PLLCSR
-  PLLF = 2; // 
+  PLLF = 2; //
   PLLE = 1; // PLL Enable
   PLOCK = 0; // PLL Lock Detector
   // PRR
@@ -296,9 +296,9 @@ const
   CSUT = 4; // Clock Start up Time
   CKSEL = 0; // Clock Source Select
   // BGCCR
-  BGCC = 0; // 
+  BGCC = 0; //
   // BGCRR
-  BGCR = 0; // 
+  BGCR = 0; //
   // EECR
   NVMBSY = 7; // None Volatile Busy Memory Busy
   EEPAGE = 6; // EEPROM Page Access
@@ -353,8 +353,8 @@ const
   PEOP0 = 0; // End of PSC0 Interrupt
   // PICR2H
   PCST2 = 7; // PSC 2 Capture Software Trigger Bit
-  PICR21 = 2; // 
-  PICR2 = 0; // 
+  PICR21 = 2; //
+  PICR2 = 0; //
   // PFRC2B
   PCAE2B = 7; // PSC 2 Capture Enable Input Part B
   PISEL2B = 6; // PSC 2 Input Select for Part B
@@ -384,12 +384,12 @@ const
   PCLKSEL2 = 1; // PSC 2 Input Clock Select
   POME2 = 0; // PSC 2 Output Matrix Enable
   // PCNFE2
-  PASDLK2 = 5; // 
-  PBFM21 = 4; // 
-  PELEV2A1 = 3; // 
-  PELEV2B1 = 2; // 
-  PISEL2A1 = 1; // 
-  PISEL2B1 = 0; // 
+  PASDLK2 = 5; //
+  PBFM21 = 4; //
+  PELEV2A1 = 3; //
+  PELEV2B1 = 2; //
+  PISEL2A1 = 1; //
+  PISEL2B1 = 0; //
   // POM2
   POMV2B = 4; // Output Matrix Output B Ramps
   POMV2A = 0; // Output Matrix Output A Ramps

rtl/embedded/avr/at90usb1286.pp

@@ -31,15 +31,15 @@ var
   PINF : byte absolute $00+$2F; // Input Pins, Port F
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   EIND : byte absolute $00+$5C; // Extended Indirect Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
@@ -68,27 +68,27 @@ var
   UBRR1L : byte absolute $00+$CC; // USART Baud Rate Register  Bytes
   UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register  Bytes
   // USB_DEVICE
-  UEINT : byte absolute $00+$F4; // 
-  UEBCHX : byte absolute $00+$F3; // 
-  UEBCLX : byte absolute $00+$F2; // 
-  UEDATX : byte absolute $00+$F1; // 
-  UEIENX : byte absolute $00+$F0; // 
-  UESTA1X : byte absolute $00+$EF; // 
-  UESTA0X : byte absolute $00+$EE; // 
-  UECFG1X : byte absolute $00+$ED; // 
-  UECFG0X : byte absolute $00+$EC; // 
-  UECONX : byte absolute $00+$EB; // 
-  UERST : byte absolute $00+$EA; // 
-  UENUM : byte absolute $00+$E9; // 
-  UEINTX : byte absolute $00+$E8; // 
-  UDMFN : byte absolute $00+$E6; // 
-  UDFNUM : word absolute $00+$E4; // 
-  UDFNUML : byte absolute $00+$E4; // 
-  UDFNUMH : byte absolute $00+$E4+1; // 
-  UDADDR : byte absolute $00+$E3; // 
-  UDIEN : byte absolute $00+$E2; // 
-  UDINT : byte absolute $00+$E1; // 
-  UDCON : byte absolute $00+$E0; // 
+  UEINT : byte absolute $00+$F4; //
+  UEBCHX : byte absolute $00+$F3; //
+  UEBCLX : byte absolute $00+$F2; //
+  UEDATX : byte absolute $00+$F1; //
+  UEIENX : byte absolute $00+$F0; //
+  UESTA1X : byte absolute $00+$EF; //
+  UESTA0X : byte absolute $00+$EE; //
+  UECFG1X : byte absolute $00+$ED; //
+  UECFG0X : byte absolute $00+$EC; //
+  UECONX : byte absolute $00+$EB; //
+  UERST : byte absolute $00+$EA; //
+  UENUM : byte absolute $00+$E9; //
+  UEINTX : byte absolute $00+$E8; //
+  UDMFN : byte absolute $00+$E6; //
+  UDFNUM : word absolute $00+$E4; //
+  UDFNUML : byte absolute $00+$E4; //
+  UDFNUMH : byte absolute $00+$E4+1; //
+  UDADDR : byte absolute $00+$E3; //
+  UDIEN : byte absolute $00+$E2; //
+  UDINT : byte absolute $00+$E1; //
+  UDCON : byte absolute $00+$E0; //
   // BOOT_LOAD
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   // EEPROM
@@ -177,12 +177,12 @@ var
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // PLL
   PLLCSR : byte absolute $00+$49; // PLL Status and Control register
   // USB_GLOBAL
-  USBINT : byte absolute $00+$DA; // 
-  USBSTA : byte absolute $00+$D9; // 
+  USBINT : byte absolute $00+$DA; //
+  USBSTA : byte absolute $00+$D9; //
   USBCON : byte absolute $00+$D8; // USB General Control Register
   UHWCON : byte absolute $00+$D7; // USB Hardware Configuration Register
 
@@ -222,8 +222,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -251,7 +251,7 @@ const
   PRSPI = 2; // Power Reduction Serial Peripheral Interface
   PRADC = 0; // Power Reduction ADC
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -303,68 +303,68 @@ const
   UCSZ1 = 1; // Character Size
   UCPOL1 = 0; // Clock Polarity
   // UEIENX
-  FLERRE = 7; // 
-  NAKINE = 6; // 
-  NAKOUTE = 4; // 
-  RXSTPE = 3; // 
-  RXOUTE = 2; // 
-  STALLEDE = 1; // 
-  TXINE = 0; // 
+  FLERRE = 7; //
+  NAKINE = 6; //
+  NAKOUTE = 4; //
+  RXSTPE = 3; //
+  RXOUTE = 2; //
+  STALLEDE = 1; //
+  TXINE = 0; //
   // UESTA1X
-  CTRLDIR = 2; // 
-  CURRBK = 0; // 
+  CTRLDIR = 2; //
+  CURRBK = 0; //
   // UESTA0X
-  CFGOK = 7; // 
-  OVERFI = 6; // 
-  UNDERFI = 5; // 
-  DTSEQ = 2; // 
-  NBUSYBK = 0; // 
+  CFGOK = 7; //
+  OVERFI = 6; //
+  UNDERFI = 5; //
+  DTSEQ = 2; //
+  NBUSYBK = 0; //
   // UECFG1X
-  EPSIZE = 4; // 
-  EPBK = 2; // 
-  ALLOC = 1; // 
+  EPSIZE = 4; //
+  EPBK = 2; //
+  ALLOC = 1; //
   // UECFG0X
-  EPTYPE = 6; // 
-  EPDIR = 0; // 
+  EPTYPE = 6; //
+  EPDIR = 0; //
   // UECONX
-  STALLRQ = 5; // 
-  STALLRQC = 4; // 
-  RSTDT = 3; // 
-  EPEN = 0; // 
+  STALLRQ = 5; //
+  STALLRQC = 4; //
+  RSTDT = 3; //
+  EPEN = 0; //
   // UERST
-  EPRST = 0; // 
+  EPRST = 0; //
   // UEINTX
-  FIFOCON = 7; // 
-  NAKINI = 6; // 
-  RWAL = 5; // 
-  NAKOUTI = 4; // 
-  RXSTPI = 3; // 
-  RXOUTI = 2; // 
-  STALLEDI = 1; // 
-  TXINI = 0; // 
+  FIFOCON = 7; //
+  NAKINI = 6; //
+  RWAL = 5; //
+  NAKOUTI = 4; //
+  RXSTPI = 3; //
+  RXOUTI = 2; //
+  STALLEDI = 1; //
+  TXINI = 0; //
   // UDMFN
-  FNCERR = 4; // 
+  FNCERR = 4; //
   // UDADDR
-  ADDEN = 7; // 
-  UADD = 0; // 
+  ADDEN = 7; //
+  UADD = 0; //
   // UDIEN
-  UPRSME = 6; // 
-  EORSME = 5; // 
-  WAKEUPE = 4; // 
-  EORSTE = 3; // 
-  SOFE = 2; // 
-  SUSPE = 0; // 
+  UPRSME = 6; //
+  EORSME = 5; //
+  WAKEUPE = 4; //
+  EORSTE = 3; //
+  SOFE = 2; //
+  SUSPE = 0; //
   // UDINT
-  UPRSMI = 6; // 
-  EORSMI = 5; // 
-  WAKEUPI = 4; // 
-  EORSTI = 3; // 
-  SOFI = 2; // 
-  SUSPI = 0; // 
+  UPRSMI = 6; //
+  EORSMI = 5; //
+  WAKEUPI = 4; //
+  EORSTI = 3; //
+  SOFI = 2; //
+  SUSPI = 0; //
   // UDCON
-  LSM = 2; // 
-  RMWKUP = 1; // 
-  DETACH = 0; // 
+  LSM = 2; //
+  RMWKUP = 1; //
+  DETACH = 0; //
   // SPMCSR
   SPMIE = 7; // SPM Interrupt Enable
   RWWSB = 6; // Read While Write Section Busy
@@ -383,7 +383,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -538,24 +538,24 @@ const
   PLLE = 1; // PLL Enable Bit
   PLOCK = 0; // PLL Lock Status Bit
   // USBINT
-  IDTI = 1; // 
-  VBUSTI = 0; // 
+  IDTI = 1; //
+  VBUSTI = 0; //
   // USBSTA
-  SPEED = 3; // 
-  ID = 1; // 
-  VBUS = 0; // 
+  SPEED = 3; //
+  ID = 1; //
+  VBUS = 0; //
   // USBCON
-  USBE = 7; // 
-  HOST = 6; // 
-  FRZCLK = 5; // 
-  OTGPADE = 4; // 
-  IDTE = 1; // 
-  VBUSTE = 0; // 
+  USBE = 7; //
+  HOST = 6; //
+  FRZCLK = 5; //
+  OTGPADE = 4; //
+  IDTE = 1; //
+  VBUSTE = 0; //
   // UHWCON
-  UIMOD = 7; // 
-  UIDE = 6; // 
-  UVCONE = 4; // 
-  UVREGE = 0; // 
+  UIMOD = 7; //
+  UIDE = 6; //
+  UVCONE = 4; //
+  UVREGE = 0; //
 
 implementation
 
@@ -596,7 +596,7 @@ procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Ti
 procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
 procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
 procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
-procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface        
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 37 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90usb1287.pp

@@ -31,15 +31,15 @@ var
   PINF : byte absolute $00+$2F; // Input Pins, Port F
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   EIND : byte absolute $00+$5C; // Extended Indirect Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
@@ -68,60 +68,60 @@ var
   UBRR1L : byte absolute $00+$CC; // USART Baud Rate Register  Bytes
   UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register  Bytes
   // USB_DEVICE
-  UEINT : byte absolute $00+$F4; // 
-  UEBCHX : byte absolute $00+$F3; // 
-  UEBCLX : byte absolute $00+$F2; // 
-  UEDATX : byte absolute $00+$F1; // 
-  UEIENX : byte absolute $00+$F0; // 
-  UESTA1X : byte absolute $00+$EF; // 
-  UESTA0X : byte absolute $00+$EE; // 
-  UECFG1X : byte absolute $00+$ED; // 
-  UECFG0X : byte absolute $00+$EC; // 
-  UECONX : byte absolute $00+$EB; // 
-  UERST : byte absolute $00+$EA; // 
-  UENUM : byte absolute $00+$E9; // 
-  UEINTX : byte absolute $00+$E8; // 
-  UDMFN : byte absolute $00+$E6; // 
-  UDFNUM : word absolute $00+$E4; // 
-  UDFNUML : byte absolute $00+$E4; // 
-  UDFNUMH : byte absolute $00+$E4+1; // 
-  UDADDR : byte absolute $00+$E3; // 
-  UDIEN : byte absolute $00+$E2; // 
-  UDINT : byte absolute $00+$E1; // 
-  UDCON : byte absolute $00+$E0; // 
+  UEINT : byte absolute $00+$F4; //
+  UEBCHX : byte absolute $00+$F3; //
+  UEBCLX : byte absolute $00+$F2; //
+  UEDATX : byte absolute $00+$F1; //
+  UEIENX : byte absolute $00+$F0; //
+  UESTA1X : byte absolute $00+$EF; //
+  UESTA0X : byte absolute $00+$EE; //
+  UECFG1X : byte absolute $00+$ED; //
+  UECFG0X : byte absolute $00+$EC; //
+  UECONX : byte absolute $00+$EB; //
+  UERST : byte absolute $00+$EA; //
+  UENUM : byte absolute $00+$E9; //
+  UEINTX : byte absolute $00+$E8; //
+  UDMFN : byte absolute $00+$E6; //
+  UDFNUM : word absolute $00+$E4; //
+  UDFNUML : byte absolute $00+$E4; //
+  UDFNUMH : byte absolute $00+$E4+1; //
+  UDADDR : byte absolute $00+$E3; //
+  UDIEN : byte absolute $00+$E2; //
+  UDINT : byte absolute $00+$E1; //
+  UDCON : byte absolute $00+$E0; //
   // USB_GLOBAL
-  OTGINT : byte absolute $00+$DF; // 
-  OTGIEN : byte absolute $00+$DE; // 
-  OTGCON : byte absolute $00+$DD; // 
-  OTGTCON : byte absolute $00+$F9; // 
-  USBINT : byte absolute $00+$DA; // 
-  USBSTA : byte absolute $00+$D9; // 
+  OTGINT : byte absolute $00+$DF; //
+  OTGIEN : byte absolute $00+$DE; //
+  OTGCON : byte absolute $00+$DD; //
+  OTGTCON : byte absolute $00+$F9; //
+  USBINT : byte absolute $00+$DA; //
+  USBSTA : byte absolute $00+$D9; //
   USBCON : byte absolute $00+$D8; // USB General Control Register
   UHWCON : byte absolute $00+$D7; // USB Hardware Configuration Register
   // USB_HOST
-  UPERRX : byte absolute $00+$F5; // 
-  UPINT : byte absolute $00+$F8; // 
-  UPBCHX : byte absolute $00+$F7; // 
-  UPBCLX : byte absolute $00+$F6; // 
-  UPDATX : byte absolute $00+$AF; // 
-  UPIENX : byte absolute $00+$AE; // 
-  UPCFG2X : byte absolute $00+$AD; // 
-  UPSTAX : byte absolute $00+$AC; // 
-  UPCFG1X : byte absolute $00+$AB; // 
-  UPCFG0X : byte absolute $00+$AA; // 
-  UPCONX : byte absolute $00+$A9; // 
-  UPRST : byte absolute $00+$A8; // 
-  UPNUM : byte absolute $00+$A7; // 
-  UPINTX : byte absolute $00+$A6; // 
-  UPINRQX : byte absolute $00+$A5; // 
-  UHFLEN : byte absolute $00+$A4; // 
-  UHFNUM : word absolute $00+$A2; // 
-  UHFNUML : byte absolute $00+$A2; // 
-  UHFNUMH : byte absolute $00+$A2+1; // 
-  UHADDR : byte absolute $00+$A1; // 
-  UHIEN : byte absolute $00+$A0; // 
-  UHINT : byte absolute $00+$9F; // 
-  UHCON : byte absolute $00+$9E; // 
+  UPERRX : byte absolute $00+$F5; //
+  UPINT : byte absolute $00+$F8; //
+  UPBCHX : byte absolute $00+$F7; //
+  UPBCLX : byte absolute $00+$F6; //
+  UPDATX : byte absolute $00+$AF; //
+  UPIENX : byte absolute $00+$AE; //
+  UPCFG2X : byte absolute $00+$AD; //
+  UPSTAX : byte absolute $00+$AC; //
+  UPCFG1X : byte absolute $00+$AB; //
+  UPCFG0X : byte absolute $00+$AA; //
+  UPCONX : byte absolute $00+$A9; //
+  UPRST : byte absolute $00+$A8; //
+  UPNUM : byte absolute $00+$A7; //
+  UPINTX : byte absolute $00+$A6; //
+  UPINRQX : byte absolute $00+$A5; //
+  UHFLEN : byte absolute $00+$A4; //
+  UHFNUM : word absolute $00+$A2; //
+  UHFNUML : byte absolute $00+$A2; //
+  UHFNUMH : byte absolute $00+$A2+1; //
+  UHADDR : byte absolute $00+$A1; //
+  UHIEN : byte absolute $00+$A0; //
+  UHINT : byte absolute $00+$9F; //
+  UHCON : byte absolute $00+$9E; //
   // BOOT_LOAD
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   // EEPROM
@@ -210,7 +210,7 @@ var
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // PLL
   PLLCSR : byte absolute $00+$49; // PLL Status and Control register
 
@@ -250,8 +250,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -279,7 +279,7 @@ const
   PRSPI = 2; // Power Reduction Serial Peripheral Interface
   PRADC = 0; // Power Reduction ADC
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -331,168 +331,168 @@ const
   UCSZ1 = 1; // Character Size
   UCPOL1 = 0; // Clock Polarity
   // UEIENX
-  FLERRE = 7; // 
-  NAKINE = 6; // 
-  NAKOUTE = 4; // 
-  RXSTPE = 3; // 
-  RXOUTE = 2; // 
-  STALLEDE = 1; // 
-  TXINE = 0; // 
+  FLERRE = 7; //
+  NAKINE = 6; //
+  NAKOUTE = 4; //
+  RXSTPE = 3; //
+  RXOUTE = 2; //
+  STALLEDE = 1; //
+  TXINE = 0; //
   // UESTA1X
-  CTRLDIR = 2; // 
-  CURRBK = 0; // 
+  CTRLDIR = 2; //
+  CURRBK = 0; //
   // UESTA0X
-  CFGOK = 7; // 
-  OVERFI = 6; // 
-  UNDERFI = 5; // 
-  DTSEQ = 2; // 
-  NBUSYBK = 0; // 
+  CFGOK = 7; //
+  OVERFI = 6; //
+  UNDERFI = 5; //
+  DTSEQ = 2; //
+  NBUSYBK = 0; //
   // UECFG1X
-  EPSIZE = 4; // 
-  EPBK = 2; // 
-  ALLOC = 1; // 
+  EPSIZE = 4; //
+  EPBK = 2; //
+  ALLOC = 1; //
   // UECFG0X
-  EPTYPE = 6; // 
-  EPDIR = 0; // 
+  EPTYPE = 6; //
+  EPDIR = 0; //
   // UECONX
-  STALLRQ = 5; // 
-  STALLRQC = 4; // 
-  RSTDT = 3; // 
-  EPEN = 0; // 
+  STALLRQ = 5; //
+  STALLRQC = 4; //
+  RSTDT = 3; //
+  EPEN = 0; //
   // UERST
-  EPRST = 0; // 
+  EPRST = 0; //
   // UEINTX
-  FIFOCON = 7; // 
-  NAKINI = 6; // 
-  RWAL = 5; // 
-  NAKOUTI = 4; // 
-  RXSTPI = 3; // 
-  RXOUTI = 2; // 
-  STALLEDI = 1; // 
-  TXINI = 0; // 
+  FIFOCON = 7; //
+  NAKINI = 6; //
+  RWAL = 5; //
+  NAKOUTI = 4; //
+  RXSTPI = 3; //
+  RXOUTI = 2; //
+  STALLEDI = 1; //
+  TXINI = 0; //
   // UDMFN
-  FNCERR = 4; // 
+  FNCERR = 4; //
   // UDADDR
-  ADDEN = 7; // 
-  UADD = 0; // 
+  ADDEN = 7; //
+  UADD = 0; //
   // UDIEN
-  UPRSME = 6; // 
-  EORSME = 5; // 
-  WAKEUPE = 4; // 
-  EORSTE = 3; // 
-  SOFE = 2; // 
-  SUSPE = 0; // 
+  UPRSME = 6; //
+  EORSME = 5; //
+  WAKEUPE = 4; //
+  EORSTE = 3; //
+  SOFE = 2; //
+  SUSPE = 0; //
   // UDINT
-  UPRSMI = 6; // 
-  EORSMI = 5; // 
-  WAKEUPI = 4; // 
-  EORSTI = 3; // 
-  SOFI = 2; // 
-  SUSPI = 0; // 
+  UPRSMI = 6; //
+  EORSMI = 5; //
+  WAKEUPI = 4; //
+  EORSTI = 3; //
+  SOFI = 2; //
+  SUSPI = 0; //
   // UDCON
-  LSM = 2; // 
-  RMWKUP = 1; // 
-  DETACH = 0; // 
+  LSM = 2; //
+  RMWKUP = 1; //
+  DETACH = 0; //
   // OTGINT
-  STOI = 5; // 
-  HNPERRI = 4; // 
-  ROLEEXI = 3; // 
-  BCERRI = 2; // 
-  VBERRI = 1; // 
-  SRPI = 0; // 
+  STOI = 5; //
+  HNPERRI = 4; //
+  ROLEEXI = 3; //
+  BCERRI = 2; //
+  VBERRI = 1; //
+  SRPI = 0; //
   // OTGIEN
-  STOE = 5; // 
-  HNPERRE = 4; // 
-  ROLEEXE = 3; // 
-  BCERRE = 2; // 
-  VBERRE = 1; // 
-  SRPE = 0; // 
+  STOE = 5; //
+  HNPERRE = 4; //
+  ROLEEXE = 3; //
+  BCERRE = 2; //
+  VBERRE = 1; //
+  SRPE = 0; //
   // OTGCON
-  HNPREQ = 5; // 
-  SRPREQ = 4; // 
-  SRPSEL = 3; // 
-  VBUSHWC = 2; // 
-  VBUSREQ = 1; // 
-  VBUSRQC = 0; // 
+  HNPREQ = 5; //
+  SRPREQ = 4; //
+  SRPSEL = 3; //
+  VBUSHWC = 2; //
+  VBUSREQ = 1; //
+  VBUSRQC = 0; //
   // OTGTCON
-  OTGTCON_7 = 7; // 
-  PAGE = 5; // 
-  VALUE_2 = 0; // 
+  OTGTCON_7 = 7; //
+  PAGE = 5; //
+  VALUE_2 = 0; //
   // USBINT
-  IDTI = 1; // 
-  VBUSTI = 0; // 
+  IDTI = 1; //
+  VBUSTI = 0; //
   // USBSTA
-  SPEED = 3; // 
-  ID = 1; // 
-  VBUS = 0; // 
+  SPEED = 3; //
+  ID = 1; //
+  VBUS = 0; //
   // USBCON
-  USBE = 7; // 
-  HOST = 6; // 
-  FRZCLK = 5; // 
-  OTGPADE = 4; // 
-  IDTE = 1; // 
-  VBUSTE = 0; // 
+  USBE = 7; //
+  HOST = 6; //
+  FRZCLK = 5; //
+  OTGPADE = 4; //
+  IDTE = 1; //
+  VBUSTE = 0; //
   // UHWCON
-  UIMOD = 7; // 
-  UIDE = 6; // 
-  UVCONE = 4; // 
-  UVREGE = 0; // 
+  UIMOD = 7; //
+  UIDE = 6; //
+  UVCONE = 4; //
+  UVREGE = 0; //
   // UPERRX
-  COUNTER = 5; // 
-  CRC16 = 4; // 
-  TIMEOUT = 3; // 
-  PID = 2; // 
-  DATAPID = 1; // 
-  DATATGL = 0; // 
+  COUNTER = 5; //
+  CRC16 = 4; //
+  TIMEOUT = 3; //
+  PID = 2; //
+  DATAPID = 1; //
+  DATATGL = 0; //
   // UPIENX
-  NAKEDE = 6; // 
-  PERRE = 4; // 
-  TXSTPE = 3; // 
-  TXOUTE = 2; // 
-  RXSTALLE = 1; // 
-  RXINE = 0; // 
+  NAKEDE = 6; //
+  PERRE = 4; //
+  TXSTPE = 3; //
+  TXOUTE = 2; //
+  RXSTALLE = 1; //
+  RXINE = 0; //
   // UPSTAX
-  NBUSYK = 0; // 
+  NBUSYK = 0; //
   // UPCFG1X
-  PSIZE = 4; // 
-  PBK = 2; // 
+  PSIZE = 4; //
+  PBK = 2; //
   // UPCFG0X
-  PTYPE = 6; // 
-  PTOKEN = 4; // 
-  PEPNUM = 0; // 
+  PTYPE = 6; //
+  PTOKEN = 4; //
+  PEPNUM = 0; //
   // UPCONX
-  PFREEZE = 6; // 
-  INMODE = 5; // 
-  PEN = 0; // 
+  PFREEZE = 6; //
+  INMODE = 5; //
+  PEN = 0; //
   // UPRST
-  PRST = 0; // 
+  PRST = 0; //
   // UPINTX
-  NAKEDI = 6; // 
-  PERRI = 4; // 
-  TXSTPI = 3; // 
-  TXOUTI = 2; // 
-  RXSTALLI = 1; // 
-  RXINI = 0; // 
+  NAKEDI = 6; //
+  PERRI = 4; //
+  TXSTPI = 3; //
+  TXOUTI = 2; //
+  RXSTALLI = 1; //
+  RXINI = 0; //
   // UHIEN
-  HWUPE = 6; // 
-  HSOFE = 5; // 
-  RXRSME = 4; // 
-  RSMEDE = 3; // 
-  RSTE = 2; // 
-  DDISCE = 1; // 
-  DCONNE = 0; // 
+  HWUPE = 6; //
+  HSOFE = 5; //
+  RXRSME = 4; //
+  RSMEDE = 3; //
+  RSTE = 2; //
+  DDISCE = 1; //
+  DCONNE = 0; //
   // UHINT
-  UHUPI = 6; // 
-  HSOFI = 5; // 
-  RXRSMI = 4; // 
-  RSMEDI = 3; // 
-  RSTI = 2; // 
-  DDISCI = 1; // 
-  DCONNI = 0; // 
+  UHUPI = 6; //
+  HSOFI = 5; //
+  RXRSMI = 4; //
+  RSMEDI = 3; //
+  RSTI = 2; //
+  DDISCI = 1; //
+  DCONNI = 0; //
   // UHCON
-  RESUME = 2; // 
-  RESET = 1; // 
-  SOFEN = 0; // 
+  RESUME = 2; //
+  RESET = 1; //
+  SOFEN = 0; //
   // SPMCSR
   SPMIE = 7; // SPM Interrupt Enable
   RWWSB = 6; // Read While Write Section Busy
@@ -511,7 +511,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -705,7 +705,7 @@ procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Ti
 procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
 procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
 procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
-procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface        
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 37 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90usb162.pp

@@ -56,40 +56,40 @@ var
   // PLL
   PLLCSR : byte absolute $00+$49; // PLL Status and Control register
   // USB_DEVICE
-  UEINT : byte absolute $00+$F4; // 
-  UEBCLX : byte absolute $00+$F2; // 
-  UEDATX : byte absolute $00+$F1; // 
-  UEIENX : byte absolute $00+$F0; // 
-  UESTA1X : byte absolute $00+$EF; // 
-  UESTA0X : byte absolute $00+$EE; // 
-  UECFG1X : byte absolute $00+$ED; // 
-  UECFG0X : byte absolute $00+$EC; // 
-  UECONX : byte absolute $00+$EB; // 
-  UERST : byte absolute $00+$EA; // 
-  UENUM : byte absolute $00+$E9; // 
-  UEINTX : byte absolute $00+$E8; // 
-  UDMFN : byte absolute $00+$E6; // 
-  UDFNUM : word absolute $00+$E4; // 
-  UDFNUML : byte absolute $00+$E4; // 
-  UDFNUMH : byte absolute $00+$E4+1; // 
-  UDADDR : byte absolute $00+$E3; // 
-  UDIEN : byte absolute $00+$E2; // 
-  UDINT : byte absolute $00+$E1; // 
-  UDCON : byte absolute $00+$E0; // 
+  UEINT : byte absolute $00+$F4; //
+  UEBCLX : byte absolute $00+$F2; //
+  UEDATX : byte absolute $00+$F1; //
+  UEIENX : byte absolute $00+$F0; //
+  UESTA1X : byte absolute $00+$EF; //
+  UESTA0X : byte absolute $00+$EE; //
+  UECFG1X : byte absolute $00+$ED; //
+  UECFG0X : byte absolute $00+$EC; //
+  UECONX : byte absolute $00+$EB; //
+  UERST : byte absolute $00+$EA; //
+  UENUM : byte absolute $00+$E9; //
+  UEINTX : byte absolute $00+$E8; //
+  UDMFN : byte absolute $00+$E6; //
+  UDFNUM : word absolute $00+$E4; //
+  UDFNUML : byte absolute $00+$E4; //
+  UDFNUMH : byte absolute $00+$E4+1; //
+  UDADDR : byte absolute $00+$E3; //
+  UDIEN : byte absolute $00+$E2; //
+  UDINT : byte absolute $00+$E1; //
+  UDCON : byte absolute $00+$E0; //
   USBCON : byte absolute $00+$D8; // USB General Control Register
   REGCR : byte absolute $00+$63; // Regulator Control Register
   // PS2
-  UPOE : byte absolute $00+$FB; // 
+  UPOE : byte absolute $00+$FB; //
   PS2CON : byte absolute $00+$FA; // PS2 Pad Enable register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   EIND : byte absolute $00+$5C; // Extended Indirect Register
   GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2
@@ -97,9 +97,9 @@ var
   GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0
   PRR1 : byte absolute $00+$65; // Power Reduction Register1
   PRR0 : byte absolute $00+$64; // Power Reduction Register0
-  CLKSTA : byte absolute $00+$D2; // 
-  CLKSEL1 : byte absolute $00+$D1; // 
-  CLKSEL0 : byte absolute $00+$D0; // 
+  CLKSTA : byte absolute $00+$D2; //
+  CLKSEL1 : byte absolute $00+$D1; //
+  CLKSEL0 : byte absolute $00+$D0; //
   DWDR : byte absolute $00+$51; // debugWire communication register
   // EXTERNAL_INTERRUPT
   EICRA : byte absolute $00+$69; // External Interrupt Control Register A
@@ -124,7 +124,7 @@ var
   WDTCKD : byte absolute $00+$62; // Watchdog Timer Clock Divider
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // PORTC
   PORTC : byte absolute $00+$28; // Port C Data Register
   DDRC : byte absolute $00+$27; // Port C Data Direction Register
@@ -161,7 +161,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -208,80 +208,80 @@ const
   PLLE = 1; // PLL Enable Bit
   PLOCK = 0; // PLL Lock Status Bit
   // UEIENX
-  FLERRE = 7; // 
-  NAKINE = 6; // 
-  NAKOUTE = 4; // 
-  RXSTPE = 3; // 
-  RXOUTE = 2; // 
-  STALLEDE = 1; // 
-  TXINE = 0; // 
+  FLERRE = 7; //
+  NAKINE = 6; //
+  NAKOUTE = 4; //
+  RXSTPE = 3; //
+  RXOUTE = 2; //
+  STALLEDE = 1; //
+  TXINE = 0; //
   // UESTA1X
-  CTRLDIR = 2; // 
-  CURRBK = 0; // 
+  CTRLDIR = 2; //
+  CURRBK = 0; //
   // UESTA0X
-  CFGOK = 7; // 
-  OVERFI = 6; // 
-  UNDERFI = 5; // 
-  DTSEQ = 2; // 
-  NBUSYBK = 0; // 
+  CFGOK = 7; //
+  OVERFI = 6; //
+  UNDERFI = 5; //
+  DTSEQ = 2; //
+  NBUSYBK = 0; //
   // UECFG1X
-  EPSIZE = 4; // 
-  EPBK = 2; // 
-  ALLOC = 1; // 
+  EPSIZE = 4; //
+  EPBK = 2; //
+  ALLOC = 1; //
   // UECFG0X
-  EPTYPE = 6; // 
-  EPDIR = 0; // 
+  EPTYPE = 6; //
+  EPDIR = 0; //
   // UECONX
-  STALLRQ = 5; // 
-  STALLRQC = 4; // 
-  RSTDT = 3; // 
-  EPEN = 0; // 
+  STALLRQ = 5; //
+  STALLRQC = 4; //
+  RSTDT = 3; //
+  EPEN = 0; //
   // UERST
-  EPRST = 0; // 
+  EPRST = 0; //
   // UEINTX
-  FIFOCON = 7; // 
-  NAKINI = 6; // 
-  RWAL = 5; // 
-  NAKOUTI = 4; // 
-  RXSTPI = 3; // 
-  RXOUTI = 2; // 
-  STALLEDI = 1; // 
-  TXINI = 0; // 
+  FIFOCON = 7; //
+  NAKINI = 6; //
+  RWAL = 5; //
+  NAKOUTI = 4; //
+  RXSTPI = 3; //
+  RXOUTI = 2; //
+  STALLEDI = 1; //
+  TXINI = 0; //
   // UDMFN
-  FNCERR = 4; // 
+  FNCERR = 4; //
   // UDADDR
-  ADDEN = 7; // 
-  UADD = 0; // 
+  ADDEN = 7; //
+  UADD = 0; //
   // UDIEN
-  UPRSME = 6; // 
-  EORSME = 5; // 
-  WAKEUPE = 4; // 
-  EORSTE = 3; // 
-  SOFE = 2; // 
-  SUSPE = 0; // 
+  UPRSME = 6; //
+  EORSME = 5; //
+  WAKEUPE = 4; //
+  EORSTE = 3; //
+  SOFE = 2; //
+  SUSPE = 0; //
   // UDINT
-  UPRSMI = 6; // 
-  EORSMI = 5; // 
-  WAKEUPI = 4; // 
-  EORSTI = 3; // 
-  SOFI = 2; // 
-  SUSPI = 0; // 
+  UPRSMI = 6; //
+  EORSMI = 5; //
+  WAKEUPI = 4; //
+  EORSTI = 3; //
+  SOFI = 2; //
+  SUSPI = 0; //
   // UDCON
-  RSTCPU = 2; // 
-  RMWKUP = 1; // 
-  DETACH = 0; // 
+  RSTCPU = 2; //
+  RMWKUP = 1; //
+  DETACH = 0; //
   // USBCON
-  USBE = 7; // 
-  FRZCLK = 5; // 
+  USBE = 7; //
+  FRZCLK = 5; //
   // REGCR
-  REGDIS = 0; // 
+  REGDIS = 0; //
   // UPOE
-  UPWE = 6; // 
-  UPDRV = 4; // 
-  SCKI = 3; // 
-  DATAI = 2; // 
-  DPI = 1; // 
-  DMI = 0; // 
+  UPWE = 6; //
+  UPDRV = 4; //
+  SCKI = 3; //
+  DATAI = 2; //
+  DPI = 1; //
+  DMI = 0; //
   // PS2CON
   PS2EN = 0; // Enable
   // SREG
@@ -304,8 +304,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -329,17 +329,17 @@ const
   PRTIM1 = 3; // Power Reduction Timer/Counter1
   PRSPI = 2; // Power Reduction Serial Peripheral Interface
   // CLKSTA
-  RCON = 1; // 
-  EXTON = 0; // 
+  RCON = 1; //
+  EXTON = 0; //
   // CLKSEL1
-  RCCKSEL = 4; // 
-  EXCKSEL = 0; // 
+  RCCKSEL = 4; //
+  EXCKSEL = 0; //
   // CLKSEL0
-  RCSUT = 6; // 
-  EXSUT = 4; // 
-  RCE = 3; // 
-  EXTE = 2; // 
-  CLKS = 0; // 
+  RCSUT = 6; //
+  EXSUT = 4; //
+  RCE = 3; //
+  EXTE = 2; //
+  CLKS = 0; //
   // EICRA
   ISC3 = 6; // External Interrupt Sense Control Bit
   ISC2 = 4; // External Interrupt Sense Control Bit

rtl/embedded/avr/at90usb646.pp

@@ -31,15 +31,15 @@ var
   PINF : byte absolute $00+$2F; // Input Pins, Port F
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   EIND : byte absolute $00+$5C; // Extended Indirect Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
@@ -68,60 +68,60 @@ var
   UBRR1L : byte absolute $00+$CC; // USART Baud Rate Register  Bytes
   UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register  Bytes
   // USB_DEVICE
-  UEINT : byte absolute $00+$F4; // 
-  UEBCHX : byte absolute $00+$F3; // 
-  UEBCLX : byte absolute $00+$F2; // 
-  UEDATX : byte absolute $00+$F1; // 
-  UEIENX : byte absolute $00+$F0; // 
-  UESTA1X : byte absolute $00+$EF; // 
-  UESTA0X : byte absolute $00+$EE; // 
-  UECFG1X : byte absolute $00+$ED; // 
-  UECFG0X : byte absolute $00+$EC; // 
-  UECONX : byte absolute $00+$EB; // 
-  UERST : byte absolute $00+$EA; // 
-  UENUM : byte absolute $00+$E9; // 
-  UEINTX : byte absolute $00+$E8; // 
-  UDMFN : byte absolute $00+$E6; // 
-  UDFNUM : word absolute $00+$E4; // 
-  UDFNUML : byte absolute $00+$E4; // 
-  UDFNUMH : byte absolute $00+$E4+1; // 
-  UDADDR : byte absolute $00+$E3; // 
-  UDIEN : byte absolute $00+$E2; // 
-  UDINT : byte absolute $00+$E1; // 
-  UDCON : byte absolute $00+$E0; // 
+  UEINT : byte absolute $00+$F4; //
+  UEBCHX : byte absolute $00+$F3; //
+  UEBCLX : byte absolute $00+$F2; //
+  UEDATX : byte absolute $00+$F1; //
+  UEIENX : byte absolute $00+$F0; //
+  UESTA1X : byte absolute $00+$EF; //
+  UESTA0X : byte absolute $00+$EE; //
+  UECFG1X : byte absolute $00+$ED; //
+  UECFG0X : byte absolute $00+$EC; //
+  UECONX : byte absolute $00+$EB; //
+  UERST : byte absolute $00+$EA; //
+  UENUM : byte absolute $00+$E9; //
+  UEINTX : byte absolute $00+$E8; //
+  UDMFN : byte absolute $00+$E6; //
+  UDFNUM : word absolute $00+$E4; //
+  UDFNUML : byte absolute $00+$E4; //
+  UDFNUMH : byte absolute $00+$E4+1; //
+  UDADDR : byte absolute $00+$E3; //
+  UDIEN : byte absolute $00+$E2; //
+  UDINT : byte absolute $00+$E1; //
+  UDCON : byte absolute $00+$E0; //
   // USB_GLOBAL
-  OTGINT : byte absolute $00+$DF; // 
-  OTGIEN : byte absolute $00+$DE; // 
-  OTGCON : byte absolute $00+$DD; // 
-  OTGTCON : byte absolute $00+$F9; // 
-  USBINT : byte absolute $00+$DA; // 
-  USBSTA : byte absolute $00+$D9; // 
+  OTGINT : byte absolute $00+$DF; //
+  OTGIEN : byte absolute $00+$DE; //
+  OTGCON : byte absolute $00+$DD; //
+  OTGTCON : byte absolute $00+$F9; //
+  USBINT : byte absolute $00+$DA; //
+  USBSTA : byte absolute $00+$D9; //
   USBCON : byte absolute $00+$D8; // USB General Control Register
   UHWCON : byte absolute $00+$D7; // USB Hardware Configuration Register
   // USB_HOST
-  UPERRX : byte absolute $00+$F5; // 
-  UPINT : byte absolute $00+$F8; // 
-  UPBCHX : byte absolute $00+$F7; // 
-  UPBCLX : byte absolute $00+$F6; // 
-  UPDATX : byte absolute $00+$AF; // 
-  UPIENX : byte absolute $00+$AE; // 
-  UPCFG2X : byte absolute $00+$AD; // 
-  UPSTAX : byte absolute $00+$AC; // 
-  UPCFG1X : byte absolute $00+$AB; // 
-  UPCFG0X : byte absolute $00+$AA; // 
-  UPCONX : byte absolute $00+$A9; // 
-  UPRST : byte absolute $00+$A8; // 
-  UPNUM : byte absolute $00+$A7; // 
-  UPINTX : byte absolute $00+$A6; // 
-  UPINRQX : byte absolute $00+$A5; // 
-  UHFLEN : byte absolute $00+$A4; // 
-  UHFNUM : word absolute $00+$A2; // 
-  UHFNUML : byte absolute $00+$A2; // 
-  UHFNUMH : byte absolute $00+$A2+1; // 
-  UHADDR : byte absolute $00+$A1; // 
-  UHIEN : byte absolute $00+$A0; // 
-  UHINT : byte absolute $00+$9F; // 
-  UHCON : byte absolute $00+$9E; // 
+  UPERRX : byte absolute $00+$F5; //
+  UPINT : byte absolute $00+$F8; //
+  UPBCHX : byte absolute $00+$F7; //
+  UPBCLX : byte absolute $00+$F6; //
+  UPDATX : byte absolute $00+$AF; //
+  UPIENX : byte absolute $00+$AE; //
+  UPCFG2X : byte absolute $00+$AD; //
+  UPSTAX : byte absolute $00+$AC; //
+  UPCFG1X : byte absolute $00+$AB; //
+  UPCFG0X : byte absolute $00+$AA; //
+  UPCONX : byte absolute $00+$A9; //
+  UPRST : byte absolute $00+$A8; //
+  UPNUM : byte absolute $00+$A7; //
+  UPINTX : byte absolute $00+$A6; //
+  UPINRQX : byte absolute $00+$A5; //
+  UHFLEN : byte absolute $00+$A4; //
+  UHFNUM : word absolute $00+$A2; //
+  UHFNUML : byte absolute $00+$A2; //
+  UHFNUMH : byte absolute $00+$A2+1; //
+  UHADDR : byte absolute $00+$A1; //
+  UHIEN : byte absolute $00+$A0; //
+  UHINT : byte absolute $00+$9F; //
+  UHCON : byte absolute $00+$9E; //
   // BOOT_LOAD
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   // EEPROM
@@ -210,7 +210,7 @@ var
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // PLL
   PLLCSR : byte absolute $00+$49; // PLL Status and Control register
 
@@ -250,8 +250,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -279,7 +279,7 @@ const
   PRSPI = 2; // Power Reduction Serial Peripheral Interface
   PRADC = 0; // Power Reduction ADC
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -331,168 +331,168 @@ const
   UCSZ1 = 1; // Character Size
   UCPOL1 = 0; // Clock Polarity
   // UEIENX
-  FLERRE = 7; // 
-  NAKINE = 6; // 
-  NAKOUTE = 4; // 
-  RXSTPE = 3; // 
-  RXOUTE = 2; // 
-  STALLEDE = 1; // 
-  TXINE = 0; // 
+  FLERRE = 7; //
+  NAKINE = 6; //
+  NAKOUTE = 4; //
+  RXSTPE = 3; //
+  RXOUTE = 2; //
+  STALLEDE = 1; //
+  TXINE = 0; //
   // UESTA1X
-  CTRLDIR = 2; // 
-  CURRBK = 0; // 
+  CTRLDIR = 2; //
+  CURRBK = 0; //
   // UESTA0X
-  CFGOK = 7; // 
-  OVERFI = 6; // 
-  UNDERFI = 5; // 
-  DTSEQ = 2; // 
-  NBUSYBK = 0; // 
+  CFGOK = 7; //
+  OVERFI = 6; //
+  UNDERFI = 5; //
+  DTSEQ = 2; //
+  NBUSYBK = 0; //
   // UECFG1X
-  EPSIZE = 4; // 
-  EPBK = 2; // 
-  ALLOC = 1; // 
+  EPSIZE = 4; //
+  EPBK = 2; //
+  ALLOC = 1; //
   // UECFG0X
-  EPTYPE = 6; // 
-  EPDIR = 0; // 
+  EPTYPE = 6; //
+  EPDIR = 0; //
   // UECONX
-  STALLRQ = 5; // 
-  STALLRQC = 4; // 
-  RSTDT = 3; // 
-  EPEN = 0; // 
+  STALLRQ = 5; //
+  STALLRQC = 4; //
+  RSTDT = 3; //
+  EPEN = 0; //
   // UERST
-  EPRST = 0; // 
+  EPRST = 0; //
   // UEINTX
-  FIFOCON = 7; // 
-  NAKINI = 6; // 
-  RWAL = 5; // 
-  NAKOUTI = 4; // 
-  RXSTPI = 3; // 
-  RXOUTI = 2; // 
-  STALLEDI = 1; // 
-  TXINI = 0; // 
+  FIFOCON = 7; //
+  NAKINI = 6; //
+  RWAL = 5; //
+  NAKOUTI = 4; //
+  RXSTPI = 3; //
+  RXOUTI = 2; //
+  STALLEDI = 1; //
+  TXINI = 0; //
   // UDMFN
-  FNCERR = 4; // 
+  FNCERR = 4; //
   // UDADDR
-  ADDEN = 7; // 
-  UADD = 0; // 
+  ADDEN = 7; //
+  UADD = 0; //
   // UDIEN
-  UPRSME = 6; // 
-  EORSME = 5; // 
-  WAKEUPE = 4; // 
-  EORSTE = 3; // 
-  SOFE = 2; // 
-  SUSPE = 0; // 
+  UPRSME = 6; //
+  EORSME = 5; //
+  WAKEUPE = 4; //
+  EORSTE = 3; //
+  SOFE = 2; //
+  SUSPE = 0; //
   // UDINT
-  UPRSMI = 6; // 
-  EORSMI = 5; // 
-  WAKEUPI = 4; // 
-  EORSTI = 3; // 
-  SOFI = 2; // 
-  SUSPI = 0; // 
+  UPRSMI = 6; //
+  EORSMI = 5; //
+  WAKEUPI = 4; //
+  EORSTI = 3; //
+  SOFI = 2; //
+  SUSPI = 0; //
   // UDCON
-  LSM = 2; // 
-  RMWKUP = 1; // 
-  DETACH = 0; // 
+  LSM = 2; //
+  RMWKUP = 1; //
+  DETACH = 0; //
   // OTGINT
-  STOI = 5; // 
-  HNPERRI = 4; // 
-  ROLEEXI = 3; // 
-  BCERRI = 2; // 
-  VBERRI = 1; // 
-  SRPI = 0; // 
+  STOI = 5; //
+  HNPERRI = 4; //
+  ROLEEXI = 3; //
+  BCERRI = 2; //
+  VBERRI = 1; //
+  SRPI = 0; //
   // OTGIEN
-  STOE = 5; // 
-  HNPERRE = 4; // 
-  ROLEEXE = 3; // 
-  BCERRE = 2; // 
-  VBERRE = 1; // 
-  SRPE = 0; // 
+  STOE = 5; //
+  HNPERRE = 4; //
+  ROLEEXE = 3; //
+  BCERRE = 2; //
+  VBERRE = 1; //
+  SRPE = 0; //
   // OTGCON
-  HNPREQ = 5; // 
-  SRPREQ = 4; // 
-  SRPSEL = 3; // 
-  VBUSHWC = 2; // 
-  VBUSREQ = 1; // 
-  VBUSRQC = 0; // 
+  HNPREQ = 5; //
+  SRPREQ = 4; //
+  SRPSEL = 3; //
+  VBUSHWC = 2; //
+  VBUSREQ = 1; //
+  VBUSRQC = 0; //
   // OTGTCON
-  OTGTCON_7 = 7; // 
-  PAGE = 5; // 
-  VALUE_2 = 0; // 
+  OTGTCON_7 = 7; //
+  PAGE = 5; //
+  VALUE_2 = 0; //
   // USBINT
-  IDTI = 1; // 
-  VBUSTI = 0; // 
+  IDTI = 1; //
+  VBUSTI = 0; //
   // USBSTA
-  SPEED = 3; // 
-  ID = 1; // 
-  VBUS = 0; // 
+  SPEED = 3; //
+  ID = 1; //
+  VBUS = 0; //
   // USBCON
-  USBE = 7; // 
-  HOST = 6; // 
-  FRZCLK = 5; // 
-  OTGPADE = 4; // 
-  IDTE = 1; // 
-  VBUSTE = 0; // 
+  USBE = 7; //
+  HOST = 6; //
+  FRZCLK = 5; //
+  OTGPADE = 4; //
+  IDTE = 1; //
+  VBUSTE = 0; //
   // UHWCON
-  UIMOD = 7; // 
-  UIDE = 6; // 
-  UVCONE = 4; // 
-  UVREGE = 0; // 
+  UIMOD = 7; //
+  UIDE = 6; //
+  UVCONE = 4; //
+  UVREGE = 0; //
   // UPERRX
-  COUNTER = 5; // 
-  CRC16 = 4; // 
-  TIMEOUT = 3; // 
-  PID = 2; // 
-  DATAPID = 1; // 
-  DATATGL = 0; // 
+  COUNTER = 5; //
+  CRC16 = 4; //
+  TIMEOUT = 3; //
+  PID = 2; //
+  DATAPID = 1; //
+  DATATGL = 0; //
   // UPIENX
-  NAKEDE = 6; // 
-  PERRE = 4; // 
-  TXSTPE = 3; // 
-  TXOUTE = 2; // 
-  RXSTALLE = 1; // 
-  RXINE = 0; // 
+  NAKEDE = 6; //
+  PERRE = 4; //
+  TXSTPE = 3; //
+  TXOUTE = 2; //
+  RXSTALLE = 1; //
+  RXINE = 0; //
   // UPSTAX
-  NBUSYK = 0; // 
+  NBUSYK = 0; //
   // UPCFG1X
-  PSIZE = 4; // 
-  PBK = 2; // 
+  PSIZE = 4; //
+  PBK = 2; //
   // UPCFG0X
-  PTYPE = 6; // 
-  PTOKEN = 4; // 
-  PEPNUM = 0; // 
+  PTYPE = 6; //
+  PTOKEN = 4; //
+  PEPNUM = 0; //
   // UPCONX
-  PFREEZE = 6; // 
-  INMODE = 5; // 
-  PEN = 0; // 
+  PFREEZE = 6; //
+  INMODE = 5; //
+  PEN = 0; //
   // UPRST
-  PRST = 0; // 
+  PRST = 0; //
   // UPINTX
-  NAKEDI = 6; // 
-  PERRI = 4; // 
-  TXSTPI = 3; // 
-  TXOUTI = 2; // 
-  RXSTALLI = 1; // 
-  RXINI = 0; // 
+  NAKEDI = 6; //
+  PERRI = 4; //
+  TXSTPI = 3; //
+  TXOUTI = 2; //
+  RXSTALLI = 1; //
+  RXINI = 0; //
   // UHIEN
-  HWUPE = 6; // 
-  HSOFE = 5; // 
-  RXRSME = 4; // 
-  RSMEDE = 3; // 
-  RSTE = 2; // 
-  DDISCE = 1; // 
-  DCONNE = 0; // 
+  HWUPE = 6; //
+  HSOFE = 5; //
+  RXRSME = 4; //
+  RSMEDE = 3; //
+  RSTE = 2; //
+  DDISCE = 1; //
+  DCONNE = 0; //
   // UHINT
-  UHUPI = 6; // 
-  HSOFI = 5; // 
-  RXRSMI = 4; // 
-  RSMEDI = 3; // 
-  RSTI = 2; // 
-  DDISCI = 1; // 
-  DCONNI = 0; // 
+  UHUPI = 6; //
+  HSOFI = 5; //
+  RXRSMI = 4; //
+  RSMEDI = 3; //
+  RSTI = 2; //
+  DDISCI = 1; //
+  DCONNI = 0; //
   // UHCON
-  RESUME = 2; // 
-  RESET = 1; // 
-  SOFEN = 0; // 
+  RESUME = 2; //
+  RESET = 1; //
+  SOFEN = 0; //
   // SPMCSR
   SPMIE = 7; // SPM Interrupt Enable
   RWWSB = 6; // Read While Write Section Busy
@@ -511,7 +511,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -705,7 +705,7 @@ procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Ti
 procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
 procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
 procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
-procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface        
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 37 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/at90usb647.pp

@@ -31,15 +31,15 @@ var
   PINF : byte absolute $00+$2F; // Input Pins, Port F
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   EIND : byte absolute $00+$5C; // Extended Indirect Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
@@ -68,60 +68,60 @@ var
   UBRR1L : byte absolute $00+$CC; // USART Baud Rate Register  Bytes
   UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register  Bytes
   // USB_DEVICE
-  UEINT : byte absolute $00+$F4; // 
-  UEBCHX : byte absolute $00+$F3; // 
-  UEBCLX : byte absolute $00+$F2; // 
-  UEDATX : byte absolute $00+$F1; // 
-  UEIENX : byte absolute $00+$F0; // 
-  UESTA1X : byte absolute $00+$EF; // 
-  UESTA0X : byte absolute $00+$EE; // 
-  UECFG1X : byte absolute $00+$ED; // 
-  UECFG0X : byte absolute $00+$EC; // 
-  UECONX : byte absolute $00+$EB; // 
-  UERST : byte absolute $00+$EA; // 
-  UENUM : byte absolute $00+$E9; // 
-  UEINTX : byte absolute $00+$E8; // 
-  UDMFN : byte absolute $00+$E6; // 
-  UDFNUM : word absolute $00+$E4; // 
-  UDFNUML : byte absolute $00+$E4; // 
-  UDFNUMH : byte absolute $00+$E4+1; // 
-  UDADDR : byte absolute $00+$E3; // 
-  UDIEN : byte absolute $00+$E2; // 
-  UDINT : byte absolute $00+$E1; // 
-  UDCON : byte absolute $00+$E0; // 
+  UEINT : byte absolute $00+$F4; //
+  UEBCHX : byte absolute $00+$F3; //
+  UEBCLX : byte absolute $00+$F2; //
+  UEDATX : byte absolute $00+$F1; //
+  UEIENX : byte absolute $00+$F0; //
+  UESTA1X : byte absolute $00+$EF; //
+  UESTA0X : byte absolute $00+$EE; //
+  UECFG1X : byte absolute $00+$ED; //
+  UECFG0X : byte absolute $00+$EC; //
+  UECONX : byte absolute $00+$EB; //
+  UERST : byte absolute $00+$EA; //
+  UENUM : byte absolute $00+$E9; //
+  UEINTX : byte absolute $00+$E8; //
+  UDMFN : byte absolute $00+$E6; //
+  UDFNUM : word absolute $00+$E4; //
+  UDFNUML : byte absolute $00+$E4; //
+  UDFNUMH : byte absolute $00+$E4+1; //
+  UDADDR : byte absolute $00+$E3; //
+  UDIEN : byte absolute $00+$E2; //
+  UDINT : byte absolute $00+$E1; //
+  UDCON : byte absolute $00+$E0; //
   // USB_GLOBAL
-  OTGINT : byte absolute $00+$DF; // 
-  OTGIEN : byte absolute $00+$DE; // 
-  OTGCON : byte absolute $00+$DD; // 
-  OTGTCON : byte absolute $00+$F9; // 
-  USBINT : byte absolute $00+$DA; // 
-  USBSTA : byte absolute $00+$D9; // 
+  OTGINT : byte absolute $00+$DF; //
+  OTGIEN : byte absolute $00+$DE; //
+  OTGCON : byte absolute $00+$DD; //
+  OTGTCON : byte absolute $00+$F9; //
+  USBINT : byte absolute $00+$DA; //
+  USBSTA : byte absolute $00+$D9; //
   USBCON : byte absolute $00+$D8; // USB General Control Register
   UHWCON : byte absolute $00+$D7; // USB Hardware Configuration Register
   // USB_HOST
-  UPERRX : byte absolute $00+$F5; // 
-  UPINT : byte absolute $00+$F8; // 
-  UPBCHX : byte absolute $00+$F7; // 
-  UPBCLX : byte absolute $00+$F6; // 
-  UPDATX : byte absolute $00+$AF; // 
-  UPIENX : byte absolute $00+$AE; // 
-  UPCFG2X : byte absolute $00+$AD; // 
-  UPSTAX : byte absolute $00+$AC; // 
-  UPCFG1X : byte absolute $00+$AB; // 
-  UPCFG0X : byte absolute $00+$AA; // 
-  UPCONX : byte absolute $00+$A9; // 
-  UPRST : byte absolute $00+$A8; // 
-  UPNUM : byte absolute $00+$A7; // 
-  UPINTX : byte absolute $00+$A6; // 
-  UPINRQX : byte absolute $00+$A5; // 
-  UHFLEN : byte absolute $00+$A4; // 
-  UHFNUM : word absolute $00+$A2; // 
-  UHFNUML : byte absolute $00+$A2; // 
-  UHFNUMH : byte absolute $00+$A2+1; // 
-  UHADDR : byte absolute $00+$A1; // 
-  UHIEN : byte absolute $00+$A0; // 
-  UHINT : byte absolute $00+$9F; // 
-  UHCON : byte absolute $00+$9E; // 
+  UPERRX : byte absolute $00+$F5; //
+  UPINT : byte absolute $00+$F8; //
+  UPBCHX : byte absolute $00+$F7; //
+  UPBCLX : byte absolute $00+$F6; //
+  UPDATX : byte absolute $00+$AF; //
+  UPIENX : byte absolute $00+$AE; //
+  UPCFG2X : byte absolute $00+$AD; //
+  UPSTAX : byte absolute $00+$AC; //
+  UPCFG1X : byte absolute $00+$AB; //
+  UPCFG0X : byte absolute $00+$AA; //
+  UPCONX : byte absolute $00+$A9; //
+  UPRST : byte absolute $00+$A8; //
+  UPNUM : byte absolute $00+$A7; //
+  UPINTX : byte absolute $00+$A6; //
+  UPINRQX : byte absolute $00+$A5; //
+  UHFLEN : byte absolute $00+$A4; //
+  UHFNUM : word absolute $00+$A2; //
+  UHFNUML : byte absolute $00+$A2; //
+  UHFNUMH : byte absolute $00+$A2+1; //
+  UHADDR : byte absolute $00+$A1; //
+  UHIEN : byte absolute $00+$A0; //
+  UHINT : byte absolute $00+$9F; //
+  UHCON : byte absolute $00+$9E; //
   // BOOT_LOAD
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   // EEPROM
@@ -210,7 +210,7 @@ var
   DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1
   // ANALOG_COMPARATOR
   ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
-  DIDR1 : byte absolute $00+$7F; // 
+  DIDR1 : byte absolute $00+$7F; //
   // PLL
   PLLCSR : byte absolute $00+$49; // PLL Status and Control register
 
@@ -250,8 +250,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -279,7 +279,7 @@ const
   PRSPI = 2; // Power Reduction Serial Peripheral Interface
   PRADC = 0; // Power Reduction ADC
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -331,168 +331,168 @@ const
   UCSZ1 = 1; // Character Size
   UCPOL1 = 0; // Clock Polarity
   // UEIENX
-  FLERRE = 7; // 
-  NAKINE = 6; // 
-  NAKOUTE = 4; // 
-  RXSTPE = 3; // 
-  RXOUTE = 2; // 
-  STALLEDE = 1; // 
-  TXINE = 0; // 
+  FLERRE = 7; //
+  NAKINE = 6; //
+  NAKOUTE = 4; //
+  RXSTPE = 3; //
+  RXOUTE = 2; //
+  STALLEDE = 1; //
+  TXINE = 0; //
   // UESTA1X
-  CTRLDIR = 2; // 
-  CURRBK = 0; // 
+  CTRLDIR = 2; //
+  CURRBK = 0; //
   // UESTA0X
-  CFGOK = 7; // 
-  OVERFI = 6; // 
-  UNDERFI = 5; // 
-  DTSEQ = 2; // 
-  NBUSYBK = 0; // 
+  CFGOK = 7; //
+  OVERFI = 6; //
+  UNDERFI = 5; //
+  DTSEQ = 2; //
+  NBUSYBK = 0; //
   // UECFG1X
-  EPSIZE = 4; // 
-  EPBK = 2; // 
-  ALLOC = 1; // 
+  EPSIZE = 4; //
+  EPBK = 2; //
+  ALLOC = 1; //
   // UECFG0X
-  EPTYPE = 6; // 
-  EPDIR = 0; // 
+  EPTYPE = 6; //
+  EPDIR = 0; //
   // UECONX
-  STALLRQ = 5; // 
-  STALLRQC = 4; // 
-  RSTDT = 3; // 
-  EPEN = 0; // 
+  STALLRQ = 5; //
+  STALLRQC = 4; //
+  RSTDT = 3; //
+  EPEN = 0; //
   // UERST
-  EPRST = 0; // 
+  EPRST = 0; //
   // UEINTX
-  FIFOCON = 7; // 
-  NAKINI = 6; // 
-  RWAL = 5; // 
-  NAKOUTI = 4; // 
-  RXSTPI = 3; // 
-  RXOUTI = 2; // 
-  STALLEDI = 1; // 
-  TXINI = 0; // 
+  FIFOCON = 7; //
+  NAKINI = 6; //
+  RWAL = 5; //
+  NAKOUTI = 4; //
+  RXSTPI = 3; //
+  RXOUTI = 2; //
+  STALLEDI = 1; //
+  TXINI = 0; //
   // UDMFN
-  FNCERR = 4; // 
+  FNCERR = 4; //
   // UDADDR
-  ADDEN = 7; // 
-  UADD = 0; // 
+  ADDEN = 7; //
+  UADD = 0; //
   // UDIEN
-  UPRSME = 6; // 
-  EORSME = 5; // 
-  WAKEUPE = 4; // 
-  EORSTE = 3; // 
-  SOFE = 2; // 
-  SUSPE = 0; // 
+  UPRSME = 6; //
+  EORSME = 5; //
+  WAKEUPE = 4; //
+  EORSTE = 3; //
+  SOFE = 2; //
+  SUSPE = 0; //
   // UDINT
-  UPRSMI = 6; // 
-  EORSMI = 5; // 
-  WAKEUPI = 4; // 
-  EORSTI = 3; // 
-  SOFI = 2; // 
-  SUSPI = 0; // 
+  UPRSMI = 6; //
+  EORSMI = 5; //
+  WAKEUPI = 4; //
+  EORSTI = 3; //
+  SOFI = 2; //
+  SUSPI = 0; //
   // UDCON
-  LSM = 2; // 
-  RMWKUP = 1; // 
-  DETACH = 0; // 
+  LSM = 2; //
+  RMWKUP = 1; //
+  DETACH = 0; //
   // OTGINT
-  STOI = 5; // 
-  HNPERRI = 4; // 
-  ROLEEXI = 3; // 
-  BCERRI = 2; // 
-  VBERRI = 1; // 
-  SRPI = 0; // 
+  STOI = 5; //
+  HNPERRI = 4; //
+  ROLEEXI = 3; //
+  BCERRI = 2; //
+  VBERRI = 1; //
+  SRPI = 0; //
   // OTGIEN
-  STOE = 5; // 
-  HNPERRE = 4; // 
-  ROLEEXE = 3; // 
-  BCERRE = 2; // 
-  VBERRE = 1; // 
-  SRPE = 0; // 
+  STOE = 5; //
+  HNPERRE = 4; //
+  ROLEEXE = 3; //
+  BCERRE = 2; //
+  VBERRE = 1; //
+  SRPE = 0; //
   // OTGCON
-  HNPREQ = 5; // 
-  SRPREQ = 4; // 
-  SRPSEL = 3; // 
-  VBUSHWC = 2; // 
-  VBUSREQ = 1; // 
-  VBUSRQC = 0; // 
+  HNPREQ = 5; //
+  SRPREQ = 4; //
+  SRPSEL = 3; //
+  VBUSHWC = 2; //
+  VBUSREQ = 1; //
+  VBUSRQC = 0; //
   // OTGTCON
-  OTGTCON_7 = 7; // 
-  PAGE = 5; // 
-  VALUE_2 = 0; // 
+  OTGTCON_7 = 7; //
+  PAGE = 5; //
+  VALUE_2 = 0; //
   // USBINT
-  IDTI = 1; // 
-  VBUSTI = 0; // 
+  IDTI = 1; //
+  VBUSTI = 0; //
   // USBSTA
-  SPEED = 3; // 
-  ID = 1; // 
-  VBUS = 0; // 
+  SPEED = 3; //
+  ID = 1; //
+  VBUS = 0; //
   // USBCON
-  USBE = 7; // 
-  HOST = 6; // 
-  FRZCLK = 5; // 
-  OTGPADE = 4; // 
-  IDTE = 1; // 
-  VBUSTE = 0; // 
+  USBE = 7; //
+  HOST = 6; //
+  FRZCLK = 5; //
+  OTGPADE = 4; //
+  IDTE = 1; //
+  VBUSTE = 0; //
   // UHWCON
-  UIMOD = 7; // 
-  UIDE = 6; // 
-  UVCONE = 4; // 
-  UVREGE = 0; // 
+  UIMOD = 7; //
+  UIDE = 6; //
+  UVCONE = 4; //
+  UVREGE = 0; //
   // UPERRX
-  COUNTER = 5; // 
-  CRC16 = 4; // 
-  TIMEOUT = 3; // 
-  PID = 2; // 
-  DATAPID = 1; // 
-  DATATGL = 0; // 
+  COUNTER = 5; //
+  CRC16 = 4; //
+  TIMEOUT = 3; //
+  PID = 2; //
+  DATAPID = 1; //
+  DATATGL = 0; //
   // UPIENX
-  NAKEDE = 6; // 
-  PERRE = 4; // 
-  TXSTPE = 3; // 
-  TXOUTE = 2; // 
-  RXSTALLE = 1; // 
-  RXINE = 0; // 
+  NAKEDE = 6; //
+  PERRE = 4; //
+  TXSTPE = 3; //
+  TXOUTE = 2; //
+  RXSTALLE = 1; //
+  RXINE = 0; //
   // UPSTAX
-  NBUSYK = 0; // 
+  NBUSYK = 0; //
   // UPCFG1X
-  PSIZE = 4; // 
-  PBK = 2; // 
+  PSIZE = 4; //
+  PBK = 2; //
   // UPCFG0X
-  PTYPE = 6; // 
-  PTOKEN = 4; // 
-  PEPNUM = 0; // 
+  PTYPE = 6; //
+  PTOKEN = 4; //
+  PEPNUM = 0; //
   // UPCONX
-  PFREEZE = 6; // 
-  INMODE = 5; // 
-  PEN = 0; // 
+  PFREEZE = 6; //
+  INMODE = 5; //
+  PEN = 0; //
   // UPRST
-  PRST = 0; // 
+  PRST = 0; //
   // UPINTX
-  NAKEDI = 6; // 
-  PERRI = 4; // 
-  TXSTPI = 3; // 
-  TXOUTI = 2; // 
-  RXSTALLI = 1; // 
-  RXINI = 0; // 
+  NAKEDI = 6; //
+  PERRI = 4; //
+  TXSTPI = 3; //
+  TXOUTI = 2; //
+  RXSTALLI = 1; //
+  RXINI = 0; //
   // UHIEN
-  HWUPE = 6; // 
-  HSOFE = 5; // 
-  RXRSME = 4; // 
-  RSMEDE = 3; // 
-  RSTE = 2; // 
-  DDISCE = 1; // 
-  DCONNE = 0; // 
+  HWUPE = 6; //
+  HSOFE = 5; //
+  RXRSME = 4; //
+  RSMEDE = 3; //
+  RSTE = 2; //
+  DDISCE = 1; //
+  DCONNE = 0; //
   // UHINT
-  UHUPI = 6; // 
-  HSOFI = 5; // 
-  RXRSMI = 4; // 
-  RSMEDI = 3; // 
-  RSTI = 2; // 
-  DDISCI = 1; // 
-  DCONNI = 0; // 
+  UHUPI = 6; //
+  HSOFI = 5; //
+  RXRSMI = 4; //
+  RSMEDI = 3; //
+  RSTI = 2; //
+  DDISCI = 1; //
+  DCONNI = 0; //
   // UHCON
-  RESUME = 2; // 
-  RESET = 1; // 
-  SOFEN = 0; // 
+  RESUME = 2; //
+  RESET = 1; //
+  SOFEN = 0; //
   // SPMCSR
   SPMIE = 7; // SPM Interrupt Enable
   RWWSB = 6; // Read While Write Section Busy
@@ -511,7 +511,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -705,7 +705,7 @@ procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Ti
 procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
 procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
 procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
-procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface        
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface
 procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 37 Store Program Memory Read
 
 procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';

rtl/embedded/avr/ata6285.pp

@@ -24,9 +24,9 @@ var
   SRCCAL : byte absolute $00+$65; // SRC-Oscillator Calibration Register
   VMCSR : byte absolute $00+$36; // Voltage Monitor Control and Status Register
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
@@ -40,9 +40,9 @@ var
   LFRB : byte absolute $00+$56; // Low Frequency Receive data Buffer
   LFRR : byte absolute $00+$50; // LF RSSI Data Register
   LFHCR : byte absolute $00+$83; // LF Header Compare Register
-  LFIDC : word absolute $00+$84; // LF ID Compare Register 
-  LFIDCL : byte absolute $00+$84; // LF ID Compare Register 
-  LFIDCH : byte absolute $00+$84+1; // LF ID Compare Register 
+  LFIDC : word absolute $00+$84; // LF ID Compare Register
+  LFIDCL : byte absolute $00+$84; // LF ID Compare Register
+  LFIDCH : byte absolute $00+$84+1; // LF ID Compare Register
   LFIMR : byte absolute $00+$81; // Low Frequency Interrupt Mask Register
   LFFR : byte absolute $00+$38; // Low Frequency Flag Register
   LFCAL : word absolute $00+$86; // LF Calibration Register  Bytes
@@ -179,7 +179,7 @@ const
   PGERS = 1; // Page Erase
   SELFPRGEN = 0; // Self Programming Enable
   // MCUCR
-  PUD = 4; // 
+  PUD = 4; //
   IVSEL = 1; // Interrupt Vector Select
   IVCE = 0; // Interrupt Vector Change Enable
   // MCUSR
@@ -189,8 +189,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // SMCR
-  SM = 1; // 
-  SE = 0; // 
+  SM = 1; //
+  SE = 0; //
   // LFRCR
   LFCS = 5; // LF receiver Capacitor Select Bits
   LFRSS = 4; // LF Receiver Sensitivity Select Bit

rtl/embedded/avr/ata6286.pp

@@ -24,9 +24,9 @@ var
   SRCCAL : byte absolute $00+$65; // SRC-Oscillator Calibration Register
   VMCSR : byte absolute $00+$36; // Voltage Monitor Control and Status Register
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUSR : byte absolute $00+$54; // MCU Status Register
@@ -40,9 +40,9 @@ var
   LFRB : byte absolute $00+$56; // Low Frequency Receive data Buffer
   LFRR : byte absolute $00+$50; // LF RSSI Data Register
   LFHCR : byte absolute $00+$83; // LF Header Compare Register
-  LFIDC : word absolute $00+$84; // LF ID Compare Register 
-  LFIDCL : byte absolute $00+$84; // LF ID Compare Register 
-  LFIDCH : byte absolute $00+$84+1; // LF ID Compare Register 
+  LFIDC : word absolute $00+$84; // LF ID Compare Register
+  LFIDCL : byte absolute $00+$84; // LF ID Compare Register
+  LFIDCH : byte absolute $00+$84+1; // LF ID Compare Register
   LFIMR : byte absolute $00+$81; // Low Frequency Interrupt Mask Register
   LFFR : byte absolute $00+$38; // Low Frequency Flag Register
   LFCAL : word absolute $00+$86; // LF Calibration Register  Bytes
@@ -179,7 +179,7 @@ const
   PGERS = 1; // Page Erase
   SELFPRGEN = 0; // Self Programming Enable
   // MCUCR
-  PUD = 4; // 
+  PUD = 4; //
   IVSEL = 1; // Interrupt Vector Select
   IVCE = 0; // Interrupt Vector Change Enable
   // MCUSR
@@ -189,8 +189,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // SMCR
-  SM = 1; // 
-  SE = 0; // 
+  SM = 1; //
+  SE = 0; //
   // LFRCR
   LFCS = 5; // LF receiver Capacitor Select Bits
   LFRSS = 4; // LF Receiver Sensitivity Select Bit

rtl/embedded/avr/atmega128.pp

@@ -32,9 +32,9 @@ var
   UBRR1L : byte absolute $00+$99; // USART Baud Rate Register Low Byte
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   MCUCR : byte absolute $00+$55; // MCU Control Register
   MCUCSR : byte absolute $00+$54; // MCU Control And Status Register
   XMCRA : byte absolute $00+$6D; // External Memory Control Register A
@@ -354,8 +354,8 @@ const
   OCF2 = 7; // Output Compare Flag 2
   TOV2 = 6; // Timer/Counter2 Overflow Flag
   // TIMSK
-  OCIE2 = 7; // 
-  TOIE2 = 6; // 
+  OCIE2 = 7; //
+  TOIE2 = 6; //
   // ETIMSK
   TICIE3 = 5; // Timer/Counter3 Input Capture Interrupt Enable
   OCIE3A = 4; // Timer/Counter3 Output CompareA Match Interrupt Enable

rtl/embedded/avr/atmega1280.pp

@@ -204,13 +204,13 @@ var
   PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   EIND : byte absolute $00+$5C; // Extended Indirect Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
@@ -285,7 +285,7 @@ const
   UCSZ0 = 1; // Character Size
   UCPOL0 = 0; // Clock Polarity
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -315,7 +315,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -544,8 +544,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable
@@ -589,23 +589,23 @@ const
   MUX5 = 3; // Analog Channel and Gain Selection Bits
   ADTS = 0; // ADC Auto Trigger Source bits
   // DIDR2
-  ADC15D = 7; // 
-  ADC14D = 6; // 
-  ADC13D = 5; // 
-  ADC12D = 4; // 
-  ADC11D = 3; // 
-  ADC10D = 2; // 
-  ADC9D = 1; // 
-  ADC8D = 0; // 
+  ADC15D = 7; //
+  ADC14D = 6; //
+  ADC13D = 5; //
+  ADC12D = 4; //
+  ADC11D = 3; //
+  ADC10D = 2; //
+  ADC9D = 1; //
+  ADC8D = 0; //
   // DIDR0
-  ADC7D = 7; // 
-  ADC6D = 6; // 
-  ADC5D = 5; // 
-  ADC4D = 4; // 
-  ADC3D = 3; // 
-  ADC2D = 2; // 
-  ADC1D = 1; // 
-  ADC0D = 0; // 
+  ADC7D = 7; //
+  ADC6D = 6; //
+  ADC5D = 5; //
+  ADC4D = 4; //
+  ADC3D = 3; //
+  ADC2D = 2; //
+  ADC1D = 1; //
+  ADC0D = 0; //
   // SPMCSR
   SPMIE = 7; // SPM Interrupt Enable
   RWWSB = 6; // Read While Write Section Busy

rtl/embedded/avr/atmega1281.pp

@@ -198,13 +198,13 @@ var
   SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   XMCRA : byte absolute $00+$74; // External Memory Control Register A
   XMCRB : byte absolute $00+$75; // External Memory Control Register B
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
   GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2
@@ -276,7 +276,7 @@ const
   UCSZ1 = 1; // Character Size
   UCPOL1 = 0; // Clock Polarity
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -306,7 +306,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -499,23 +499,23 @@ const
   MUX5 = 3; // Analog Channel and Gain Selection Bits
   ADTS = 0; // ADC Auto Trigger Source bits
   // DIDR2
-  ADC15D = 7; // 
-  ADC14D = 6; // 
-  ADC13D = 5; // 
-  ADC12D = 4; // 
-  ADC11D = 3; // 
-  ADC10D = 2; // 
-  ADC9D = 1; // 
-  ADC8D = 0; // 
+  ADC15D = 7; //
+  ADC14D = 6; //
+  ADC13D = 5; //
+  ADC12D = 4; //
+  ADC11D = 3; //
+  ADC10D = 2; //
+  ADC9D = 1; //
+  ADC8D = 0; //
   // DIDR0
-  ADC7D = 7; // 
-  ADC6D = 6; // 
-  ADC5D = 5; // 
-  ADC4D = 4; // 
-  ADC3D = 3; // 
-  ADC2D = 2; // 
-  ADC1D = 1; // 
-  ADC0D = 0; // 
+  ADC7D = 7; //
+  ADC6D = 6; //
+  ADC5D = 5; //
+  ADC4D = 4; //
+  ADC3D = 3; //
+  ADC2D = 2; //
+  ADC1D = 1; //
+  ADC0D = 0; //
   // SPMCSR
   SPMIE = 7; // SPM Interrupt Enable
   RWWSB = 6; // Read While Write Section Busy
@@ -552,8 +552,8 @@ const
   XMBK = 7; // External Memory Bus Keeper Enable
   XMM = 0; // External Memory High Mask
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable

rtl/embedded/avr/atmega1284.pp

@@ -137,11 +137,11 @@ var
   WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
   GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2
@@ -191,7 +191,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -317,14 +317,14 @@ const
   // ADCSRB
   ADTS = 0; // ADC Auto Trigger Source bits
   // DIDR0
-  ADC7D = 7; // 
-  ADC6D = 6; // 
-  ADC5D = 5; // 
-  ADC4D = 4; // 
-  ADC3D = 3; // 
-  ADC2D = 2; // 
-  ADC1D = 1; // 
-  ADC0D = 0; // 
+  ADC7D = 7; //
+  ADC6D = 6; //
+  ADC5D = 5; //
+  ADC4D = 4; //
+  ADC3D = 3; //
+  ADC2D = 2; //
+  ADC1D = 1; //
+  ADC0D = 0; //
   // MCUCR
   JTD = 7; // JTAG Interface Disable
   // MCUSR
@@ -336,7 +336,7 @@ const
   EEPE = 1; // EEPROM Write Enable
   EERE = 0; // EEPROM Read Enable
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -412,8 +412,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable

rtl/embedded/avr/atmega1284p.pp

@@ -137,11 +137,11 @@ var
   WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register
   // CPU
   SREG : byte absolute $00+$5F; // Status Register
-  SP : word absolute $00+$5D; // Stack Pointer 
-  SPL : byte absolute $00+$5D; // Stack Pointer 
-  SPH : byte absolute $00+$5D+1; // Stack Pointer 
+  SP : word absolute $00+$5D; // Stack Pointer
+  SPL : byte absolute $00+$5D; // Stack Pointer
+  SPH : byte absolute $00+$5D+1; // Stack Pointer
   OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
-  CLKPR : byte absolute $00+$61; // 
+  CLKPR : byte absolute $00+$61; //
   SMCR : byte absolute $00+$53; // Sleep Mode Control Register
   RAMPZ : byte absolute $00+$5B; // RAM Page Z Select Register
   GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2
@@ -191,7 +191,7 @@ const
   // TCCR0B
   FOC0A = 7; // Force Output Compare A
   FOC0B = 6; // Force Output Compare B
-  WGM02 = 3; // 
+  WGM02 = 3; //
   CS0 = 0; // Clock Select
   // TCCR0A
   COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
@@ -317,14 +317,14 @@ const
   // ADCSRB
   ADTS = 0; // ADC Auto Trigger Source bits
   // DIDR0
-  ADC7D = 7; // 
-  ADC6D = 6; // 
-  ADC5D = 5; // 
-  ADC4D = 4; // 
-  ADC3D = 3; // 
-  ADC2D = 2; // 
-  ADC1D = 1; // 
-  ADC0D = 0; // 
+  ADC7D = 7; //
+  ADC6D = 6; //
+  ADC5D = 5; //
+  ADC4D = 4; //
+  ADC3D = 3; //
+  ADC2D = 2; //
+  ADC1D = 1; //
+  ADC0D = 0; //
   // MCUCR
   JTD = 7; // JTAG Interface Disable
   // MCUSR
@@ -336,7 +336,7 @@ const
   EEPE = 1; // EEPROM Write Enable
   EERE = 0; // EEPROM Read Enable
   // TWAMR
-  TWAM = 1; // 
+  TWAM = 1; //
   // TWCR
   TWINT = 7; // TWI Interrupt Flag
   TWEA = 6; // TWI Enable Acknowledge Bit
@@ -414,8 +414,8 @@ const
   EXTRF = 1; // External Reset Flag
   PORF = 0; // Power-on reset flag
   // CLKPR
-  CLKPCE = 7; // 
-  CLKPS = 0; // 
+  CLKPCE = 7; //
+  CLKPS = 0; //
   // SMCR
   SM = 1; // Sleep Mode Select bits
   SE = 0; // Sleep Enable