* a64: Corrected supported shifter/extender mnemonics for arithmetic/logical instructions

compiler/aarch64/aasmcpu.pas

@@ -967,9 +967,6 @@ implementation
         case opc of
           A_ADD,
           A_SUB,
-          A_NEG,
-          A_AND,
-          A_TST,
           A_CMN,
           A_CMP:
             begin
@@ -977,23 +974,24 @@ implementation
               if not useszr then
                 result:=
                   (sm in shiftedregmodes) and
-                  ((shiftimm in [0..31]) or
-                   (is64bit and
-                    (shiftimm in [32..63])));
+                  (shiftimm in [0..31*(ord(is64bit)+1)+ord(is64bit)]);
               if not usessp then
                 result:=
                   result or
                   ((sm in extendedregmodes) and
-                   (shiftimm in [0..4]));
+                   (shiftimm in [0..31*(ord(is64bit)+1)+ord(is64bit)]));
             end;
+          A_AND,
           A_BIC,
           A_EON,
           A_EOR,
           A_MVN,
+          A_NEG,
           A_ORN,
-          A_ORR:
+          A_ORR,
+          A_TST:
             result:=
-              (sm in shiftedregmodes) and
+              (sm in logicalshiftedregmodes) and
               (shiftimm in [0..31*(ord(is64bit)+1)+ord(is64bit)]);
           A_MOVK,
           A_MOVZ,

compiler/aarch64/cpubase.pas

@@ -241,6 +241,7 @@ unit cpubase;
 
       shiftedregmodes = [SM_LSL,SM_UXTB,SM_UXTH,SM_UXTW,SM_UXTX,SM_SXTB,SM_SXTH,SM_SXTW,SM_SXTX];
       extendedregmodes = [SM_LSL,SM_LSR,SM_ASR];
+      logicalshiftedregmodes = [SM_LSL,SM_LSR,SM_ASR,SM_ROR];
 
 
 {*****************************************************************************