+ RiscV64: make use of rev8 instruction

rtl/riscv64/riscv64.inc

@@ -251,3 +251,48 @@ procedure inclocked(var l:int64);
   begin
     InterLockedIncrement64(l);
   end;
+
+{$ifdef CPURV_HAS_ZBB}
+
+{$define FPC_SYSTEM_HAS_SWAPENDIAN}
+
+function SwapEndian(const AValue: SmallInt): SmallInt; assembler; nostackframe;
+asm
+  rev8 a0, a0
+  srli a0, a0, 48
+end;
+
+
+function SwapEndian(const AValue: Word): Word; assembler; nostackframe;
+asm
+  rev8 a0, a0
+  srli a0, a0, 48
+end;
+
+
+function SwapEndian(const AValue: LongInt): LongInt; assembler; nostackframe;
+asm
+  rev8 a0, a0
+  srli a0, a0, 32
+end;
+
+
+function SwapEndian(const AValue: DWord): DWord; assembler; nostackframe;
+asm
+  rev8 a0, a0
+  srli a0, a0, 32
+end;
+
+
+function SwapEndian(const AValue: Int64): Int64; assembler; nostackframe;
+asm
+  rev8 a0, a0
+end;
+
+
+function SwapEndian(const AValue: QWord): QWord; assembler; nostackframe;
+asm
+  rev8 a0, a0
+end;
+
+{$endif CPURV_HAS_ZBB}