+ Added mips32r2 opcodes needed for pic32.

* Output registers of type R_SPECIALREGISTER as numbers.
+ For MTC0/MFC0 instructions, set type of first operand to R_SPECIALREGISTER, since it designates a coprocessor register.

git-svn-id: trunk@24799 -

compiler/mips/cpugas.pas

@@ -67,7 +67,10 @@ unit cpugas;
           R_SUBL, R_SUBW, R_SUBD, R_SUBQ:
            setsubreg(hr, R_SUBD);
         end;
-        result:=std_regname(hr);
+        if getregtype(r)=R_SPECIALREGISTER then
+          result:=tostr(getsupreg(r))
+        else
+          result:=std_regname(hr);
       end;
 
 

compiler/mips/opcode.inc

@@ -204,4 +204,11 @@ A_SAR64SUB,
 A_SHL64SUB,
 A_SHR64SUB,
 A_XOR64SUB,
+A_EHB,
+A_EXT,
+A_INS,
+A_MFC0,
+A_MTC0,
+A_SDBBP,
+A_WRPGPR,
 A_END_DEF

compiler/mips/racpugas.pas

@@ -59,6 +59,7 @@ Interface
       scanner,
       procinfo,
       rabase,
+      rgbase,
       itcpugas,
       cgbase,cgobj
       ;
@@ -644,7 +645,13 @@ Interface
           begin
             condition := actcondition;
             if is_calljmp(opcode) then
-            ConvertCalljmp(instr);
+              ConvertCalljmp(instr);
+            if (opcode in [A_MTC0,A_MFC0]) then
+              begin
+                if (ops<2) or (operands[2].opr.typ<>OPR_REGISTER) then
+                  message(asmr_e_syn_operand);
+                operands[2].opr.reg:=newreg(R_SPECIALREGISTER,getsupreg(operands[2].opr.reg),R_SUBNONE);
+              end;
             ConcatInstruction(curlist);
             Free;
           end;

compiler/mips/strinst.inc

@@ -204,4 +204,11 @@
 'shl64sub',
 'shr64sub',
 'xor64sub',
+'ehb',
+'ext',
+'ins',
+'mfc0',
+'mtc0',
+'sdbbp',
+'wrpgpr',
 'end_def'