* fix tcgx86.a_op_reg_reg on x86-64 and make use of it

git-svn-id: trunk@26636 -

compiler/x86/cgx86.pas

@@ -1881,7 +1881,10 @@ unit cgx86;
 
     procedure tcgx86.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
       const
-{$if defined(cpu64bitalu) or defined(cpu32bitalu)}
+{$if defined(cpu64bitalu)}
+        REGCX=NR_RCX;
+        REGCX_Size = OS_64;
+{$elseif defined(cpu32bitalu)}
         REGCX=NR_ECX;
         REGCX_Size = OS_32;
 {$elseif defined(cpu16bitalu)}

compiler/x86_64/nx64mat.pas

@@ -179,18 +179,19 @@ implementation
 
     procedure tx8664shlshrnode.pass_generate_code;
       var
-        op : Tasmop;
+        op : topcg;
         opsize : tcgsize;
         mask : aint;
+        hcountreg : TRegister;
       begin
         secondpass(left);
         secondpass(right);
 
         { determine operator }
         if nodetype=shln then
-          op:=A_SHL
+          op:=OP_SHL
         else
-          op:=A_SHR;
+          op:=OP_SHR;
 
         { special treatment of 32bit values for backwards compatibility }
         { mul optimizations require to keep the sign (FK) }
@@ -212,21 +213,33 @@ implementation
           end;
 
         { load left operators in a register }
-        location_copy(location,left.location);
-        hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,cgsize_orddef(opsize),false);
+        if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
+          { location_force_reg can be also used to change the size of a register }
+          (left.location.size<>opsize) then
+          hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(opsize),true);
+        location_reset(location,LOC_REGISTER,opsize);
+        location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
 
         { shifting by a constant directly coded: }
         if (right.nodetype=ordconstn) then
-          emit_const_reg(op,tcgsize2opsize[opsize],tordconstnode(right).value and mask,location.register)
+          cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,location.size,
+            tordconstnode(right).value.uvalue and 63,left.location.register,location.register)
         else
           begin
-            { load right operators in a RCX }
-            cg.getcpuregister(current_asmdata.CurrAsmList,NR_RCX);
-            hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,osuinttype,right.location,NR_RCX);
-
-            { right operand is in ECX }
-            cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_RCX);
-            emit_reg_reg(op,tcgsize2opsize[opsize],NR_CL,location.register);
+            { load right operators in a register - this
+              is done since most target cpu which will use this
+              node do not support a shift count in a mem. location (cec)
+            }
+            if not(right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
+               { location_force_reg can be also used to change the size of a register }
+              (right.location.size<>opsize) then
+              begin
+                hcountreg:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,cgsize_orddef(opsize),right.location,hcountreg);
+              end
+            else
+              hcountreg:=right.location.register;
+            cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,opsize,hcountreg,left.location.register,location.register);
           end;
       end;