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@@ -8618,39 +8618,77 @@ unit aoptx86;
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begin
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if (taicpu(p).oper[0]^.typ = top_const) then
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begin
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- if (taicpu(hp1).opcode = A_AND) and
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- MatchOpType(taicpu(hp1),top_const,top_reg) and
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- (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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- { the second register must contain the first one, so compare their subreg types }
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- (getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
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- (abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
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- { change
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- and const1, reg
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- and const2, reg
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- to
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- and (const1 and const2), reg
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- }
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- begin
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- taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
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- DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
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- RemoveCurrentP(p, hp1);
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- Result:=true;
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- exit;
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- end
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- else if (taicpu(hp1).opcode = A_MOVZX) and
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- MatchOpType(taicpu(hp1),top_reg,top_reg) and
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- SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^.reg) and
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- (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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- (((taicpu(p).opsize=S_W) and
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- (taicpu(hp1).opsize=S_BW)) or
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- ((taicpu(p).opsize=S_L) and
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- (taicpu(hp1).opsize in [S_WL,S_BL{$ifdef x86_64},S_BQ,S_WQ{$endif x86_64}]))
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+ case taicpu(hp1).opcode of
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+ A_AND:
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+ if MatchOpType(taicpu(hp1),top_const,top_reg) and
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+ (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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+ { the second register must contain the first one, so compare their subreg types }
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+ (getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
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+ (abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
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+ { change
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+ and const1, reg
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+ and const2, reg
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+ to
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+ and (const1 and const2), reg
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+ }
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+ begin
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+ taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
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+ DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
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+ RemoveCurrentP(p, hp1);
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+ Result:=true;
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+ exit;
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+ end;
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+
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+ A_CMP:
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+ if (PopCnt(DWord(taicpu(p).oper[0]^.val)) = 1) and { Only 1 bit set }
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+ MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.val) and
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+ MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^.reg) and
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+ { Just check that the condition on the next instruction is compatible }
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+ GetNextInstruction(hp1, hp2) and
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+ (hp2.typ = ait_instruction) and
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+ (taicpu(hp2).condition in [C_Z, C_E, C_NZ, C_NE])
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+ then
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+ { change
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+ and 2^n, reg
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+ cmp 2^n, reg
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+ j(c) / set(c) / cmov(c) (c is equal or not equal)
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+ to
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+ and 2^n, reg
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+ test reg, reg
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+ j(~c) / set(~c) / cmov(~c)
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+ }
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+ begin
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+ { Keep TEST instruction in, rather than remove it, because
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+ it may trigger other optimisations such as MovAndTest2Test }
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+ taicpu(hp1).loadreg(0, taicpu(hp1).oper[1]^.reg);
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+ taicpu(hp1).opcode := A_TEST;
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+ DebugMsg(SPeepholeOptimization + 'AND/CMP/J(c) -> AND/J(~c) with power of 2 constant', p);
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+ taicpu(hp2).condition := inverse_cond(taicpu(hp2).condition);
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+ Result := True;
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+ Exit;
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+ end;
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+
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+ A_MOVZX:
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+ if MatchOpType(taicpu(hp1),top_reg,top_reg) and
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+ SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^.reg) and
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+ (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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+ (
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+ (
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+ (taicpu(p).opsize=S_W) and
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+ (taicpu(hp1).opsize=S_BW)
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+ ) or
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+ (
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+ (taicpu(p).opsize=S_L) and
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+ (taicpu(hp1).opsize in [S_WL,S_BL{$ifdef x86_64},S_BQ,S_WQ{$endif x86_64}])
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+ )
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{$ifdef x86_64}
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- or
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- ((taicpu(p).opsize=S_Q) and
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- (taicpu(hp1).opsize in [S_BQ,S_WQ,S_BL,S_WL]))
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+ or
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+ (
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+ (taicpu(p).opsize=S_Q) and
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+ (taicpu(hp1).opsize in [S_BQ,S_WQ,S_BL,S_WL])
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+ )
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{$endif x86_64}
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- ) then
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+ ) then
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begin
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if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ff)=taicpu(p).oper[0]^.val)
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@@ -8673,108 +8711,114 @@ unit aoptx86;
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{ See if there are other optimisations possible }
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Continue;
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end;
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- end
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- else if (taicpu(hp1).opcode = A_SHL) and
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- MatchOpType(taicpu(hp1),top_const,top_reg) and
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- (getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
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- begin
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+ end;
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+
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+ A_SHL:
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+ if MatchOpType(taicpu(hp1),top_const,top_reg) and
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+ (getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
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+ begin
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{$ifopt R+}
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{$define RANGE_WAS_ON}
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{$R-}
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{$endif}
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- { get length of potential and mask }
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- MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
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+ { get length of potential and mask }
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+ MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
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- { really a mask? }
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+ { really a mask? }
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{$ifdef RANGE_WAS_ON}
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{$R+}
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{$endif}
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- if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
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- { unmasked part shifted out? }
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- ((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
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- begin
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- DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
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- RemoveCurrentP(p, hp1);
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- Result:=true;
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- exit;
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+ if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
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+ { unmasked part shifted out? }
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+ ((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
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+ RemoveCurrentP(p, hp1);
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+ Result:=true;
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+ exit;
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+ end;
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end;
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- end
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- else if (taicpu(hp1).opcode = A_SHR) and
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- MatchOpType(taicpu(hp1),top_const,top_reg) and
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- (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) and
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- (taicpu(hp1).oper[0]^.val <= 63) then
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- begin
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- { Does SHR combined with the AND cover all the bits?
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- e.g. for "andb $252,%reg; shrb $2,%reg" - the "and" can be removed }
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+ A_SHR:
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+ if MatchOpType(taicpu(hp1),top_const,top_reg) and
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+ (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) and
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+ (taicpu(hp1).oper[0]^.val <= 63) then
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+ begin
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+ { Does SHR combined with the AND cover all the bits?
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- MaskedBits := taicpu(p).oper[0]^.val or ((TCgInt(1) shl taicpu(hp1).oper[0]^.val) - 1);
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+ e.g. for "andb $252,%reg; shrb $2,%reg" - the "and" can be removed }
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- if ((taicpu(p).opsize = S_B) and ((MaskedBits and $FF) = $FF)) or
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- ((taicpu(p).opsize = S_W) and ((MaskedBits and $FFFF) = $FFFF)) or
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- ((taicpu(p).opsize = S_L) and ((MaskedBits and $FFFFFFFF) = $FFFFFFFF)) then
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- begin
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- DebugMsg(SPeepholeOptimization + 'AndShrToShr done', p);
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- RemoveCurrentP(p, hp1);
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- Result := True;
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- Exit;
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+ MaskedBits := taicpu(p).oper[0]^.val or ((TCgInt(1) shl taicpu(hp1).oper[0]^.val) - 1);
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+
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+ if ((taicpu(p).opsize = S_B) and ((MaskedBits and $FF) = $FF)) or
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+ ((taicpu(p).opsize = S_W) and ((MaskedBits and $FFFF) = $FFFF)) or
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+ ((taicpu(p).opsize = S_L) and ((MaskedBits and $FFFFFFFF) = $FFFFFFFF)) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'AndShrToShr done', p);
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+ RemoveCurrentP(p, hp1);
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+ Result := True;
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+ Exit;
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+ end;
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end;
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- end
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- else if ((taicpu(hp1).opcode = A_MOVSX){$ifdef x86_64} or (taicpu(hp1).opcode = A_MOVSXD){$endif x86_64}) and
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- (taicpu(hp1).oper[0]^.typ = top_reg) and
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- SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
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- begin
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- if SuperRegistersEqual(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) and
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- (
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+
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+ A_MOVSX{$ifdef x86_64}, A_MOVSXD{$endif x86_64}:
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+ if (taicpu(hp1).oper[0]^.typ = top_reg) and
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+ SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
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+ begin
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+ if SuperRegistersEqual(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) and
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(
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- (taicpu(hp1).opsize in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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- ((taicpu(p).oper[0]^.val and $7F) = taicpu(p).oper[0]^.val)
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- ) or (
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- (taicpu(hp1).opsize in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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- ((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val)
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+ (
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+ (taicpu(hp1).opsize in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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+ ((taicpu(p).oper[0]^.val and $7F) = taicpu(p).oper[0]^.val)
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+ ) or (
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+ (taicpu(hp1).opsize in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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+ ((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val)
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{$ifdef x86_64}
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- ) or (
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- (taicpu(hp1).opsize = S_LQ) and
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- ((taicpu(p).oper[0]^.val and $7fffffff) = taicpu(p).oper[0]^.val)
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+ ) or (
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+ (taicpu(hp1).opsize = S_LQ) and
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+ ((taicpu(p).oper[0]^.val and $7fffffff) = taicpu(p).oper[0]^.val)
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{$endif x86_64}
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- )
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- ) then
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- begin
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- if (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg){$ifdef x86_64} or (taicpu(hp1).opsize = S_LQ){$endif x86_64} then
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- begin
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- DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
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- RemoveInstruction(hp1);
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- { See if there are other optimisations possible }
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- Continue;
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- end;
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+ )
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+ ) then
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+ begin
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+ if (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg){$ifdef x86_64} or (taicpu(hp1).opsize = S_LQ){$endif x86_64} then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
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+ RemoveInstruction(hp1);
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+ { See if there are other optimisations possible }
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+ Continue;
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+ end;
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- { The super-registers are the same though.
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+ { The super-registers are the same though.
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- Note that this change by itself doesn't improve
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- code speed, but it opens up other optimisations. }
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+ Note that this change by itself doesn't improve
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+ code speed, but it opens up other optimisations. }
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{$ifdef x86_64}
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- { Convert 64-bit register to 32-bit }
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- case taicpu(hp1).opsize of
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- S_BQ:
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- begin
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- taicpu(hp1).opsize := S_BL;
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- taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
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- end;
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- S_WQ:
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- begin
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- taicpu(hp1).opsize := S_WL;
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- taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
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- end
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- else
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- ;
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- end;
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+ { Convert 64-bit register to 32-bit }
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+ case taicpu(hp1).opsize of
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+ S_BQ:
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+ begin
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+ taicpu(hp1).opsize := S_BL;
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+ taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
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+ end;
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+ S_WQ:
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+ begin
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+ taicpu(hp1).opsize := S_WL;
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+ taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
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+ end
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+ else
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+ ;
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+ end;
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{$endif x86_64}
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- DebugMsg(SPeepholeOptimization + 'AndMovsxToAndMovzx', hp1);
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- taicpu(hp1).opcode := A_MOVZX;
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- { See if there are other optimisations possible }
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- Continue;
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- end;
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- end;
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+ DebugMsg(SPeepholeOptimization + 'AndMovsxToAndMovzx', hp1);
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+ taicpu(hp1).opcode := A_MOVZX;
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+ { See if there are other optimisations possible }
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+ Continue;
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+ end;
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+ end;
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+ else
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+ ;
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+ end;
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end;
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if (taicpu(hp1).is_jmp) and
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florian