* compiles again both i386,alpha both with optimizer

compiler/new/alpha/aoptcpub.pas

@@ -0,0 +1,123 @@
+ {
+    $Id$
+    Copyright (c) 1999 by Jonas Maebe, member of the Free Pascal
+    Development Team
+
+    This unit contains several types and constants necessary for the
+    optimizer to work on the 80x86 architecture
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+Unit aoptcpub; { Assembler OPTimizer CPU specific Base }
+
+{ enable the following define if memory references can have both a base and }
+{ index register in 1 operand                                               }
+
+{$define RefsHaveIndexReg}
+
+{ enable the following define if memory references can have a scaled index }
+
+{$define RefsHaveScale}
+
+{ enable the following define if memory references can have a segment }
+{ override                                                            }
+
+{ define RefsHaveSegment}
+
+Interface
+
+Uses
+  CPUAsm,AOptBase;
+
+Type
+
+{ type of a normal instruction }
+  TInstr = Taicpu;
+  PInstr = ^TInstr;
+
+{ ************************************************************************* }
+{ **************************** TCondRegs ********************************** }
+{ ************************************************************************* }
+{ Info about the conditional registers                                      }
+  TCondRegs = Object
+    Constructor Init;
+    Destructor Done;
+  End;
+
+{ ************************************************************************* }
+{ **************************** TAoptBaseCpu ******************************* }
+{ ************************************************************************* }
+
+  TAoptBaseCpu = Object(TAoptBase)
+  End;
+
+
+{ ************************************************************************* }
+{ ******************************* Constants ******************************* }
+{ ************************************************************************* }
+Const
+
+{ the maximum number of things (registers, memory, ...) a single instruction }
+{ changes                                                                    }
+
+  MaxCh = 3;
+
+{ the maximum number of operands an instruction has }
+
+  MaxOps = 3;
+
+{Oper index of operand that contains the source (reference) with a load }
+{instruction                                                            }
+
+  LoadSrc = 0;
+
+{Oper index of operand that contains the destination (register) with a load }
+{instruction                                                                }
+
+  LoadDst = 1;
+
+{Oper index of operand that contains the source (register) with a store }
+{instruction                                                            }
+
+  StoreSrc = 0;
+
+{Oper index of operand that contains the destination (reference) with a load }
+{instruction                                                                 }
+
+  StoreDst = 1;
+
+Implementation
+
+{ ************************************************************************* }
+{ **************************** TCondRegs ********************************** }
+{ ************************************************************************* }
+Constructor TCondRegs.init;
+Begin
+End;
+
+Destructor TCondRegs.Done; {$ifdef inl} inline; {$endif inl}
+Begin
+End;
+
+End.
+
+{
+ $Log$
+ Revision 1.1  1999-11-09 22:57:09  peter
+   * compiles again both i386,alpha both with optimizer
+
+}

compiler/new/alpha/aoptcpuc.pas

@@ -0,0 +1,45 @@
+ {
+    $Id$
+    Copyright (c) 1999 by Jonas Maebe, member of the Free Pascal
+    Development Team
+
+    This unit contains the processor specific implementation of the
+    assembler optimizer common subexpression elimination object.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit aoptcpuc;
+
+Interface
+
+Uses
+  AOptCs;
+
+Type
+  TRegInfoCpu = Object(TRegInfo)
+  End;
+
+
+Implementation
+
+End.
+{
+  $Log$
+  Revision 1.1  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+}

compiler/new/alpha/aoptcpud.pas

@@ -0,0 +1,47 @@
+{
+    $Id$
+    Copyright (c) 1999 by Jonas Maebe, member of the Free Pascal
+    Development Team
+
+    This unit contains the processor specific implementation of the
+    assembler optimizer data flow analyzer.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+Unit aoptcpud;
+
+Interface
+
+uses
+  AOptDA;
+
+Type
+  PAOptDFACpu = ^TAOptDFACpu;
+  TAOptDFACpu = Object(TAOptDFA)
+  End;
+
+Implementation
+
+
+End.
+
+{
+  $Log$
+  Revision 1.1  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+}

compiler/new/alpha/cpubase.pas

@@ -70,7 +70,7 @@ Const
   lastop  = high(tasmop);
 
 type
-  TAsmCond = 
+  TAsmCond =
    (
     C_None,C_A,C_AE,C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_NA,C_NAE,
     C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_NO,C_NP,C_NS,C_NZ,C_O,C_P,
@@ -111,17 +111,29 @@ Const
   max_scratch_regs = 2;
   scratch_regs : array[1..max_scratch_regs] of tregister = (R_1,R_2);
 
+{ low and high of the available maximum width integer general purpose }
+{ registers                                                           }
+  LoGPReg = R_0;
+  HiGPReg = R_31;
+
+{ low and high of every possible width general purpose register (same as }
+{ above on most architctures apart from the 80x86)                       }
+  LoReg = R_0;
+  HiReg = R_31;
+
   cpuflags = [cf_64bitaddr];
 
   { sizes }
   pointersize   = 8;
   extended_size = 16;
-  
+
+  general_registers = [R_0..R_31];
+
   intregs = [R_0..R_31];
   fpuregs = [R_F0..R_F31];
   mmregs = [];
- 
-  availabletempregsint = [R_0..R_14,R_16..R_25,R_28];     
+
+  availabletempregsint = [R_0..R_14,R_16..R_25,R_28];
   availabletempregsfpu = [R_F0..R_F30];
   availabletempregsmm  = [];
 
@@ -134,15 +146,16 @@ Const
   registers_saved_on_cdecl = [R_9..R_14,R_F2..R_F9];
   maxvarregs = 6;
 
-  varregs : Array [1..maxvarregs] of Tregister = 
+  varregs : Array [1..maxvarregs] of Tregister =
             (R_9,R_10,R_11,R_12,R_13,R_14);
-  
-Type 
+
+Type
  TReference = record
    offset : aword;
    symbol : pasmsymbol;
    base : tregister;
    is_immediate : boolean;
+   offsetfixup : word; {needed for inline}
    { the boundary to which the reference is surely aligned }
    alignment : byte;
    end;
@@ -194,6 +207,18 @@ Const
   OQ_FLOATING_UNDERFLOW_ENABLE   = $20;  { /U }
   OQ_INTEGER_OVERFLOW_ENABLE     = $40;  { /V }
 
+
+{*****************************************************************************
+                   Opcode propeties (needed for optimizer)
+*****************************************************************************}
+
+{$ifndef NOOPT}
+Type
+{What an instruction can change}
+  TInsChange = (Ch_None);
+{$endif}
+
+
 { resets all values of ref to defaults }
 procedure reset_reference(var ref : treference);
 { set mostly used values of a new reference }
@@ -209,7 +234,7 @@ function reg2str(r : tregister) : string;
 
   procedure InitCpu;
   procedure DoneCpu;
-  
+
 implementation
 
 uses
@@ -266,15 +291,18 @@ end;
   procedure InitCpu;
     begin
     end;
-    
+
   procedure DoneCpu;
     begin
     end;
-  
+
 end.
 {
   $Log$
-  Revision 1.14  1999-08-23 23:27:55  pierre
+  Revision 1.15  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+  Revision 1.14  1999/08/23 23:27:55  pierre
    + dummy InitCpu/DoneCpu
 
   Revision 1.13  1999/08/06 16:41:10  jonas

compiler/new/aopt.pas

@@ -29,7 +29,7 @@ Interface
 Uses Aasm, cobjects, aoptobj, aoptcpud, aoptcpub {aoptcs, aoptpeep} ;
 
 Type
-
+  PAsmOptimizer = ^TAsmOptimizer;
   TAsmOptimizer = Object(TAoptObj)
 
     { _AsmL is the PAasmOutpout list that has to be optimized }
@@ -46,6 +46,9 @@ Type
 
   End;
 
+procedure Optimize(AsmL:Paasmoutput);
+
+
 Implementation
 
 uses cpuinfo, globtype, globals, tainst;
@@ -221,13 +224,27 @@ Begin
   Dispose(LabelInfo)
 End;
 
+
+procedure Optimize(AsmL:Paasmoutput);
+var
+  p : PAsmOptimizer;
+begin
+  new(p,Init(AsmL));
+  p^.Optimize;
+  dispose(p,Done);
+end;
+
+
 End.
 
 {Virtual methods, most have to be overridden by processor dependent methods}
 
 {
  $Log$
- Revision 1.3  1999-08-18 14:32:20  jonas
+ Revision 1.4  1999-11-09 22:57:08  peter
+   * compiles again both i386,alpha both with optimizer
+
+ Revision 1.3  1999/08/18 14:32:20  jonas
    + compilable!
    + dataflow analyzer finished
    + start of CSE units

compiler/new/aoptbase.pas

@@ -47,7 +47,7 @@ Type
     Function RegInRef(Reg: TRegister; Const Ref: TReference): Boolean;
 
     { returns true if the references are completely equal }
-    Function RefsEqual(Const R1, R2: TReference): Boolean;
+    {Function RefsEqual(Const R1, R2: TReference): Boolean;}
 
     { gets the next Pai object after current that contains info relevant }
     { to the optimizer in p1. If there is none, it returns false and     }
@@ -82,10 +82,33 @@ Type
 
 end;
 
+Function RefsEqual(Const R1, R2: TReference): Boolean;
+
+
 Implementation
 
 uses globals, aoptcpub, cpuinfo;
 
+Function RefsEqual(Const R1, R2: TReference): Boolean;
+Begin
+  If R1.is_immediate Then
+    RefsEqual := R2.is_immediate and (R1.Offset = R2.Offset)
+  Else
+    RefsEqual := (R1.Offset+R1.OffsetFixup = R2.Offset+R2.OffsetFixup)
+                 And (R1.Base = R2.Base)
+{$ifdef RefsHaveindex}
+                 And (R1.Index = R2.Index)
+{$endif RefsHaveindex}
+{$ifdef RefsHaveScale}
+                 And (R1.ScaleFactor = R2.ScaleFactor)
+{$endif RefsHaveScale}
+                 And (R1.Symbol = R2.Symbol)
+{$ifdef RefsHaveSegment}
+                 And (R1.Segment = R2.Segment)
+{$endif RefsHaveSegment}
+End;
+
+
 constructor taoptbase.init;
 begin
 end;
@@ -128,25 +151,6 @@ Begin
 {$endif RefsHaveIndexReg}
 End;
 
-Function TAOptBase.RefsEqual(Const R1, R2: TReference): Boolean;
-Begin
-  If R1.is_immediate Then
-    RefsEqual := R2.is_immediate and (R1.Offset = R2.Offset)
-  Else
-    RefsEqual := (R1.Offset+R1.OffsetFixup = R2.Offset+R2.OffsetFixup)
-                 And (R1.Base = R2.Base)
-{$ifdef RefsHaveindex}
-                 And (R1.Index = R2.Index)
-{$endif RefsHaveindex}
-{$ifdef RefsHaveScale}
-                 And (R1.ScaleFactor = R2.ScaleFactor)
-{$endif RefsHaveScale}
-                 And (R1.Symbol = R2.Symbol)
-{$ifdef RefsHaveSegment}
-                 And (R1.Segment = R2.Segment)
-{$endif RefsHaveSegment}
-End;
-
 Function TAOptBase.GetNextInstruction(Current: Pai; Var Next: Pai): Boolean;
 Begin
   Repeat
@@ -259,7 +263,10 @@ End.
 
 {
   $Log$
-  Revision 1.3  1999-09-08 15:01:31  jonas
+  Revision 1.4  1999-11-09 22:57:08  peter
+    * compiles again both i386,alpha both with optimizer
+
+  Revision 1.3  1999/09/08 15:01:31  jonas
     * some small changes so the noew optimizer is again compilable
 
   Revision 1.2  1999/08/23 14:41:12  jonas

compiler/new/aoptda.pas

@@ -43,8 +43,8 @@ Type
     { last one that modified the register                               }
     InstrSinceLastMod: TInstrSinceLastMod;
 
-    { convert a TChange value into the corresponding register }
-    Function TCh2Reg(Ch: TChange): TRegister; Virtual;
+    { convert a TInsChange value into the corresponding register }
+    Function TCh2Reg(Ch: TInsChange): TRegister; Virtual;
     { returns whether the instruction P reads from register Reg }
     Function RegReadByInstr(Reg: TRegister; p: Pai): Boolean; Virtual;
   End;
@@ -76,13 +76,16 @@ Begin
         Begin
           GetLastInstruction(p, hp);
           CurProp^.Regs := PPaiProp(hp^.OptInfo)^.Regs;
+{ !!!!!!!!!!!! }
+{$ifdef i386}
           CurProp^.CondRegs.Flags :=
             PPaiProp(hp^.OptInfo)^.CondRegs.Flags;
+{$endif}
         End;
       CurProp^.UsedRegs.InitWithValue(UsedRegs.GetUsedRegs);
       UsedRegs.Update(Pai(p^.Next));
       PPaiProp(p^.OptInfo) := CurProp;
-      For TmpReg := R_EAX To R_EDI Do
+      For TmpReg := LoGPReg To HiGPReg Do
         Inc(InstrSinceLastMod[TmpReg]);
       Case p^.typ Of
         ait_label:
@@ -154,17 +157,19 @@ End;
 
 Procedure TAoptDFA.CpuDFA(p: PInstr);
 Begin
-  Abstract
+  Abstract;
 End;
 
-Function TAOptDFA.TCh2Reg(Ch: TChange): TRegister;
+Function TAOptDFA.TCh2Reg(Ch: TInsChange): TRegister;
 Begin
-  Abstract
+  TCh2Reg:=R_NO;
+  Abstract;
 End;
 
 Function TAOptDFA.RegReadByInstr(Reg: TRegister; p: Pai): Boolean;
 Begin
-  Abstract
+  RegReadByInstr:=false;
+  Abstract;
 End;
 
 
@@ -172,7 +177,10 @@ End.
 
 {
   $Log$
-  Revision 1.4  1999-08-18 14:32:21  jonas
+  Revision 1.5  1999-11-09 22:57:08  peter
+    * compiles again both i386,alpha both with optimizer
+
+  Revision 1.4  1999/08/18 14:32:21  jonas
     + compilable!
     + dataflow analyzer finished
     + start of CSE units

compiler/new/aoptobj.pas

@@ -195,10 +195,10 @@ Type
 
    { returns whether two references with at least one pointing to an array }
    { may point to the same memory location                                 }
-   Function ArrayRefsEq(const r1, r2: TReference): Boolean;
 
   End;
 
+
 { ************************************************************************* }
 { ************************ Label information ****************************** }
 { ************************************************************************* }
@@ -273,12 +273,13 @@ Type
 
   End;
 
+   Function ArrayRefsEq(const r1, r2: TReference): Boolean;
 
 { ***************************** Implementation **************************** }
 
 Implementation
 
-uses hcodegen, globtype, globals, tainst;
+uses globtype, globals, cgbase, tainst;
 
 { ************************************************************************* }
 { ******************************** TUsedRegs ****************************** }
@@ -360,7 +361,7 @@ Begin
     Begin
       If IsLoadMemReg(p) Then
         With PInstr(p)^.oper[LoadSrc].ref^ Do
-          If (Base = ProcInfo.FramePointer)
+          If (Base = ProcInfo^.FramePointer)
 {$ifdef RefsHaveIndexReg}
              And (Index = R_NO)
 {$endif RefsHaveIndexReg} Then
@@ -398,8 +399,8 @@ Var TmpWState, TmpRState: Byte;
     Counter: TRegister;
 Begin
   Reg := RegMaxSize(Reg);
-  If (Reg in [R_EAX..R_EDI]) Then
-    For Counter := R_EAX to R_EDI Do
+  If (Reg in [LoGPReg..HiGPReg]) Then
+    For Counter := LoGPReg to HiGPReg Do
       With Regs[Counter] Do
         If (Counter = reg) Or
            ((Typ = Con_Ref) And
@@ -415,10 +416,13 @@ Begin
           End
 End;
 
-Function TPaiProp.ArrayRefsEq(const r1, r2: TReference): Boolean;
+Function ArrayRefsEq(const r1, r2: TReference): Boolean;
 Begin
   ArrayRefsEq := (R1.Offset+R1.OffsetFixup = R2.Offset+R2.OffsetFixup) And
-                 (R1.Segment = R2.Segment) And (R1.Base = R2.Base) And
+{$ifdef refsHaveSegmentReg}
+                 (R1.Segment = R2.Segment) And
+{$endif}
+                 (R1.Base = R2.Base) And
                  (R1.Symbol=R2.Symbol);
 End;
 
@@ -474,7 +478,8 @@ Begin
               Then
                 DestroyReg(Counter, InstrSinceLastMod)
           End
-    Else
+    End
+  Else
 {write something to a pointer location, so
    * with uncertain optimzations on:
       - do not destroy registers which contain a local/global variable or a
@@ -493,7 +498,7 @@ Begin
         {don't destroy if reg contains a parameter, local or global variable}
               Not((NrOfMods = 1) And
                   (PInstr(StartMod)^.oper[0].typ = top_ref) And
-                  ((PInstr(StartMod)^.oper[0].ref^.base = ProcInfo.FramePointer) Or
+                  ((PInstr(StartMod)^.oper[0].ref^.base = ProcInfo^.FramePointer) Or
                     Assigned(PInstr(StartMod)^.oper[0].ref^.Symbol)
                   )
                  )
@@ -504,7 +509,7 @@ End;
 Procedure TPaiProp.DestroyAllRegs(var InstrSinceLastMod: TInstrSinceLastMod);
 Var Counter: TRegister;
 Begin {initializes/desrtoys all registers}
-  For Counter := R_EAX To R_EDI Do
+  For Counter := LoGPReg To HiGPReg Do
     Begin
       ReadReg(Counter);
       DestroyReg(Counter, InstrSinceLastMod);
@@ -520,7 +525,7 @@ Begin
     top_reg: DestroyReg(o.reg, InstrSinceLastMod);
     top_ref:
       Begin
-        ReadRef(o.ref^);
+        ReadRef(o.ref);
         DestroyRefs(o.ref^, R_NO, InstrSinceLastMod);
       End;
     top_symbol:;
@@ -538,8 +543,10 @@ Procedure TPaiProp.ReadRef(Ref: PReference);
 Begin
   If Ref^.Base <> R_NO Then
     ReadReg(Ref^.Base);
+{$ifdef refsHaveIndexReg}
   If Ref^.Index <> R_NO Then
     ReadReg(Ref^.Index);
+{$endif}
 End;
 
 Procedure TPaiProp.ReadOp(const o:toper);
@@ -654,7 +661,7 @@ Begin
         (Counter <= Content.NrOfMods) Do
     Begin
       If (p^.typ = ait_instruction) And
-         RefInInstruction(Ref, p)
+         RefInInstruction(Ref, p, {$ifdef fpc}@{$endif}RefsEqual)
         Then TmpResult := True;
       Inc(Counter);
       GetNextInstruction(p,p)
@@ -784,7 +791,10 @@ End.
 
 {
  $Log$
- Revision 1.6  1999-09-29 13:50:34  jonas
+ Revision 1.7  1999-11-09 22:57:08  peter
+   * compiles again both i386,alpha both with optimizer
+
+ Revision 1.6  1999/09/29 13:50:34  jonas
    * fixes from daopt386.pas integrated
 
  Revision 1.5  1999/08/26 14:50:52  jonas

compiler/new/i386/aoptcpub.pas

@@ -60,46 +60,14 @@ Type
 { ************************************************************************* }
 { Info about the conditional registers                                      }
   TCondRegs = Object
-                Flags: Array[TFlag] of TFlagContents;
-                Constructor Init;
-                Procedure InitFlag(f: TFlag);
-                Procedure SetFlag(f: TFlag);
-                Procedure ClearFlag(f: TFlag);
-                Function GetFlag(f: TFlag): TFlagContents;
-                Destructor Done;
-              End;
-
-{ What an instruction can change }
-  TChange = (C_None,
-             { Read from a predefined register }
-             C_REAX, C_RECX, C_REDX, C_REBX, C_RESP, C_REBP, C_RESI, C_REDI,
-             { write to a predefined register }
-             C_WEAX, C_WECX, C_WEDX, C_WEBX, C_WESP, C_WEBP, C_WESI, C_WEDI,
-             { read and write from/to a predefined register }
-             C_RWEAX, C_RWECX, C_RWEDX, C_RWEBX, C_RWESP, C_RWEBP, C_RWESI, C_RWEDI,
-             { modify the contents of a register with the purpose of using  }
-             { this changed content afterwards (add/sub/..., but e.g. not   }
-             { rep (ECX) or movsd (ESI/EDI)                                 }
-{$ifdef arithopt}
-             C_MEAX, C_MECX, C_MEDX, C_MEBX, C_MESP, C_MEBP, C_MESI, C_MEDI,
-{$endif arithopt}
-             C_CDirFlag { clear direction flag }, C_SDirFlag { set dir flag },
-             { read  , write  or read and write to the flags }
-             C_RFlags, C_WFlags, C_RWFlags,
-             { change the FPU registers }
-             C_FPU,
-             { read, write or both read and write from operand x }
-             C_Rop1, C_Wop1, C_RWop1,
-             C_Rop2, C_Wop2, C_RWop2,
-             C_Rop3, C_WOp3, C_RWOp3,
-{$ifdef arithopt}
-             { modify operand x }
-             C_Mop1, C_Mop2, C_Mop3,
-{$endif arithopt}
-             { write to the memory where edi points to (movsd/stosd) }
-             C_WMemEDI,
-             { assume all integer/general purpose registers are changed }
-             C_All);
+    Flags: Array[TFlag] of TFlagContents;
+    Constructor Init;
+    Procedure InitFlag(f: TFlag);
+    Procedure SetFlag(f: TFlag);
+    Procedure ClearFlag(f: TFlag);
+    Function GetFlag(f: TFlag): TFlagContents;
+    Destructor Done;
+  End;
 
 { ************************************************************************* }
 { **************************** TAoptBaseCpu ******************************* }
@@ -119,26 +87,6 @@ Type
 { ******************************* Constants ******************************* }
 { ************************************************************************* }
 Const
-
-{$ifndef arithopt}
-   C_MEAX = C_RWEAX;
-   C_MECX = C_RWECX;
-   C_MEDX = C_RWEDX;
-   C_MEBX = C_RWEBX;
-   C_MESP = C_RWESP;
-   C_MEBP = C_RWEBP;
-   C_MESI = C_RWESI;
-   C_MEDI = C_RWEDI;
-   C_Mop1 = C_RWOp1;
-   C_Mop2 = C_RWOp2;
-   C_Mop3 = C_RWOp3;
-{$endif arithopt}
-
-{ the maximum number of things (registers, memory, ...) a single instruction }
-{ changes                                                                    }
-
-  MaxCh = 3;
-
 { the maximum number of operands an instruction has }
 
   MaxOps = 3;
@@ -163,479 +111,6 @@ Const
 
   StoreDst = 1;
 
-Type
-{ the properties of a cpu instruction }
-  TAsmInstrucProp = Record
-                      { what it changes }
-                      Ch: Array[1..MaxCh] of TChange;
-                    End;
-
-Const AsmInstr: Array[tasmop] Of TAsmInstrucProp = (
-  {A_<NONE>} (Ch: (C_All, C_None, C_None)), { new }
-  {A_LOCK} (Ch: (C_None, C_None, C_None)),
- { the repCC instructions don't write to the flags themselves, but since  }
- { they loop as long as CC is not fulfilled, it's possible that after the }
- { repCC instructions the flags have changed                              }
-  {A_REP} (Ch: (C_RWECX, C_RWFlags, C_None)),
-  {A_REPE} (Ch: (C_RWECX, C_RWFlags, C_None)),
-  {A_REPNE} (Ch: (C_RWECX, C_RWFlags, C_None)),
-  {A_REPNZ} (Ch: (C_RWECX, C_RWFLAGS, C_None)), { new }
-  {A_REPZ} (Ch: (C_RWECX, C_RWFLAGS, C_None)), { new }
-  {A_SEGCS} (Ch: (C_None, C_None, C_None)), { new }
-  {A_SEGES} (Ch: (C_None, C_None, C_None)), { new }
-  {A_SEGDS} (Ch: (C_None, C_None, C_None)), { new }
-  {A_SEGFS} (Ch: (C_None, C_None, C_None)), { new }
-  {A_SEGGS} (Ch: (C_None, C_None, C_None)), { new }
-  {A_SEGSS} (Ch: (C_None, C_None, C_None)), { new }
-  {A_AAA} (Ch: (C_MEAX, C_WFlags, C_None)),
-  {A_AAD} (Ch: (C_MEAX, C_WFlags, C_None)),
-  {A_AAM} (Ch: (C_MEAX, C_WFlags, C_None)),
-  {A_AAS} (Ch: (C_MEAX, C_WFlags, C_None)),
-  {A_ADC} (Ch: (C_Mop2, C_Rop1, C_RWFlags)),
-  {A_ADD} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_AND} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_ARPL} (Ch: (C_WFlags, C_None, C_None)),
-  {A_BOUND} (Ch: (C_Rop1, C_None, C_None)),
-  {A_BSF} (Ch: (C_Wop2, C_WFlags, C_Rop1)),
-  {A_BSR} (Ch: (C_Wop2, C_WFlags, C_Rop1)),
-  {A_BSWAP} (Ch: (C_MOp1, C_None, C_None)), { new }
-  {A_BT} (Ch: (C_WFlags, C_Rop1, C_None)),
-  {A_BTC} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_BTR} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_BTS} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_CALL} (Ch: (C_All, C_None, C_None)), {don't know value of any register}
-  {A_CBW} (Ch: (C_MEAX, C_None, C_None)),
-  {A_CDQ} (Ch: (C_MEAX, C_WEDX, C_None)),
-  {A_CLC} (Ch: (C_WFlags, C_None, C_None)),
-  {A_CLD} (Ch: (C_CDirFlag, C_None, C_None)),
-  {A_CLI} (Ch: (C_WFlags, C_None, C_None)),
-  {A_CLTS} (Ch: (C_None, C_None, C_None)),
-  {A_CMC} (Ch: (C_WFlags, C_None, C_None)),
-  {A_CMP} (Ch: (C_WFlags, C_None, C_None)),
-  {A_CMPSB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_CMPSD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_CMPSW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_CMPXCHG} (Ch: (C_All, C_None, C_None)), { new }
-  {A_CMPXCHG486} (Ch: (C_All, C_None, C_None)), { new }
-  {A_CMPXCHG8B} (Ch: (C_All, C_None, C_None)), { new }
-  {A_CPUID} (Ch: (C_All, C_None, C_none)),
-  {A_CWD} (Ch: (C_MEAX, C_WEDX, C_None)),
-  {A_CWDE} (Ch: (C_MEAX, C_None, C_None)),
-  {A_DAA} (Ch: (C_MEAX, C_None, C_None)),
-  {A_DAS} (Ch: (C_MEAX, C_None, C_None)),
-  {A_DEC} (Ch: (C_Mop1, C_WFlags, C_None)),
-  {A_DIV} (Ch: (C_RWEAX, C_WEDX, C_WFlags)), {handled separately, because modifies more than three things}
-  {A_EMMS} (Ch: (C_FPU, C_None, C_None)), { new }
-  {A_ENTER} (Ch: (C_RWESP, C_None, C_None)),
-  {A_EQU} (Ch: (C_ALL, C_None, C_None)), { new }
-  {A_F2XM1} (Ch: (C_FPU, C_None, C_None)),
-  {A_FABS} (Ch: (C_FPU, C_None, C_None)),
-  {A_FADD} (Ch: (C_FPU, C_None, C_None)),
-  {A_FADDP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FBLD} (Ch: (C_Rop1, C_FPU, C_None)),
-  {A_FBSTP} (Ch: (C_Wop1, C_FPU, C_None)),
-  {A_FCHS} (Ch: (C_FPU, C_None, C_None)),
-  {A_FCLEX} (Ch: (C_FPU, C_None, C_None)),
-  {A_FCMOVB} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCMOVBE} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCMOVE} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCMOVNB} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCMOVNBE} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCMOVNE} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCMOVNU} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCMOVU} (Ch: (C_FPU, C_RFLAGS, C_None)), { new }
-  {A_FCOM} (Ch: (C_FPU, C_None, C_None)),
-  {A_FCOMI} (Ch: (C_WFLAGS, C_None, C_None)), { new }
-  {A_FCOMIP} (Ch: (C_FPU, C_WFLAGS, C_None)), { new }
-  {A_FCOMP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FCOMPP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FCOS} (Ch: (C_FPU, C_None, C_None)),
-  {A_FDECSTP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FDISI} (Ch: (C_FPU, C_None, C_None)),
-  {A_FDIV} (Ch: (C_FPU, C_None, C_None)),
-  {A_FDIVP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FDIVR} (Ch: (C_FPU, C_None, C_None)),
-  {A_FDIVRP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FEMMS} (Ch: (C_All, C_None, C_None)), { new }
-  {A_FENI} (Ch: (C_FPU, C_None, C_None)),
-  {A_FFREE} (Ch: (C_FPU, C_None, C_None)),
-  {A_FIADD} (Ch: (C_FPU, C_None, C_None)),
-  {A_FICOM} (Ch: (C_FPU, C_None, C_None)),
-  {A_FICOMP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FIDIV} (Ch: (C_FPU, C_None, C_None)),
-  {A_FIDIVR} (Ch: (C_FPU, C_None, C_None)),
-  {A_FILD} (Ch: (C_FPU, C_None, C_None)),
-  {A_FIMUL} (Ch: (C_FPU, C_None, C_None)),
-  {A_FINCSTP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FINIT} (Ch: (C_FPU, C_None, C_None)),
-  {A_FIST} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FISTP} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FISUB} (Ch: (C_FPU, C_None, C_None)),
-  {A_FISUBR} (Ch: (C_FPU, C_None, C_None)), { new }
-  {A_FLD} (Ch: (C_Rop1, C_FPU, C_None)),
-  {A_FLD1} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDCW} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDENV} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDL2E} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDL2T} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDLG2} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDLN2} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDPI} (Ch: (C_FPU, C_None, C_None)),
-  {A_FLDZ} (Ch: (C_FPU, C_None, C_None)),
-  {A_FMUL} (Ch: (C_ROp1, C_FPU, C_None)),
-  {A_FMULP} (Ch: (C_ROp1, C_FPU, C_None)),
-  {A_FNCLEX} (Ch: (C_FPU, C_None, C_None)),
-  {A_FNDISI} (Ch: (C_FPU, C_None, C_None)),
-  {A_FNENI} (Ch: (C_FPU, C_None, C_None)),
-  {A_FNINIT} (Ch: (C_FPU, C_None, C_None)),
-  {A_FNOP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FNSAVE} (Ch: (C_FPU, C_None, C_None)),
-  {A_FNSTCW} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FNSTENV} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FNSTSW} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FPATAN} (Ch: (C_FPU, C_None, C_None)),
-  {A_FPREM} (Ch: (C_FPU, C_None, C_None)),
-  {A_FPREM1} (Ch: (C_FPU, C_None, C_None)),
-  {A_FPTAN} (Ch: (C_FPU, C_None, C_None)),
-  {A_FRNDINT} (Ch: (C_FPU, C_None, C_None)),
-  {A_FRSTOR} (Ch: (C_FPU, C_None, C_None)),
-  {A_FSAVE} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FSCALE} (Ch: (C_FPU, C_None, C_None)),
-  {A_FSETPM} (Ch: (C_FPU, C_None, C_None)),
-  {A_FSIN} (Ch: (C_FPU, C_None, C_None)),
-  {A_FSINCOS} (Ch: (C_FPU, C_None, C_None)),
-  {A_FSQRT} (Ch: (C_FPU, C_None, C_None)),
-  {A_FST} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FSTCW} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FSTENV} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FSTP} (Ch: (C_Wop1, C_FPU, C_None)),
-  {A_FSTSW} (Ch: (C_Wop1, C_None, C_None)),
-  {A_FSUB} (Ch: (C_ROp1, C_FPU, C_None)),
-  {A_FSUBP} (Ch: (C_ROp1, C_FPU, C_None)),
-  {A_FSUBR} (Ch: (C_ROp1, C_FPU, C_None)),
-  {A_FSUBRP} (Ch: (C_ROp1, C_FPU, C_None)),
-  {A_FTST} (Ch: (C_FPU, C_None, C_None)),
-  {A_FUCOM} (Ch: (C_None, C_None, C_None)), {changes fpu status word}
-  {A_FUCOMI} (Ch: (C_WFLAGS, C_None, C_None)), { new }
-  {A_FUCOMIP} (Ch: (C_FPU, C_WFLAGS, C_None)), { new }
-  {A_FUCOMP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FUCOMPP} (Ch: (C_FPU, C_None, C_None)),
-  {A_FWAIT} (Ch: (C_FPU, C_None, C_None)),
-  {A_FXAM} (Ch: (C_FPU, C_None, C_None)),
-  {A_FXCH} (Ch: (C_FPU, C_None, C_None)),
-  {A_FXTRACT} (Ch: (C_FPU, C_None, C_None)),
-  {A_FYL2X} (Ch: (C_FPU, C_None, C_None)),
-  {A_FYL2XP1} (Ch: (C_FPU, C_None, C_None)),
-  {A_HLT} (Ch: (C_None, C_None, C_None)),
-  {A_IBTS} (Ch: (C_All, C_None, C_None)), { new }
-  {A_ICEBP} (Ch: (C_All, C_None, C_None)), { new }
-  {A_IDIV} (Ch: (C_RWEAX, C_WEDX, C_WFlags)), {handled separately, because modifies more than three things}
-  {A_IMUL} (Ch: (C_RWEAX, C_WEDX, C_WFlags)), {handled separately, because several forms exist}
-  {A_IN} (Ch: (C_Wop2, C_Rop1, C_None)),
-  {A_INC} (Ch: (C_Mop1, C_WFlags, C_None)),
-  {A_INSB} (Ch: (C_WMemEDI, C_RWEDI, C_REDX)), { new }
-  {A_INSD} (Ch: (C_WMemEDI, C_RWEDI, C_REDX)), { new }
-  {A_INSW} (Ch: (C_WMemEDI, C_RWEDI, C_REDX)), { new }
-  {A_INT} (Ch: (C_All, C_None, C_None)), {don't know value of any register}
-  {A_INT01} (Ch: (C_All, C_None, C_None)), { new }
-  {A_INT1} (Ch: (C_All, C_None, C_None)), { new }
-{!!!} {A_INT03} (Ch: (C_None, C_None, C_None)),
-  {A_INT3} (Ch: (C_None, C_None, C_None)),
-  {A_INTO} (Ch: (C_All, C_None, C_None)), {don't know value of any register}
-  {A_INVD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_INVLPG} (Ch: (C_All, C_None, C_None)), { new }
-  {A_IRET} (Ch: (C_All, C_None, C_None)), {don't know value of any register}
-  {A_IRETD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_IRETW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_JCXZ} (Ch: (C_RECX, C_None, C_None)),
-  {A_JECXZ} (Ch: (C_RECX, C_None, C_None)),
-  {A_JMP} (Ch: (C_None, C_None, C_None)),
-  {A_LAHF} (Ch: (C_WEAX, C_RFlags, C_None)),
-  {A_LAR} (Ch: (C_Wop2, C_None, C_None)),
-  {A_LDS} (Ch: (C_Wop2, C_None, C_None)),
-  {A_LEA} (Ch: (C_Wop2, C_Rop1, C_None)),
-  {A_LEAVE} (Ch: (C_RWESP, C_None, C_None)),
-  {A_LES} (Ch: (C_Wop2, C_None, C_None)),
-  {A_LFS} (Ch: (C_Wop2, C_None, C_None)),
-  {A_LGDT} (Ch: (C_None, C_None, C_None)),
-  {A_LGS} (Ch: (C_Wop2, C_None, C_None)),
-  {A_LIDT} (Ch: (C_None, C_None, C_None)),
-  {A_LLDT} (Ch: (C_None, C_None, C_None)),
-  {A_LMSW} (Ch: (C_None, C_None, C_None)),
-  {A_LOADALL} (Ch: (C_All, C_None, C_None)), { new }
-  {A_LOADALL286} (Ch: (C_All, C_None, C_None)), { new }
-  {A_LODSB} (Ch: (C_WEAX, C_RWESI, C_None)), { new }
-  {A_LODSD} (Ch: (C_WEAX, C_RWESI, C_None)), { new }
-  {A_LODSW} (Ch: (C_WEAX, C_RWESI, C_None)), { new }
-  {A_LOOP} (Ch: (C_RWECX, C_None, C_None)),
-  {A_LOOPE} (Ch: (C_RWECX, C_RFlags, C_None)),
-  {A_LOOPNE} (Ch: (C_RWECX, C_RFlags, C_None)),
-  {A_LOOPNZ} (Ch: (C_RWECX, C_RFlags, C_None)),
-  {A_LOOPZ} (Ch: (C_RWECX, C_RFlags, C_None)),
-  {A_LSL} (Ch: (C_Wop2, C_WFlags, C_None)),
-  {A_LSS} (Ch: (C_Wop2, C_None, C_None)),
-  {A_LTR} (Ch: (C_None, C_None, C_None)),
-  {A_MOV} (Ch: (C_Wop2, C_Rop1, C_None)),
-  {A_MOVD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_MOVQ} (Ch: (C_All, C_None, C_None)), { new }
-  {A_MOVSB} (Ch: (C_All, C_Rop1, C_None)),
-  {A_MOVSD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_MOVSW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_MOVSX} (Ch: (C_Wop2, C_Rop1, C_None)),
-  {A_MOVZX} (Ch: (C_Wop2, C_Rop1, C_None)),
-  {A_MUL} (Ch: (C_RWEAX, C_WEDX, C_WFlags)), {handled separately, because modifies more than three things}
-  {A_NEG} (Ch: (C_Mop1, C_None, C_None)),
-  {A_NOP} (Ch: (C_None, C_None, C_None)),
-  {A_NOT} (Ch: (C_Mop1, C_WFlags, C_None)),
-  {A_OR} (Ch: (C_Mop2, C_WFlags, C_None)),
-  {A_OUT} (Ch: (C_Rop1, C_Rop2, C_None)),
-  {A_OUTSB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_OUTSD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_OUTSW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PACKSSDW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PACKSSWB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PACKUSWB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDSB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDSIW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDSW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDUSB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDUSW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PADDW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PAND} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PANDN} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PAVEB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PAVGUSB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PCMPEQB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PCMPEQD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PCMPEQW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PCMPGTB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PCMPGTD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PCMPGTW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PDISTIB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PF2ID} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFACC} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFADD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFCMPEQ} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFCMPGE} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFCMPGT} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFMAX} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFMIN} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFMUL} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFRCP} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFRCPIT1} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFRCPIT2} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFRSQIT1} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFRSQRT} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFSUB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PFSUBR} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PI2FD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMACHRIW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMADDWD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMAGW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMULHRIW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMULHRWA} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMULHRWC} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMULHW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMULLW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMVGEZB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMVLZB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMVNZB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PMVZB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_POP} (Ch: (C_Wop1, C_RWESP, C_None)),
-  {A_POPA} (Ch: (C_All, C_None, C_None)), {don't know value of any register}
-  {A_POPAD} (Ch: (C_All, C_None, C_None)), {don't know value of any register}
-  {A_POPAW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_POPF} (Ch: (C_RWESP, C_WFlags, C_None)),
-  {A_POPFD} (Ch: (C_RWESP, C_WFlags, C_None)),
-  {A_POPFW} (Ch: (C_RWESP, C_WFLAGS, C_None)), { new }
-  {A_POR} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PREFETCH} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PREFETCHW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSLLD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSLLQ} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSLLW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSRAD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSRAW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSRLD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSRLQ} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSRLW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBSB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBSIW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBSW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBUSB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBUSW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PSUBW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUNPCKHBW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUNPCKHDQ} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUNPCKHWD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUNPCKLBW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUNPCKLDQ} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUNPCKLWD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUSH} (Ch: (C_Rop1, C_RWESP, C_None)),
-  {A_PUSHA} (Ch: (C_All, C_None, C_None)),
-  {A_PUSHAD} (Ch: (C_All, C_None, C_None)),
-  {A_PUSHAW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_PUSHF} (Ch: (C_RWESP, C_RFlags, C_None)),
-  {A_PUSHFD} (Ch: (C_RWESP, C_RFlags, C_None)),
-  {A_PUSHFW} (Ch: (C_RWESP, C_RFLAGS, C_None)), { new }
-  {A_PXOR} (Ch: (C_All, C_None, C_None)), { new }
-  {A_RCL} (Ch: (C_Mop2, C_Rop1, C_RWFlags)),
-  {A_RCR} (Ch: (C_Mop2, C_Rop1, C_RWFlags)),
-{!!!}  {A_RDSHR} (Ch: (C_All, C_None, C_None)), { new }
-  {A_RDMSR} (Ch: (C_WEAX, C_WEDX, C_None)), { new }
-  {A_RDPMC} (Ch: (C_WEAX, C_WEDX, C_None)), { new }
-  {A_RDTSC} (Ch: (C_WEAX, C_WEDX, C_None)), { new }
-  {A_RESB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_RET} (Ch: (C_All, C_None, C_None)),
-  {A_RETF} (Ch: (C_All, C_None, C_None)), { new }
-  {A_RETN} (Ch: (C_All, C_None, C_None)), { new }
-  {A_ROL} (Ch: (C_Mop2, C_Rop1, C_RWFlags)),
-  {A_ROR} (Ch: (C_Mop2, C_Rop1, C_RWFlags)),
-{!!!}  {A_RSDC} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_RSLDT} (Ch: (C_All, C_None, C_None)), { new }
-  {A_RSM} (Ch: (C_All, C_None, C_None)), { new }
-  {A_SAHF} (Ch: (C_WFlags, C_REAX, C_None)),
-  {A_SAL} (Ch: (C_Mop2, C_Rop1, C_RWFlags)),
-  {A_SALC} (Ch: (C_WEAX, C_RFLAGS, C_None)), { new }
-  {A_SAR} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_SBB} (Ch: (C_Mop2, C_Rop1, C_RWFlags)),
-  {A_SCASB} (Ch: (C_All, C_None, C_None)), { new }
-  {A_SCASD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_SCASW} (Ch: (C_All, C_None, C_None)), { new }
-  {A_SGDT} (Ch: (C_Wop1, C_None, C_None)),
-  {A_SHL} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_SHLD} (Ch: (C_MOp3, C_RWFlags, C_Rop2)),
-  {A_SHR} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_SHRD} (Ch: (C_MOp3, C_RWFlags, C_Rop2)),
-  {A_SIDT} (Ch: (C_Wop1, C_None, C_None)),
-  {A_SLDT} (Ch: (C_Wop1, C_None, C_None)),
-  {A_SMI} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SMINT} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SMINTOLD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_SMSW} (Ch: (C_Wop1, C_None, C_None)),
-  {A_STC} (Ch: (C_WFlags, C_None, C_None)),
-  {A_STD} (Ch: (C_SDirFlag, C_None, C_None)),
-  {A_STI} (Ch: (C_WFlags, C_None, C_None)),
-  {A_STOSB} (Ch: (C_REAX, C_WMemEDI, C_RWEDI)), { new }
-  {A_STOSD} (Ch: (C_REAX, C_WMemEDI, C_RWEDI)), { new }
-  {A_STOSW} (Ch: (C_REAX, C_WMemEDI, C_RWEDI)), { new }
-  {A_STR}  (Ch: (C_Wop1, C_None, C_None)),
-  {A_SUB} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-{!!!}  {A_SVDC} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SVLDT} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SVTS} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SYSCALL} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SYSENTER} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SYSEXIT} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_SYSRET} (Ch: (C_All, C_None, C_None)), { new }
-  {A_TEST} (Ch: (C_WFlags, C_Rop1, C_Rop2)),
-{!!!}  {A_UD1} (Ch: (C_All, C_None, C_None)), { new }
-{!!!}  {A_UD2} (Ch: (C_All, C_None, C_None)), { new }
-  {A_UMOV} (Ch: (C_All, C_None, C_None)), { new }
-  {A_VERR} (Ch: (C_WFlags, C_None, C_None)),
-  {A_VERW} (Ch: (C_WFlags, C_None, C_None)),
-  {A_WAIT} (Ch: (C_None, C_None, C_None)),
-  {A_WBINVD} (Ch: (C_None, C_None, C_None)), { new }
-{!!!}  {A_WRSHR} (Ch: (C_All, C_None, C_None)), { new }
-  {A_WRMSR} (Ch: (C_All, C_None, C_None)), { new }
-  {A_XADD} (Ch: (C_All, C_None, C_None)), { new }
-  {A_XBTS} (Ch: (C_All, C_None, C_None)), { new }
-  {A_XCHG} (Ch: (C_RWop1, C_RWop2, C_None)), {(might be) handled seperately}
-  {A_XLAT} (Ch: (C_WEAX, C_REBX, C_None)),
-  {A_XLATB} (Ch: (C_WEAX, C_REBX, C_None)),
-  {A_XOR} (Ch: (C_Mop2, C_Rop1, C_WFlags)),
-  {A_CMOV} (Ch: (C_ROp1, C_WOp2, C_RFLAGS)), { new }
-  {A_J} (Ch: (C_None, C_None, C_None)), { new }
-  {A_SET} (Ch: (C_WEAX, C_RFLAGS, C_None)),  { new }
-{!!!! From here everything is new !!!!!!!!}
-  {ADDPS} (Ch: (C_All, C_None, C_None)), { new }
-  {ADDSS} (Ch: (C_All, C_None, C_None)), { new }
-  {ANDNPS} (Ch: (C_All, C_None, C_None)), { new }
-  {ANDPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPEQPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPEQSS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPLEPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPLESS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPLTPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPLTSS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPNEQPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPNEQSS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPNLEPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPNLESS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPNLTPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPNLTSS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPORDPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPORDSS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPUNORDPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPUNORDSS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPPS} (Ch: (C_All, C_None, C_None)), { new }
-  {CMPSS} (Ch: (C_All, C_None, C_None)), { new }
-  {COMISS} (Ch: (C_All, C_None, C_None)), { new }
-  {CVTPI2PS} (Ch: (C_All, C_None, C_None)), { new }
-  {CVTPS2PI} (Ch: (C_All, C_None, C_None)), { new }
-  {CVTSI2SS} (Ch: (C_All, C_None, C_None)), { new }
-  {CVTSS2SI} (Ch: (C_All, C_None, C_None)), { new }
-  {CVTTPS2PI} (Ch: (C_All, C_None, C_None)), { new }
-  {CVTTSS2SI} (Ch: (C_All, C_None, C_None)), { new }
-  {DIVPS} (Ch: (C_All, C_None, C_None)), { new }
-  {DIVSS} (Ch: (C_All, C_None, C_None)), { new }
-  {LDMXCSR} (Ch: (C_All, C_None, C_None)), { new }
-  {MAXPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MAXSS} (Ch: (C_All, C_None, C_None)), { new }
-  {MINPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MINSS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVAPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVHPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVLHPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVLPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVHLPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVMSKPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVNTPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVSS} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVUPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MULPS} (Ch: (C_All, C_None, C_None)), { new }
-  {MULSS} (Ch: (C_All, C_None, C_None)), { new }
-  {ORPS} (Ch: (C_All, C_None, C_None)), { new }
-  {RCPPS} (Ch: (C_All, C_None, C_None)), { new }
-  {RCPSS} (Ch: (C_All, C_None, C_None)), { new }
-  {RSQRTPS} (Ch: (C_All, C_None, C_None)), { new }
-  {RSQRTSS} (Ch: (C_All, C_None, C_None)), { new }
-  {SHUFPS} (Ch: (C_All, C_None, C_None)), { new }
-  {SQRTPS} (Ch: (C_All, C_None, C_None)), { new }
-  {SQRTSS} (Ch: (C_All, C_None, C_None)), { new }
-  {STMXCSR} (Ch: (C_All, C_None, C_None)), { new }
-  {SUBPS} (Ch: (C_All, C_None, C_None)), { new }
-  {SUBSS} (Ch: (C_All, C_None, C_None)), { new }
-  {UCOMISS} (Ch: (C_All, C_None, C_None)), { new }
-  {UNPCKHPS} (Ch: (C_All, C_None, C_None)), { new }
-  {UNPCKLPS} (Ch: (C_All, C_None, C_None)), { new }
-  {XORPS} (Ch: (C_All, C_None, C_None)), { new }
-  {FXRSTOR} (Ch: (C_All, C_None, C_None)), { new }
-  {FXSAVE} (Ch: (C_All, C_None, C_None)), { new }
-  {PREFETCHNTA} (Ch: (C_All, C_None, C_None)), { new }
-  {PREFETCHT0} (Ch: (C_All, C_None, C_None)), { new }
-  {PREFETCHT1} (Ch: (C_All, C_None, C_None)), { new }
-  {PREFETCHT2} (Ch: (C_All, C_None, C_None)), { new }
-  {SFENCE} (Ch: (C_All, C_None, C_None)), { new }
-  {MASKMOVQ} (Ch: (C_All, C_None, C_None)), { new }
-  {MOVNTQ} (Ch: (C_All, C_None, C_None)), { new }
-  {PAVGB} (Ch: (C_All, C_None, C_None)), { new }
-  {PAVGW} (Ch: (C_All, C_None, C_None)), { new }
-  {PEXTRW} (Ch: (C_All, C_None, C_None)), { new }
-  {PINSRW} (Ch: (C_All, C_None, C_None)), { new }
-  {PMAXSW} (Ch: (C_All, C_None, C_None)), { new }
-  {PMAXUB} (Ch: (C_All, C_None, C_None)), { new }
-  {PMINSW} (Ch: (C_All, C_None, C_None)), { new }
-  {PMINUB} (Ch: (C_All, C_None, C_None)), { new }
-  {PMOVMSKB} (Ch: (C_All, C_None, C_None)), { new }
-  {PMULHUW} (Ch: (C_All, C_None, C_None)), { new }
-  {PSADBW} (Ch: (C_All, C_None, C_None)), { new }
-  {PSHUFW} (Ch: (C_All, C_None, C_None)) { new }
-  );
 
 Implementation
 
@@ -739,7 +214,10 @@ End.
 
 {
  $Log$
- Revision 1.6  1999-09-08 15:05:43  jonas
+ Revision 1.7  1999-11-09 22:57:09  peter
+   * compiles again both i386,alpha both with optimizer
+
+ Revision 1.6  1999/09/08 15:05:43  jonas
    * some small changes so the new optimizer is again compilable
 
  Revision 1.5  1999/08/25 12:00:19  jonas

compiler/new/i386/aoptcpuc.pas

@@ -26,6 +26,9 @@ unit aoptcpuc;
 
 Interface
 
+Uses
+  CpuBase,AOptCs;
+
 Type
   TRegInfoCpu = Object(TRegInfo)
     Procedure AddReg(OldReg, NewReg: TRegister); Virtual;
@@ -82,7 +85,10 @@ End;
 End.
 {
   $Log$
-  Revision 1.1  1999-08-18 14:32:26  jonas
+  Revision 1.2  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+  Revision 1.1  1999/08/18 14:32:26  jonas
     + compilable!
     + dataflow analyzer finished
     + start of CSE units

compiler/new/i386/aoptcpud.pas

@@ -1,5 +1,5 @@
 {
-    $Id $
+    $Id$
     Copyright (c) 1999 by Jonas Maebe, member of the Free Pascal
     Development Team
 
@@ -35,7 +35,7 @@ Type
 
     { handles the processor dependent dataflow analizing               }
     Procedure CpuDFA(p: PInstr); Virtual;
-    Function TCh2Reg(Ch: TChange): TRegister; Virtual;
+    Function TCh2Reg(Ch: TInsChange): TRegister; Virtual;
     Function RegReadByInstr(Reg: TRegister; p: Pai): Boolean; Virtual;
   End;
 
@@ -48,7 +48,7 @@ Procedure TAOptDFACpu.CpuDFA(p: PInstr);
 { for the instructions between blockstart and blockend. Returns the last pai }
 { which has been processed                                                   }
 Var CurProp: PPaiProp;
-    InstrProp: TAsmInstrucProp;
+    InstrProp: TInsProp;
     TmpRef: TReference;
     Cnt: Byte;
 Begin
@@ -108,67 +108,67 @@ Begin
         End
     Else
       Begin
-        InstrProp := AsmInstr[p^.OpCode];
+        InstrProp := InsProp[p^.OpCode];
         Cnt := 1;
         While (Cnt <= MaxCh) And
-              (InstrProp.Ch[Cnt] <> C_None) Do
+              (InstrProp.Ch[Cnt] <> Ch_None) Do
           Begin
             Case InstrProp.Ch[Cnt] Of
-              C_REAX..C_REDI:
+              Ch_REAX..Ch_REDI:
                 CurProp^.ReadReg(TCh2Reg(InstrProp.Ch[Cnt]));
-              C_WEAX..C_RWEDI:
+              Ch_WEAX..Ch_RWEDI:
                 Begin
-                  If (InstrProp.Ch[Cnt] >= C_RWEAX) Then
+                  If (InstrProp.Ch[Cnt] >= Ch_RWEAX) Then
                     CurProp^.ReadReg(TCh2Reg(InstrProp.Ch[Cnt]));
                   CurProp^.DestroyReg(TCh2Reg(InstrProp.Ch[Cnt]),InstrSinceLastMod);
                 End;
           {$ifdef arithopt}
-              C_MEAX..C_MEDI:
+              Ch_MEAX..Ch_MEDI:
                 CurProp^.ModifyReg(TCh2Reg(InstrProp.Ch[Cnt]), InstrSinceLastMod);
           {$endif arithopt}
-              C_CDirFlag: CurProp^.CondRegs.ClearFlag(DirFlag);
-              C_SDirFlag: CurProp^.CondRegs.SetFlag(DirFlag);
-              C_Rop1: CurProp^.ReadOp(p^.oper[0]);
-              C_Rop2: CurProp^.ReadOp(p^.oper[1]);
-              C_Rop3: CurProp^.ReadOp(p^.oper[2]);
-              C_Wop1..C_RWop1:
+              Ch_CDirFlag: CurProp^.CondRegs.ClearFlag(DirFlag);
+              Ch_SDirFlag: CurProp^.CondRegs.SetFlag(DirFlag);
+              Ch_Rop1: CurProp^.ReadOp(p^.oper[0]);
+              Ch_Rop2: CurProp^.ReadOp(p^.oper[1]);
+              Ch_Rop3: CurProp^.ReadOp(p^.oper[2]);
+              Ch_Wop1..Ch_RWop1:
                 Begin
-                  If (InstrProp.Ch[Cnt] = C_RWop1) Then
+                  If (InstrProp.Ch[Cnt] = Ch_RWop1) Then
                     CurProp^.ReadOp(p^.oper[0]);
                   CurProp^.DestroyOp(p^.oper[0], InstrSinceLastMod);
                 End;
         {$ifdef arithopt}
-              C_Mop1:
+              Ch_Mop1:
                 CurProp^.ModifyOp(p^.oper[0], InstrSinceLastMod);
         {$endif arithopt}
-              C_Wop2..C_RWop2:
+              Ch_Wop2..Ch_RWop2:
                 Begin
-                  If (InstrProp.Ch[Cnt] = C_RWop2) Then
+                  If (InstrProp.Ch[Cnt] = Ch_RWop2) Then
                     CurProp^.ReadOp(p^.oper[1]);
                   CurProp^.DestroyOp(p^.oper[1], InstrSinceLastMod);
                 End;
         {$ifdef arithopt}
-              C_Mop2:
+              Ch_Mop2:
                 CurProp^.ModifyOp(p^.oper[1], InstrSinceLastMod);
         {$endif arithopt}
-              C_Wop3..C_RWop3:
+              Ch_Wop3..Ch_RWop3:
                 Begin
-                  If (InstrProp.Ch[Cnt] = C_RWop3) Then
+                  If (InstrProp.Ch[Cnt] = Ch_RWop3) Then
                     CurProp^.ReadOp(p^.oper[2]);
                   CurProp^.DestroyOp(p^.oper[2], InstrSinceLastMod);
                 End;
         {$ifdef arithopt}
-              C_Mop3:
+              Ch_Mop3:
                 CurProp^.ModifyOp(p^.oper[2], InstrSinceLastMod);
         {$endif arithopt}
-              C_WMemEDI:
+              Ch_WMemEDI:
                 Begin
                   CurProp^.ReadReg(R_EDI);
                   FillChar(TmpRef, SizeOf(TmpRef), 0);
                   TmpRef.Base := R_EDI;
                   CurProp^.DestroyRefs(TmpRef, R_NO, InstrSinceLastMod)
                 End;
-              C_RFlags, C_WFlags, C_RWFlags, C_FPU:;
+              Ch_RFlags, Ch_WFlags, Ch_RWFlags, Ch_FPU:;
               Else CurProp^.DestroyAllRegs(InstrSinceLastMod)
             End;
             Inc(Cnt)
@@ -179,7 +179,7 @@ End;
 
 Function TAOptDFACpu.RegReadByInstr(Reg: TRegister; p: Pai): Boolean;
 Var Cnt: AWord;
-    InstrProp: TAsmInstrucProp;
+    InstrProp: TInsProp;
     TmpResult: Boolean;
 Begin
   TmpResult := False;
@@ -204,31 +204,31 @@ Begin
       Else
         Begin
           Cnt := 1;
-          InstrProp := AsmInstr[PInstr(p)^.OpCode];
+          InstrProp := InsProp[PInstr(p)^.OpCode];
           While (Cnt <= MaxCh) And
-                (InstrProp.Ch[Cnt] <> C_None) And
+                (InstrProp.Ch[Cnt] <> Ch_None) And
                 Not(TmpResult) Do
             Begin
               Case InstrProp.Ch[Cnt] Of
-                C_REAX..C_REDI,C_RWEAX..C_RWEDI
+                Ch_REAX..Ch_REDI,Ch_RWEAX..Ch_RWEDI
   {$ifdef arithopt}
-                ,C_MEAX..C_MEDI
+                ,Ch_MEAX..Ch_MEDI
   {$endif arithopt}:
                   TmpResult := Reg = TCh2Reg(InstrProp.Ch[Cnt]);
-                C_ROp1,C_RWOp1{$ifdef arithopt},C_Mop1{$endif arithopt}:
+                Ch_ROp1,Ch_RWOp1{$ifdef arithopt},Ch_Mop1{$endif arithopt}:
                   TmpResult := RegInOp(Reg,PInstr(p)^.oper[0]);
-                C_ROp2,C_RWOp2{$ifdef arithopt},C_Mop2{$endif arithopt}:
+                Ch_ROp2,Ch_RWOp2{$ifdef arithopt},Ch_Mop2{$endif arithopt}:
                   TmpResult := RegInOp(Reg,PInstr(p)^.oper[1]);
-                C_ROp3,C_RWOp3{$ifdef arithopt},C_Mop3{$endif arithopt}:
+                Ch_ROp3,Ch_RWOp3{$ifdef arithopt},Ch_Mop3{$endif arithopt}:
                   TmpResult := RegInOp(Reg,PInstr(p)^.oper[2]);
-                C_WOp1: TmpResult := (PInstr(p)^.oper[0].typ = top_ref) And
+                Ch_WOp1: TmpResult := (PInstr(p)^.oper[0].typ = top_ref) And
                                      RegInRef(Reg,PInstr(p)^.oper[0].ref^);
-                C_WOp2: TmpResult := (PInstr(p)^.oper[1].typ = top_ref) And
+                Ch_WOp2: TmpResult := (PInstr(p)^.oper[1].typ = top_ref) And
                                      RegInRef(Reg,PInstr(p)^.oper[1].ref^);
-                C_WOp3: TmpResult := (PInstr(p)^.oper[2].typ = top_ref) And
+                Ch_WOp3: TmpResult := (PInstr(p)^.oper[2].typ = top_ref) And
                                      RegInRef(Reg,PInstr(p)^.oper[2].ref^);
-                C_WMemEDI: TmpResult := (Reg = R_EDI);
-                C_FPU: TmpResult := Reg in [R_ST..R_ST7,R_MM0..R_MM7]
+                Ch_WMemEDI: TmpResult := (Reg = R_EDI);
+                Ch_FPU: TmpResult := Reg in [R_ST..R_ST7,R_MM0..R_MM7]
               End;
               Inc(Cnt)
             End
@@ -237,19 +237,19 @@ Begin
   RegReadByInstr := TmpResult
 End;
 
-Function TAOptDFACpu.TCh2Reg(Ch: TChange): TRegister;
+Function TAOptDFACpu.TCh2Reg(Ch: TInsChange): TRegister;
 Begin
-  If (Ch <= C_REDI) Then
+  If (Ch <= Ch_REDI) Then
     TCh2Reg := TRegister(Byte(Ch))
   Else
-    If (Ch <= C_WEDI) Then
-      TCh2Reg := TRegister(Byte(Ch) - Byte(C_REDI))
+    If (Ch <= Ch_WEDI) Then
+      TCh2Reg := TRegister(Byte(Ch) - Byte(Ch_REDI))
     Else
-      If (Ch <= C_RWEDI) Then
-        TCh2Reg := TRegister(Byte(Ch) - Byte(C_WEDI))
+      If (Ch <= Ch_RWEDI) Then
+        TCh2Reg := TRegister(Byte(Ch) - Byte(Ch_WEDI))
       Else
-        If (Ch <= C_MEDI) Then
-          TCh2Reg := TRegister(Byte(Ch) - Byte(C_RWEDI))
+        If (Ch <= Ch_MEDI) Then
+          TCh2Reg := TRegister(Byte(Ch) - Byte(Ch_RWEDI))
 End;
 
 
@@ -257,7 +257,10 @@ End.
 
 {
   $Log$
-  Revision 1.3  1999-09-08 15:01:31  jonas
+  Revision 1.4  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+  Revision 1.3  1999/09/08 15:01:31  jonas
     * some small changes so the noew optimizer is again compilable
 
   Revision 1.2  1999/08/18 14:32:26  jonas

compiler/new/i386/cgcpu.pas

@@ -49,12 +49,7 @@ unit cgcpu;
   implementation
 
     uses
-<<<<<<< cgcpu.pas
-       globtype,globals,cpuasm,symconst,symtable,cgbase,
-       verbose;
-=======
        globtype,globals,cpuasm,symconst,symtable,cgbase,verbose;
->>>>>>> 1.6
 
     constructor tcg386.init;
 
@@ -145,7 +140,10 @@ unit cgcpu;
 end.
 {
   $Log$
-  Revision 1.7  1999-09-15 20:35:47  florian
+  Revision 1.8  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+  Revision 1.7  1999/09/15 20:35:47  florian
     * small fix to operator overloading when in MMX mode
     + the compiler uses now fldz and fld1 if possible
     + some fixes to floating point registers

compiler/new/powerpc/aoptcpub.pas

@@ -0,0 +1,123 @@
+ {
+    $Id$
+    Copyright (c) 1999 by Jonas Maebe, member of the Free Pascal
+    Development Team
+
+    This unit contains several types and constants necessary for the
+    optimizer to work on the 80x86 architecture
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+Unit aoptcpub; { Assembler OPTimizer CPU specific Base }
+
+{ enable the following define if memory references can have both a base and }
+{ index register in 1 operand                                               }
+
+{$define RefsHaveIndexReg}
+
+{ enable the following define if memory references can have a scaled index }
+
+{$define RefsHaveScale}
+
+{ enable the following define if memory references can have a segment }
+{ override                                                            }
+
+{ define RefsHaveSegment}
+
+Interface
+
+Uses
+  CPUAsm,AOptBase;
+
+Type
+
+{ type of a normal instruction }
+  TInstr = Taicpu;
+  PInstr = ^TInstr;
+
+{ ************************************************************************* }
+{ **************************** TCondRegs ********************************** }
+{ ************************************************************************* }
+{ Info about the conditional registers                                      }
+  TCondRegs = Object
+    Constructor Init;
+    Destructor Done;
+  End;
+
+{ ************************************************************************* }
+{ **************************** TAoptBaseCpu ******************************* }
+{ ************************************************************************* }
+
+  TAoptBaseCpu = Object(TAoptBase)
+  End;
+
+
+{ ************************************************************************* }
+{ ******************************* Constants ******************************* }
+{ ************************************************************************* }
+Const
+
+{ the maximum number of things (registers, memory, ...) a single instruction }
+{ changes                                                                    }
+
+  MaxCh = 3;
+
+{ the maximum number of operands an instruction has }
+
+  MaxOps = 3;
+
+{Oper index of operand that contains the source (reference) with a load }
+{instruction                                                            }
+
+  LoadSrc = 0;
+
+{Oper index of operand that contains the destination (register) with a load }
+{instruction                                                                }
+
+  LoadDst = 1;
+
+{Oper index of operand that contains the source (register) with a store }
+{instruction                                                            }
+
+  StoreSrc = 0;
+
+{Oper index of operand that contains the destination (reference) with a load }
+{instruction                                                                 }
+
+  StoreDst = 1;
+
+Implementation
+
+{ ************************************************************************* }
+{ **************************** TCondRegs ********************************** }
+{ ************************************************************************* }
+Constructor TCondRegs.init;
+Begin
+End;
+
+Destructor TCondRegs.Done; {$ifdef inl} inline; {$endif inl}
+Begin
+End;
+
+End.
+
+{
+ $Log$
+ Revision 1.1  1999-11-09 22:57:09  peter
+   * compiles again both i386,alpha both with optimizer
+
+}

compiler/new/powerpc/aoptcpuc.pas

@@ -0,0 +1,45 @@
+ {
+    $Id$
+    Copyright (c) 1999 by Jonas Maebe, member of the Free Pascal
+    Development Team
+
+    This unit contains the processor specific implementation of the
+    assembler optimizer common subexpression elimination object.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit aoptcpuc;
+
+Interface
+
+Uses
+  AOptCs;
+
+Type
+  TRegInfoCpu = Object(TRegInfo)
+  End;
+
+
+Implementation
+
+End.
+{
+  $Log$
+  Revision 1.1  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+}

compiler/new/powerpc/aoptcpud.pas

@@ -0,0 +1,47 @@
+{
+    $Id$
+    Copyright (c) 1999 by Jonas Maebe, member of the Free Pascal
+    Development Team
+
+    This unit contains the processor specific implementation of the
+    assembler optimizer data flow analyzer.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+Unit aoptcpud;
+
+Interface
+
+uses
+  AOptDA;
+
+Type
+  PAOptDFACpu = ^TAOptDFACpu;
+  TAOptDFACpu = Object(TAOptDFA)
+  End;
+
+Implementation
+
+
+End.
+
+{
+  $Log$
+  Revision 1.1  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+}

compiler/new/powerpc/cpubase.pas

@@ -377,7 +377,7 @@ const
   param_regs_fpu: Array[1..max_param_regs_fpu] of tregister =
     (R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13);
 
-
+  general_registers = [R_0..R_31];
 
   intregs = [R_0..R_31];
   fpuregs = [R_F0..R_F31];
@@ -397,6 +397,16 @@ const
   max_scratch_regs = 3;
   scratch_regs: Array[1..max_scratch_regs] of TRegister = (R_11,R_12,R_30);
 
+{ low and high of the available maximum width integer general purpose }
+{ registers                                                           }
+  LoGPReg = R_0;
+  HiGPReg = R_31;
+
+{ low and high of every possible width general purpose register (same as }
+{ above on most architctures apart from the 80x86)                       }
+  LoReg = R_0;
+  HiReg = R_31;
+
 (*  cpuflags : set of tcpuflags = []; *)
 
   { sizes }
@@ -549,7 +559,10 @@ implementation
 end.
 {
   $Log$
-  Revision 1.9  1999-10-20 12:21:34  jonas
+  Revision 1.10  1999-11-09 22:57:09  peter
+    * compiles again both i386,alpha both with optimizer
+
+  Revision 1.9  1999/10/20 12:21:34  jonas
     * changed scratch_registers to (R_11,_R12,R_30) because R_0 is a special
       case and R_31 is used as some kind of frame pointer under LinuxPPC