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@@ -146,6 +146,9 @@ unit aoptx86;
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{ Returns true if the given logic instruction can be converted into a BTx instruction (BT not included) }
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class function IsBTXAcceptable(p : tai) : boolean; static;
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+ { Returns the index of an input operand that can take a register or a
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+ reference, or -1 if there isn't one }
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+ class function GetRMReadIndex(var p : tai) : integer; static;
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{ Converts the LEA instruction to ADD/INC/SUB/DEC. Returns True if the
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conversion was successful }
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@@ -2885,6 +2888,115 @@ unit aoptx86;
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end;
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+ class function TX86AsmOptimizer.GetRMReadIndex(var p : taI): integer;
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+ var
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+ hp: taicpu absolute p; { Implicit typecast }
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+ begin
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+ if p.typ<>ait_instruction then
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+ begin
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+ Result:=-1;
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+ Exit;
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+ end;
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+
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+ { Remember we're looking for input operands that can either be a
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+ register or a reference. If it can take only a register or only a
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+ reference, or is read/write, it doesn't count }
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+ case hp.opcode of
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+ A_MOV,
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+ A_ADC,
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+ A_ADD,
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+ A_AND,
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+ A_CMP,
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+ A_OR,
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+ A_SBB,
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+ A_SUB,
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+ A_TEST,
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+ A_XOR:
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+ if (hp.oper[0]^.typ=top_reg) and
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+ (hp.oper[1]^.typ=top_reg) and
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+ { Don't count "xor %reg,%reg" etc. }
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+ (hp.oper[0]^.reg<>hp.oper[1]^.reg) then
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+ Result:=0
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+ else
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+ Result:=-1;
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+
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+ A_MOVZX,
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+ A_MOVSX,
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+{$ifdef x86_64}
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+ A_MOVSXD,
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+{$endif x86_64}
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+ A_BSF,
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+ A_BSR,
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+ A_CMOVcc,
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+ A_CVTSI2SS,
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+ A_CVTSI2SD,
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+ A_LZCNT,
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+ A_POPCNT,
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+ A_VCVTSI2SS,
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+ A_VCVTSI2SD,
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+ { BMI1 instructions }
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+ A_ANDN, A_BLSI, A_BLSMSK, A_BLSR, A_TZCNT,
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+ { BMI2 instructions }
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+ A_MULX, A_PDEP, A_PEXT,
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+ { ADX }
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+ A_ADCX, A_ADOX:
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+ Result:=0;
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+
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+ { BMI1 instructions }
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+ A_BEXTR,
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+ { BMI2 instructions }
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+ A_BZHI, A_RORX, A_SARX, A_SHLX, A_SHRX:
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+ Result:=1;
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+
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+ A_MOVD,
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+ A_MOVQ,
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+ A_VMOVD,
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+ A_VMOVQ:
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+ if (hp.oper[0]^.typ = top_reg) and
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+ (getregtype(hp.oper[0]^.reg) = R_INTREGISTER) then
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+ Result:=0
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+ else
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+ Result:=-1;
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+
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+ A_DIV,
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+ A_IDIV:
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+ if (taicpu(p).oper[0]^.typ=top_reg) and
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+ (
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+ (getsupreg(taicpu(p).oper[0]^.reg)=RS_EAX) or { EAX is also used implicitly; don't change }
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+ (
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+ (hp.opsize<>S_B) and
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+ (getsupreg(taicpu(p).oper[0]^.reg)=RS_EDX) { EDX is also used implicitly; don't change }
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+ )
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+ ) then
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+ Result:=-1
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+ else
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+ Result:=0;
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+
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+ A_MUL:
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+ if (taicpu(p).oper[0]^.typ=top_reg) and (getsupreg(taicpu(p).oper[0]^.reg)=RS_EAX) then
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+ Result:=-1 { EAX is also used implicitly; don't change }
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+ else
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+ Result:=0;
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+
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+ A_IMUL:
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+ case hp.ops of
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+ 3:
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+ Result:=1;
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+ 2:
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+ Result:=0;
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+ else
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+ if (taicpu(p).oper[0]^.typ=top_reg) and (getsupreg(taicpu(p).oper[0]^.reg)=RS_EAX) then
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+ Result:=-1 { EAX is also used implicitly; don't change }
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+ else
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+ Result:=0;
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+ end;
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+
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+ else
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+ Result:=-1;
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+ end;
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+ end;
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+
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+
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function TX86AsmOptimizer.ConvertLEA(const p: taicpu): Boolean;
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var
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l: asizeint;
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@@ -3268,6 +3380,7 @@ unit aoptx86;
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SourceRef, TargetRef: TReference;
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MovAligned, MovUnaligned: TAsmOp;
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JumpTracking: TLinkedList;
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+ op_idx: integer;
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begin
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Result:=false;
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@@ -3989,17 +4102,43 @@ unit aoptx86;
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<op> ref,reg1
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}
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- if MatchOpType(taicpu(hp1),top_reg,top_reg) and
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- (taicpu(hp1).oper[0]^.reg = p_TargetReg) and
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- MatchInstruction(hp1, [A_AND, A_OR, A_XOR, A_ADD, A_SUB, A_CMP, A_TEST, A_CMOVcc, A_BSR, A_BSF, A_POPCNT, A_LZCNT], [taicpu(p).opsize]) and
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- not SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, p_TargetReg) and
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+ op_idx := -1; { Needed to prevent compiler warnings }
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+ if (SetAndPassThrough(GetRMReadIndex(hp1),op_idx)<>-1) and
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+ (taicpu(hp1).oper[op_idx]^.reg = p_TargetReg) and
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not RefModifiedBetween(taicpu(p).oper[0]^.ref^, topsize2memsize[taicpu(p).opsize] shr 3, p, hp1) then
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begin
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegsBetween(TmpUsedRegs, tai(p.Next), hp1);
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- if not RegUsedAfterInstruction(p_TargetReg, hp1, TmpUsedRegs) then
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+
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+ DoOptimisation := True;
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+ if RegUsedAfterInstruction(p_TargetReg, hp1, TmpUsedRegs) then
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begin
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- taicpu(hp1).loadref(0,taicpu(p).oper[0]^.ref^);
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+ { We may still be able to perform the optimisation if we're careful }
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+
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+ { A trick so RegLoadedWithNewValue will not return False
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+ if p_TargetReg is read from or appears in the reference }
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+ taicpu(hp1).loadreg(op_idx,NR_NO);
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+
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegsBetween(TmpUsedRegs, tai(p.Next), hp1);
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+
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+ { Note, RegReadByInstruction is indirectly called by
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+ RegUsedAfterInstruction and will return True if
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+ another operand reads from p_TargetReg or is read
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+ from implicitly, so RegLoadedWithNewValue will
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+ return False in this situation, and hence
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+ RegUsedAfterInstruction will return True }
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+ if RegUsedAfterInstruction(p_TargetReg, hp1, TmpUsedRegs) then
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+ begin
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+ { Abort }
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+ taicpu(hp1).loadreg(op_idx,p_TargetReg);
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+ DoOptimisation := False;
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+ end;
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+ end;
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+
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+ if DoOptimisation then
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+ begin
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+ taicpu(hp1).loadref(op_idx,taicpu(p).oper[0]^.ref^);
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{ loadref increases the reference count, so decrement it again }
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if Assigned(taicpu(p).oper[0]^.ref^.symbol) then
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@@ -4013,6 +4152,14 @@ unit aoptx86;
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if not RegInRef(p_TargetReg, taicpu(p).oper[0]^.ref^) then
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TryRemoveRegAlloc(p_TargetReg, p, hp1);
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+ { Update the register tracking for the registers inside the reference }
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+ if (taicpu(p).oper[0]^.ref^.base<>NR_NO) then
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+ AllocRegBetween(taicpu(p).oper[0]^.ref^.base, p, hp1, UsedRegs);
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+
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+ if (taicpu(p).oper[0]^.ref^.index<>NR_NO) and
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+ (taicpu(p).oper[0]^.ref^.index<>taicpu(p).oper[0]^.ref^.base) then
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+ AllocRegBetween(taicpu(p).oper[0]^.ref^.index, p, hp1, UsedRegs);
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+
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RemoveCurrentp(p);
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Result:=true;
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exit;
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J. Gareth "Curious Kit" Moreton