* fixed tinterlockedmt*.pp for architectures with weak memory consistency

    models

git-svn-id: trunk@41164 -

tests/test/tinterlocked64mt.pp

@@ -208,6 +208,8 @@ begin
       end;
   end;
 
+  { ensure the writes to Counter and Counter2 are ordered vs the writes to FinishedCount }
+  WriteBarrier;
   InterLockedIncrement64(FinishedCount);
 end;
 
@@ -293,6 +295,10 @@ begin
   if t = 0 then
     t:=1/MSecsPerDay;
 
+  { ensure the read from FinishedCount above is ordered relative to the reads from
+    Counter and Counter2 (counterpart to WriteBarrier in the thread function) }
+  ReadBarrier();
+
   CheckResult(Counter, 0, 20, 'Counter error:');
 
   CheckResult(Counter2, (LastCompareVal - 2)*CmpCount, 21, 'Counter2 error:');

tests/test/tinterlockedmt.pp

@@ -204,6 +204,9 @@ begin
       end;
   end;
 
+  { ensure the writes to Counter and Counter2 are ordered vs the writes to FinishedCount }
+  WriteBarrier;
+
   InterLockedIncrement(FinishedCount);
 end;
 
@@ -288,6 +291,10 @@ begin
   if t = 0 then
     t:=1/MSecsPerDay;
 
+  { ensure the read from FinishedCount above is ordered relative to the reads from
+    Counter and Counter2 (counterpart to WriteBarrier in the thread function) }
+  ReadBarrier();
+
   CheckResult(Counter, 0, 20, 'Counter error:');
 
   CheckResult(Counter2, (LastCompareVal - 2)*CmpCount, 21, 'Counter2 error:');