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@@ -0,0 +1,579 @@
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+{
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+Register definitions and utility code for STM32F429
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+
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+Created by Jeppe Johansen 2015 - [email protected]
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+}
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+unit stm32f429;
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+
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+{$goto on}
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+
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+interface
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+
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+{$PACKRECORDS 2}
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+const
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+ PeripheralBase = $40000000;
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+
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+ FSMC_Base = $A0000000;
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+ RNG_Base = $50060800;
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+ HASH_Base = $50060400;
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+ CRYP_Base = $50060000;
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+ DCMI_Base = $50050000;
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+ USB_OTG_FS_Base = $50000000;
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+ USB_OTG_HS_Base = $40040000;
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+ DMA2D_Base = $4002B000;
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+ ETHERNET_Base = $40026400;
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+ DMA2_Base = $40026400;
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+ DMA1_Base = $40026000;
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+ BKPSRAM_Base = $40024000;
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+ FLASH_Base = $40023C00;
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+ RCC_Base = $40023800;
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+ CRC_Base = $40023000;
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+ GPIOK_Base = $40022800;
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+ GPIOJ_Base = $40022400;
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+ GPIOI_Base = $40022000;
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+ GPIOH_Base = $40021C00;
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+ GPIOG_Base = $40021800;
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+ GPIOF_Base = $40021400;
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+ GPIOE_Base = $40021000;
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+ GPIOD_Base = $40020C00;
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+ GPIOC_Base = $40020800;
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+ GPIOB_Base = $40020400;
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+ GPIOA_Base = $40020000;
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+ LCD_TFT_Base = $40016800;
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+ SAI1_Base = $40015800;
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+ SPI6_Base = $40015400;
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+ SPI5_Base = $40015000;
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+ TIM11_Base = $40014800;
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+ TIM10_Base = $40014400;
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+ TIM9_Base = $40014000;
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+ EXTI_Base = $40013C00;
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+ SYSCFG_Base = $40013800;
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+ SPI4_Base = $40013400;
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+ SPI1_Base = $40013000;
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+ SDIO_Base = $40012C00;
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+ ADC_Base = $40012000;
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+ USART6_Base = $40011600;
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+ USART1_Base = $40011000;
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+ TIM8_Base = $40010400;
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+ TIM1_Base = $40010000;
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+ UART8_Base = $40007C00;
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+ UART7_Base = $40007800;
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+ DAC_Base = $40007400;
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+ PWR_Base = $40007000;
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+ CAN2_Base = $40006800;
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+ CAN1_Base = $40006400;
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+ I2C3_Base = $40005C00;
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+ I2C2_Base = $40005800;
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+ I2C1_Base = $40005400;
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+ UART5_Base = $40005000;
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+ UART4_Base = $40004C00;
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+ USART3_Base = $40004800;
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+ USART2_Base = $40004400;
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+ I2S3ext_Base = $40004000;
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+ SPI3_Base = $40003C00;
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+ SPI2_Base = $40003800;
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+ I2S2ext_Base = $40003400;
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+ IWDG_Base = $40003000;
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+ WWDG_Base = $40002C00;
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+ RTC_Base = $40002800;
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+ TIM14_Base = $40002000;
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+ TIM13_Base = $40001C00;
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+ TIM12_Base = $40001800;
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+ TIM7_Base = $40001400;
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+ TIM6_Base = $40001000;
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+ TIM5_Base = $40000C00;
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+ TIM4_Base = $40000800;
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+ TIM3_Base = $40000400;
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+ TIM2_Base = $40000000;
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+
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+type
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+ TPortRegisters = record
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+ MODER,
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+ OTYPER,
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+ OSPEEDER,
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+ PUPDR,
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+ IDR,
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+ ODR,
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+ BSRR,
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+ LCKR,
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+ AFRL,
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+ AFRH: longword;
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+ end;
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+
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+ TRCCRegister = record
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+ CR,
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+ PLLCFGR,
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+ CFGR,
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+ CIR,
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+ AHB1RSTR,
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+ AHB2RSTR,
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+ AHB3RSTR,
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+ _res0,
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+ APB1RSTR,
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+ APB2RSTR,
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+ _res1,_res2,
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+ AHB1ENR,
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+ AHB2ENR,
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+ AHB3ENR,
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+ _res3,
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+ APB1ENR,
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+ APB2ENR,
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+ _res4,_res5,
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+ AHB1LPENR,
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+ AHB2LPENR,
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+ AHB3LPENR,
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+ _res6,
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+ APB1LPENR,
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+ APB2LPENR,
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+ _res7,_res8,
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+ BDCR,
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+ CSR,
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+ _res9,_res10,
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+ SSCGR,
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+ PLLI2SCFGR,
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+ PLLSAICFGR,
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+ DCKCFGR: longword;
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+ end;
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+
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+ TPWRRegisters = record
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+ CR,
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+ CSR: longword;
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+ end;
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+
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+{$ALIGN 2}
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+var
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+ { GPIO }
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+ PortA: TPortRegisters absolute GPIOA_Base;
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+ PortB: TPortRegisters absolute GPIOB_Base;
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+ PortC: TPortRegisters absolute GPIOC_Base;
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+ PortD: TPortRegisters absolute GPIOD_Base;
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+ PortE: TPortRegisters absolute GPIOE_Base;
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+ PortF: TPortRegisters absolute GPIOF_Base;
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+ PortG: TPortRegisters absolute GPIOG_Base;
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+ PortH: TPortRegisters absolute GPIOH_Base;
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+ PortI: TPortRegisters absolute GPIOI_Base;
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+ PortJ: TPortRegisters absolute GPIOJ_Base;
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+ PortK: TPortRegisters absolute GPIOK_Base;
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+
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+ { RCC }
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+ RCC: TRCCRegister absolute RCC_Base;
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+
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+ { PWR }
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+ PWR: TPWRRegisters absolute PWR_Base;
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+
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+implementation
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+
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+procedure NMI_interrupt; external name 'NMI_interrupt';
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+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
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+procedure MemManage_interrupt; external name 'MemManage_interrupt';
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+procedure BusFault_interrupt; external name 'BusFault_interrupt';
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+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
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+procedure SWI_interrupt; external name 'SWI_interrupt';
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+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
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+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
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+procedure SysTick_interrupt; external name 'SysTick_interrupt';
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+
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+procedure WWDG_interrupt; external name 'WWDG_interrupt';
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+procedure PVD_interrupt; external name 'PVD_interrupt';
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+procedure TAMP_STAMP_interrupt; external name 'TAMP_STAMP_interrupt';
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+procedure RTC_WKUP_interrupt; external name 'RTC_WKUP_interrupt';
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+procedure FLASH_interrupt; external name 'FLASH_interrupt';
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+procedure RCC_interrupt; external name 'RCC_interrupt';
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+procedure EXTI0_interrupt; external name 'EXTI0_interrupt';
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+procedure EXTI1_interrupt; external name 'EXTI1_interrupt';
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+procedure EXTI2_interrupt; external name 'EXTI2_interrupt';
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+procedure EXTI3_interrupt; external name 'EXTI3_interrupt';
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+procedure EXTI4_interrupt; external name 'EXTI4_interrupt';
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+procedure DMA1_Channel0_interrupt; external name 'DMA1_Channel0_interrupt';
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+procedure DMA1_Channel1_interrupt; external name 'DMA1_Channel1_interrupt';
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+procedure DMA1_Channel2_interrupt; external name 'DMA1_Channel2_interrupt';
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+procedure DMA1_Channel3_interrupt; external name 'DMA1_Channel3_interrupt';
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+procedure DMA1_Channel4_interrupt; external name 'DMA1_Channel4_interrupt';
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+procedure DMA1_Channel5_interrupt; external name 'DMA1_Channel5_interrupt';
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+procedure DMA1_Channel6_interrupt; external name 'DMA1_Channel6_interrupt';
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+procedure ADC1_2_3_interrupt; external name 'ADC1_2_3_interrupt';
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+procedure CAN1_TX_interrupt; external name 'CAN1_TX_interrupt';
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+procedure CAN1_RX0_interrupt; external name 'CAN1_RX0_interrupt';
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+procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt';
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+procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt';
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+procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt';
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+procedure TIM1_BRK_TIM9_interrupt; external name 'TIM1_BRK_TIM9_interrupt';
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+procedure TIM1_UP_TIM10_interrupt; external name 'TIM1_UP_TIM10_interrupt';
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+procedure TIM1_TRG_COM_TIM11_interruptirq; external name 'TIM1_TRG_COM_TIM11_interruptirq';
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+procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
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+procedure TIM2_interrupt; external name 'TIM2_interrupt';
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+procedure TIM3_interrupt; external name 'TIM3_interrupt';
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+procedure TIM4_interrupt; external name 'TIM4_interrupt';
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+procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt';
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+procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt';
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+procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt';
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+procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt';
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+procedure SPI1_interrupt; external name 'SPI1_interrupt';
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+procedure SPI2_interrupt; external name 'SPI2_interrupt';
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+procedure USART1_interrupt; external name 'USART1_interrupt';
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+procedure USART2_interrupt; external name 'USART2_interrupt';
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+procedure USART3_interrupt; external name 'USART3_interrupt';
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+procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt';
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+procedure RTCAlarm_interrupt; external name 'RTCAlarm_interrupt';
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+procedure OTG_FS_WKUP_interrupt; external name 'OTG_FS_WKUP_interrupt';
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+procedure TIM8_BRK_TIM12_interrupt; external name 'TIM8_BRK_TIM12_interrupt';
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+procedure TIM8_UP_TIM13_interrupt; external name 'TIM8_UP_TIM13_interrupt';
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+procedure TIM8_TRG_COM_TIM14_interrupt; external name 'TIM8_TRG_COM_TIM14_interrupt';
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+procedure TIM8_CC_interrupt; external name 'TIM8_CC_interrupt';
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+procedure DMA1_Stream7_interrupt; external name 'DMA1_Stream7_interrupt';
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+procedure FSMC_interrupt; external name 'FSMC_interrupt';
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+procedure SDIO_interrupt; external name 'SDIO_interrupt';
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+procedure TIM5_interrupt; external name 'TIM5_interrupt';
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+procedure SPI3_interrupt; external name 'SPI3_interrupt';
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+procedure UART4_interrupt; external name 'UART4_interrupt';
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+procedure UART5_interrupt; external name 'UART5_interrupt';
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+procedure TIM6_DAC1_2_interrupt; external name 'TIM6_DAC1_2_interrupt';
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+procedure TIM7_interrupt; external name 'TIM7_interrupt';
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+procedure DMA2_Stream0_interrupt; external name 'DMA2_Stream0_interrupt';
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+procedure DMA2_Stream1_interrupt; external name 'DMA2_Stream1_interrupt';
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+procedure DMA2_Stream2_interrupt; external name 'DMA2_Stream2_interrupt';
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+procedure DMA2_Stream3_interrupt; external name 'DMA2_Stream3_interrupt';
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+procedure DMA2_Stream4_interrupt; external name 'DMA2_Stream4_interrupt';
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+procedure ETH_interrupt; external name 'ETH_interrupt';
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+procedure ETHWKUP_interrupt; external name 'ETHWKUP_interrupt';
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+procedure CAN2_TX_interrupt; external name 'CAN2_TX_interrupt';
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+procedure CAN2_RX0_interrupt; external name 'CAN2_RX0_interrupt';
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+procedure CAN2_RX1_interrupt; external name 'CAN2_RX1_interrupt';
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+procedure CAN2_SCE_interrupt; external name 'CAN2_SCE_interrupt';
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+procedure OTG_FS_interrupt; external name 'OTG_FS_interrupt';
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+procedure DMA2_Stream5_interrupt; external name 'DMA2_Stream5_interrupt';
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+procedure DMA2_Stream6_interrupt; external name 'DMA2_Stream6_interrupt';
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+procedure DMA2_Stream7_interrupt; external name 'DMA2_Stream7_interrupt';
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+procedure USART6_interrupt; external name 'USART6_interrupt';
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+procedure I2C3_EV_interrupt; external name 'I2C3_EV_interrupt';
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+procedure I2C3_ER_interrupt; external name 'I2C3_ER_interrupt';
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+procedure OTG_HS_EP1_OUT_interrupt; external name 'OTG_HS_EP1_OUT_interrupt';
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+procedure OTG_HS_EP1_IN_interrupt; external name 'OTG_HS_EP1_IN_interrupt';
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+procedure OTG_HS_WKUP_interrupt; external name 'OTG_HS_WKUP_interrupt';
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+procedure OTG_HS_interrupt; external name 'OTG_HS_interrupt';
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+procedure DCMI_interrupt; external name 'DCMI_interrupt';
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+procedure CRYP_interrupt; external name 'CRYP_interrupt';
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+procedure HASH_RNG_interrupt; external name 'HASH_RNG_interrupt';
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+procedure FPU_interrupt; external name 'FPU_interrupt';
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+procedure UART7_interrupt; external name 'UART7_interrupt';
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+procedure UART8_interrupt; external name 'UART8_interrupt';
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+procedure SPI4_interrupt; external name 'SPI4_interrupt';
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+procedure LTDC_interrupt; external name 'LTDC_interrupt';
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+procedure LTDC_ERR_interrupt; external name 'LTDC_ERR_interrupt';
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+procedure DMA2D_interrupt; external name 'DMA2D_interrupt';
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+
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+{$i cortexm4f_start.inc}
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+
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+procedure Vectors; assembler; nostackframe;
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+label interrupt_vectors;
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+asm
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+ .section ".init.interrupt_vectors"
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+interrupt_vectors:
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+ .long _stack_top
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+ .long Startup
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+ .long NMI_interrupt
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+ .long Hardfault_interrupt
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+ .long MemManage_interrupt
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+ .long BusFault_interrupt
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+ .long UsageFault_interrupt
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+ .long 0
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+ .long 0
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+ .long 0
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+ .long 0
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+ .long SWI_interrupt
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+ .long DebugMonitor_interrupt
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+ .long 0
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+ .long PendingSV_interrupt
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+ .long SysTick_interrupt
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+
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+ .long WWDG_interrupt
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+ .long PVD_interrupt
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+ .long TAMP_STAMP_interrupt
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+ .long RTC_WKUP_interrupt
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+ .long FLASH_interrupt
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+ .long RCC_interrupt
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+ .long EXTI0_interrupt
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+ .long EXTI1_interrupt
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+ .long EXTI2_interrupt
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+ .long EXTI3_interrupt
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+ .long EXTI4_interrupt
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+ .long DMA1_Channel0_interrupt
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+ .long DMA1_Channel1_interrupt
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+ .long DMA1_Channel2_interrupt
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+ .long DMA1_Channel3_interrupt
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+ .long DMA1_Channel4_interrupt
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+ .long DMA1_Channel5_interrupt
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+ .long DMA1_Channel6_interrupt
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+ .long ADC1_2_3_interrupt
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+ .long CAN1_TX_interrupt
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+ .long CAN1_RX0_interrupt
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+ .long CAN1_RX1_interrupt
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+ .long CAN1_SCE_interrupt
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+ .long EXTI9_5_interrupt
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+ .long TIM1_BRK_TIM9_interrupt
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+ .long TIM1_UP_TIM10_interrupt
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+ .long TIM1_TRG_COM_TIM11_interruptirq
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+ .long TIM1_CC_interrupt
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+ .long TIM2_interrupt
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+ .long TIM3_interrupt
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+ .long TIM4_interrupt
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+ .long I2C1_EV_interrupt
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+ .long I2C1_ER_interrupt
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+ .long I2C2_EV_interrupt
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+ .long I2C2_ER_interrupt
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+ .long SPI1_interrupt
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+ .long SPI2_interrupt
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+ .long USART1_interrupt
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+ .long USART2_interrupt
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+ .long USART3_interrupt
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+ .long EXTI15_10_interrupt
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+ .long RTCAlarm_interrupt
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+ .long OTG_FS_WKUP_interrupt
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+ .long TIM8_BRK_TIM12_interrupt
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+ .long TIM8_UP_TIM13_interrupt
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+ .long TIM8_TRG_COM_TIM14_interrupt
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+ .long TIM8_CC_interrupt
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+ .long DMA1_Stream7_interrupt
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+ .long FSMC_interrupt
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+ .long SDIO_interrupt
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+ .long TIM5_interrupt
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+ .long SPI3_interrupt
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+ .long UART4_interrupt
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+ .long UART5_interrupt
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+ .long TIM6_DAC1_2_interrupt
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+ .long TIM7_interrupt
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+ .long DMA2_Stream0_interrupt
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+ .long DMA2_Stream1_interrupt
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+ .long DMA2_Stream2_interrupt
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+ .long DMA2_Stream3_interrupt
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+ .long DMA2_Stream4_interrupt
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+ .long ETH_interrupt
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+ .long ETHWKUP_interrupt
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+ .long CAN2_TX_interrupt
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+ .long CAN2_RX0_interrupt
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+ .long CAN2_RX1_interrupt
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+ .long CAN2_SCE_interrupt
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+ .long OTG_FS_interrupt
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+ .long DMA2_Stream5_interrupt
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+ .long DMA2_Stream6_interrupt
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+ .long DMA2_Stream7_interrupt
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+ .long USART6_interrupt
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+ .long I2C3_EV_interrupt
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+ .long I2C3_ER_interrupt
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+ .long OTG_HS_EP1_OUT_interrupt
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+ .long OTG_HS_EP1_IN_interrupt
|
|
|
+ .long OTG_HS_WKUP_interrupt
|
|
|
+ .long OTG_HS_interrupt
|
|
|
+ .long DCMI_interrupt
|
|
|
+ .long CRYP_interrupt
|
|
|
+ .long HASH_RNG_interrupt
|
|
|
+ .long FPU_interrupt
|
|
|
+ .long UART7_interrupt
|
|
|
+ .long UART8_interrupt
|
|
|
+ .long SPI4_interrupt
|
|
|
+ .long LTDC_interrupt
|
|
|
+ .long LTDC_ERR_interrupt
|
|
|
+ .long DMA2D_interrupt
|
|
|
+
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|
|
+ .weak NMI_interrupt
|
|
|
+ .weak Hardfault_interrupt
|
|
|
+ .weak MemManage_interrupt
|
|
|
+ .weak BusFault_interrupt
|
|
|
+ .weak UsageFault_interrupt
|
|
|
+ .weak SWI_interrupt
|
|
|
+ .weak DebugMonitor_interrupt
|
|
|
+ .weak PendingSV_interrupt
|
|
|
+ .weak SysTick_interrupt
|
|
|
+
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|
|
+ .weak WWDG_interrupt
|
|
|
+ .weak PVD_interrupt
|
|
|
+ .weak TAMP_STAMP_interrupt
|
|
|
+ .weak RTC_WKUP_interrupt
|
|
|
+ .weak FLASH_interrupt
|
|
|
+ .weak RCC_interrupt
|
|
|
+ .weak EXTI0_interrupt
|
|
|
+ .weak EXTI1_interrupt
|
|
|
+ .weak EXTI2_interrupt
|
|
|
+ .weak EXTI3_interrupt
|
|
|
+ .weak EXTI4_interrupt
|
|
|
+ .weak DMA1_Channel0_interrupt
|
|
|
+ .weak DMA1_Channel1_interrupt
|
|
|
+ .weak DMA1_Channel2_interrupt
|
|
|
+ .weak DMA1_Channel3_interrupt
|
|
|
+ .weak DMA1_Channel4_interrupt
|
|
|
+ .weak DMA1_Channel5_interrupt
|
|
|
+ .weak DMA1_Channel6_interrupt
|
|
|
+ .weak ADC1_2_3_interrupt
|
|
|
+ .weak CAN1_TX_interrupt
|
|
|
+ .weak CAN1_RX0_interrupt
|
|
|
+ .weak CAN1_RX1_interrupt
|
|
|
+ .weak CAN1_SCE_interrupt
|
|
|
+ .weak EXTI9_5_interrupt
|
|
|
+ .weak TIM1_BRK_TIM9_interrupt
|
|
|
+ .weak TIM1_UP_TIM10_interrupt
|
|
|
+ .weak TIM1_TRG_COM_TIM11_interruptirq
|
|
|
+ .weak TIM1_CC_interrupt
|
|
|
+ .weak TIM2_interrupt
|
|
|
+ .weak TIM3_interrupt
|
|
|
+ .weak TIM4_interrupt
|
|
|
+ .weak I2C1_EV_interrupt
|
|
|
+ .weak I2C1_ER_interrupt
|
|
|
+ .weak I2C2_EV_interrupt
|
|
|
+ .weak I2C2_ER_interrupt
|
|
|
+ .weak SPI1_interrupt
|
|
|
+ .weak SPI2_interrupt
|
|
|
+ .weak USART1_interrupt
|
|
|
+ .weak USART2_interrupt
|
|
|
+ .weak USART3_interrupt
|
|
|
+ .weak EXTI15_10_interrupt
|
|
|
+ .weak RTCAlarm_interrupt
|
|
|
+ .weak OTG_FS_WKUP_interrupt
|
|
|
+ .weak TIM8_BRK_TIM12_interrupt
|
|
|
+ .weak TIM8_UP_TIM13_interrupt
|
|
|
+ .weak TIM8_TRG_COM_TIM14_interrupt
|
|
|
+ .weak TIM8_CC_interrupt
|
|
|
+ .weak DMA1_Stream7_interrupt
|
|
|
+ .weak FSMC_interrupt
|
|
|
+ .weak SDIO_interrupt
|
|
|
+ .weak TIM5_interrupt
|
|
|
+ .weak SPI3_interrupt
|
|
|
+ .weak UART4_interrupt
|
|
|
+ .weak UART5_interrupt
|
|
|
+ .weak TIM6_DAC1_2_interrupt
|
|
|
+ .weak TIM7_interrupt
|
|
|
+ .weak DMA2_Stream0_interrupt
|
|
|
+ .weak DMA2_Stream1_interrupt
|
|
|
+ .weak DMA2_Stream2_interrupt
|
|
|
+ .weak DMA2_Stream3_interrupt
|
|
|
+ .weak DMA2_Stream4_interrupt
|
|
|
+ .weak ETH_interrupt
|
|
|
+ .weak ETHWKUP_interrupt
|
|
|
+ .weak CAN2_TX_interrupt
|
|
|
+ .weak CAN2_RX0_interrupt
|
|
|
+ .weak CAN2_RX1_interrupt
|
|
|
+ .weak CAN2_SCE_interrupt
|
|
|
+ .weak OTG_FS_interrupt
|
|
|
+ .weak DMA2_Stream5_interrupt
|
|
|
+ .weak DMA2_Stream6_interrupt
|
|
|
+ .weak DMA2_Stream7_interrupt
|
|
|
+ .weak USART6_interrupt
|
|
|
+ .weak I2C3_EV_interrupt
|
|
|
+ .weak I2C3_ER_interrupt
|
|
|
+ .weak OTG_HS_EP1_OUT_interrupt
|
|
|
+ .weak OTG_HS_EP1_IN_interrupt
|
|
|
+ .weak OTG_HS_WKUP_interrupt
|
|
|
+ .weak OTG_HS_interrupt
|
|
|
+ .weak DCMI_interrupt
|
|
|
+ .weak CRYP_interrupt
|
|
|
+ .weak HASH_RNG_interrupt
|
|
|
+ .weak FPU_interrupt
|
|
|
+ .weak UART7_interrupt
|
|
|
+ .weak UART8_interrupt
|
|
|
+ .weak SPI4_interrupt
|
|
|
+ .weak LTDC_interrupt
|
|
|
+ .weak LTDC_ERR_interrupt
|
|
|
+ .weak DMA2D_interrupt
|
|
|
+
|
|
|
+ .set NMI_interrupt, HaltProc
|
|
|
+ .set Hardfault_interrupt, HaltProc
|
|
|
+ .set MemManage_interrupt, HaltProc
|
|
|
+ .set BusFault_interrupt, HaltProc
|
|
|
+ .set UsageFault_interrupt, HaltProc
|
|
|
+ .set SWI_interrupt, HaltProc
|
|
|
+ .set DebugMonitor_interrupt, HaltProc
|
|
|
+ .set PendingSV_interrupt, HaltProc
|
|
|
+ .set SysTick_interrupt, HaltProc
|
|
|
+
|
|
|
+ .set WWDG_interrupt, HaltProc
|
|
|
+ .set PVD_interrupt, HaltProc
|
|
|
+ .set TAMP_STAMP_interrupt, HaltProc
|
|
|
+ .set RTC_WKUP_interrupt, HaltProc
|
|
|
+ .set FLASH_interrupt, HaltProc
|
|
|
+ .set RCC_interrupt, HaltProc
|
|
|
+ .set EXTI0_interrupt, HaltProc
|
|
|
+ .set EXTI1_interrupt, HaltProc
|
|
|
+ .set EXTI2_interrupt, HaltProc
|
|
|
+ .set EXTI3_interrupt, HaltProc
|
|
|
+ .set EXTI4_interrupt, HaltProc
|
|
|
+ .set DMA1_Channel0_interrupt, HaltProc
|
|
|
+ .set DMA1_Channel1_interrupt, HaltProc
|
|
|
+ .set DMA1_Channel2_interrupt, HaltProc
|
|
|
+ .set DMA1_Channel3_interrupt, HaltProc
|
|
|
+ .set DMA1_Channel4_interrupt, HaltProc
|
|
|
+ .set DMA1_Channel5_interrupt, HaltProc
|
|
|
+ .set DMA1_Channel6_interrupt, HaltProc
|
|
|
+ .set ADC1_2_3_interrupt, HaltProc
|
|
|
+ .set CAN1_TX_interrupt, HaltProc
|
|
|
+ .set CAN1_RX0_interrupt, HaltProc
|
|
|
+ .set CAN1_RX1_interrupt, HaltProc
|
|
|
+ .set CAN1_SCE_interrupt, HaltProc
|
|
|
+ .set EXTI9_5_interrupt, HaltProc
|
|
|
+ .set TIM1_BRK_TIM9_interrupt, HaltProc
|
|
|
+ .set TIM1_UP_TIM10_interrupt, HaltProc
|
|
|
+ .set TIM1_TRG_COM_TIM11_interruptirq, HaltProc
|
|
|
+ .set TIM1_CC_interrupt, HaltProc
|
|
|
+ .set TIM2_interrupt, HaltProc
|
|
|
+ .set TIM3_interrupt, HaltProc
|
|
|
+ .set TIM4_interrupt, HaltProc
|
|
|
+ .set I2C1_EV_interrupt, HaltProc
|
|
|
+ .set I2C1_ER_interrupt, HaltProc
|
|
|
+ .set I2C2_EV_interrupt, HaltProc
|
|
|
+ .set I2C2_ER_interrupt, HaltProc
|
|
|
+ .set SPI1_interrupt, HaltProc
|
|
|
+ .set SPI2_interrupt, HaltProc
|
|
|
+ .set USART1_interrupt, HaltProc
|
|
|
+ .set USART2_interrupt, HaltProc
|
|
|
+ .set USART3_interrupt, HaltProc
|
|
|
+ .set EXTI15_10_interrupt, HaltProc
|
|
|
+ .set RTCAlarm_interrupt, HaltProc
|
|
|
+ .set OTG_FS_WKUP_interrupt, HaltProc
|
|
|
+ .set TIM8_BRK_TIM12_interrupt, HaltProc
|
|
|
+ .set TIM8_UP_TIM13_interrupt, HaltProc
|
|
|
+ .set TIM8_TRG_COM_TIM14_interrupt, HaltProc
|
|
|
+ .set TIM8_CC_interrupt, HaltProc
|
|
|
+ .set DMA1_Stream7_interrupt, HaltProc
|
|
|
+ .set FSMC_interrupt, HaltProc
|
|
|
+ .set SDIO_interrupt, HaltProc
|
|
|
+ .set TIM5_interrupt, HaltProc
|
|
|
+ .set SPI3_interrupt, HaltProc
|
|
|
+ .set UART4_interrupt, HaltProc
|
|
|
+ .set UART5_interrupt, HaltProc
|
|
|
+ .set TIM6_DAC1_2_interrupt, HaltProc
|
|
|
+ .set TIM7_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream0_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream1_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream2_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream3_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream4_interrupt, HaltProc
|
|
|
+ .set ETH_interrupt, HaltProc
|
|
|
+ .set ETHWKUP_interrupt, HaltProc
|
|
|
+ .set CAN2_TX_interrupt, HaltProc
|
|
|
+ .set CAN2_RX0_interrupt, HaltProc
|
|
|
+ .set CAN2_RX1_interrupt, HaltProc
|
|
|
+ .set CAN2_SCE_interrupt, HaltProc
|
|
|
+ .set OTG_FS_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream5_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream6_interrupt, HaltProc
|
|
|
+ .set DMA2_Stream7_interrupt, HaltProc
|
|
|
+ .set USART6_interrupt, HaltProc
|
|
|
+ .set I2C3_EV_interrupt, HaltProc
|
|
|
+ .set I2C3_ER_interrupt, HaltProc
|
|
|
+ .set OTG_HS_EP1_OUT_interrupt, HaltProc
|
|
|
+ .set OTG_HS_EP1_IN_interrupt, HaltProc
|
|
|
+ .set OTG_HS_WKUP_interrupt, HaltProc
|
|
|
+ .set OTG_HS_interrupt, HaltProc
|
|
|
+ .set DCMI_interrupt, HaltProc
|
|
|
+ .set CRYP_interrupt, HaltProc
|
|
|
+ .set HASH_RNG_interrupt, HaltProc
|
|
|
+ .set FPU_interrupt, HaltProc
|
|
|
+ .set UART7_interrupt, HaltProc
|
|
|
+ .set UART8_interrupt, HaltProc
|
|
|
+ .set SPI4_interrupt, HaltProc
|
|
|
+ .set LTDC_interrupt, HaltProc
|
|
|
+ .set LTDC_ERR_interrupt, HaltProc
|
|
|
+ .set DMA2D_interrupt, HaltProc
|
|
|
+
|
|
|
+ .text
|
|
|
+end;
|
|
|
+
|
|
|
+end.
|
Jeppe Johansen