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@@ -99,8 +99,6 @@ type
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procedure g_concatcopy(list: TAsmList; const source, dest: treference;
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procedure g_concatcopy(list: TAsmList; const source, dest: treference;
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len: aint); override;
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len: aint); override;
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- procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const
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- labelname: string; ioffset: longint); override;
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private
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private
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procedure a_load_regconst_subsetreg_intern(list : TAsmList; fromsize, subsetsize: tcgsize; fromreg: tregister; const sreg: tsubsetregister; slopt: tsubsetloadopt); override;
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procedure a_load_regconst_subsetreg_intern(list : TAsmList; fromsize, subsetsize: tcgsize; fromreg: tregister; const sreg: tsubsetregister; slopt: tsubsetloadopt); override;
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@@ -132,10 +130,6 @@ type
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for the current procedure }
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for the current procedure }
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procedure calcFirstUsedGPR(out firstgpr : TSuperRegister; out gprcount : aint);
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procedure calcFirstUsedGPR(out firstgpr : TSuperRegister; out gprcount : aint);
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- { returns true if the offset of the given reference can not be represented by a 16 bit
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- immediate as required by some PowerPC instructions }
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- function hasLargeOffset(const ref : TReference) : Boolean; inline;
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-
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{ generates code to call a method with the given string name. The boolean options
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{ generates code to call a method with the given string name. The boolean options
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control code generation. If prependDot is true, a single dot character is prepended to
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control code generation. If prependDot is true, a single dot character is prepended to
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the string, if addNOP is true a single NOP instruction is added after the call, and
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the string, if addNOP is true a single NOP instruction is added after the call, and
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@@ -177,7 +171,7 @@ end;
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function cgsize2string(const size : TCgSize) : string;
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function cgsize2string(const size : TCgSize) : string;
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const
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const
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- cgsize_strings : array[TCgSize] of string[7] = (
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+ cgsize_strings : array[TCgSize] of string[8] = (
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'OS_NO', 'OS_8', 'OS_16', 'OS_32', 'OS_64', 'OS_128', 'OS_S8', 'OS_S16', 'OS_S32',
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'OS_NO', 'OS_8', 'OS_16', 'OS_32', 'OS_64', 'OS_128', 'OS_S8', 'OS_S16', 'OS_S32',
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'OS_S64', 'OS_S128', 'OS_F32', 'OS_F64', 'OS_F80', 'OS_C64', 'OS_F128',
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'OS_S64', 'OS_S128', 'OS_F32', 'OS_F64', 'OS_F80', 'OS_C64', 'OS_F128',
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'OS_M8', 'OS_M16', 'OS_M32', 'OS_M64', 'OS_M128', 'OS_MS8', 'OS_MS16', 'OS_MS32',
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'OS_M8', 'OS_M16', 'OS_M32', 'OS_M64', 'OS_M128', 'OS_MS8', 'OS_MS16', 'OS_MS32',
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@@ -400,12 +394,22 @@ end;
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procedure tcgppc.init_register_allocators;
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procedure tcgppc.init_register_allocators;
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begin
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begin
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inherited init_register_allocators;
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inherited init_register_allocators;
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- rg[R_INTREGISTER] := trgcpu.create(R_INTREGISTER, R_SUBWHOLE,
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- [RS_R3, RS_R4, RS_R5, RS_R6, RS_R7, RS_R8,
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- RS_R9, RS_R10, RS_R11, RS_R12, RS_R31, RS_R30, RS_R29,
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- RS_R28, RS_R27, RS_R26, RS_R25, RS_R24, RS_R23, RS_R22,
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- RS_R21, RS_R20, RS_R19, RS_R18, RS_R17, RS_R16, RS_R15,
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- RS_R14], first_int_imreg, []);
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+ if (target_info.system <> system_powerpc64_darwin) then
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+ // r13 is tls, do not use, r2 is not available
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+ rg[R_INTREGISTER] := trgcpu.create(R_INTREGISTER, R_SUBWHOLE,
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+ [RS_R3, RS_R4, RS_R5, RS_R6, RS_R7, RS_R8,
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+ RS_R9, RS_R10, RS_R11, RS_R12, RS_R31, RS_R30, RS_R29,
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+ RS_R28, RS_R27, RS_R26, RS_R25, RS_R24, RS_R23, RS_R22,
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+ RS_R21, RS_R20, RS_R19, RS_R18, RS_R17, RS_R16, RS_R15,
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+ RS_R14], first_int_imreg, [])
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+ else
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+ { special for darwin/ppc64: r2 available volatile, r13 = tls }
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+ rg[R_INTREGISTER] := trgcpu.create(R_INTREGISTER, R_SUBWHOLE,
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+ [RS_R2, RS_R3, RS_R4, RS_R5, RS_R6, RS_R7, RS_R8,
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+ RS_R9, RS_R10, RS_R11, RS_R12, RS_R31, RS_R30, RS_R29,
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+ RS_R28, RS_R27, RS_R26, RS_R25, RS_R24, RS_R23, RS_R22,
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+ RS_R21, RS_R20, RS_R19, RS_R18, RS_R17, RS_R16, RS_R15,
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+ RS_R14], first_int_imreg, []);
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rg[R_FPUREGISTER] := trgcpu.create(R_FPUREGISTER, R_SUBNONE,
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rg[R_FPUREGISTER] := trgcpu.create(R_FPUREGISTER, R_SUBNONE,
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[RS_F0, RS_F1, RS_F2, RS_F3, RS_F4, RS_F5, RS_F6, RS_F7, RS_F8, RS_F9,
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[RS_F0, RS_F1, RS_F2, RS_F3, RS_F4, RS_F5, RS_F6, RS_F7, RS_F8, RS_F9,
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RS_F10, RS_F11, RS_F12, RS_F13, RS_F31, RS_F30, RS_F29, RS_F28, RS_F27,
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RS_F10, RS_F11, RS_F12, RS_F13, RS_F31, RS_F30, RS_F29, RS_F28, RS_F27,
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@@ -669,11 +673,11 @@ procedure tcgppc.a_load_const_reg(list: TAsmList; size: TCGSize; a: aint;
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begin
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begin
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if (lo(a) = 0) and (hi(a) <> 0) then begin
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if (lo(a) = 0) and (hi(a) <> 0) then begin
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{ load only upper 32 bits, and shift }
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{ load only upper 32 bits, and shift }
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- load32bitconstant(list, size, hi(a), reg);
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+ load32bitconstant(list, size, longint(hi(a)), reg);
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list.concat(taicpu.op_reg_reg_const(A_SLDI, reg, reg, 32));
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list.concat(taicpu.op_reg_reg_const(A_SLDI, reg, reg, 32));
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end else begin
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end else begin
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{ load lower 32 bits }
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{ load lower 32 bits }
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- extendssign := load32bitconstant(list, size, lo(a), reg);
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+ extendssign := load32bitconstant(list, size, longint(lo(a)), reg);
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if (extendssign) and (hi(a) = 0) then
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if (extendssign) and (hi(a) = 0) then
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{ if upper 32 bits are zero, but loading the lower 32 bit resulted in automatic
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{ if upper 32 bits are zero, but loading the lower 32 bit resulted in automatic
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sign extension, clear those bits }
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sign extension, clear those bits }
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@@ -689,7 +693,7 @@ procedure tcgppc.a_load_const_reg(list: TAsmList; size: TCGSize; a: aint;
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- loading the lower 32 bits resulted in 0 in the upper 32 bits, and the upper
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- loading the lower 32 bits resulted in 0 in the upper 32 bits, and the upper
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32 bits should contain 0 }
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32 bits should contain 0 }
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a_reg_alloc(list, NR_R0);
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a_reg_alloc(list, NR_R0);
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- load32bitconstantR0(list, size, hi(a));
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+ load32bitconstantR0(list, size, longint(hi(a)));
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{ combine both registers }
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{ combine both registers }
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list.concat(taicpu.op_reg_reg_const_const(A_RLDIMI, reg, NR_R0, 32, 0));
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list.concat(taicpu.op_reg_reg_const_const(A_RLDIMI, reg, NR_R0, 32, 0));
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a_reg_dealloc(list, NR_R0);
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a_reg_dealloc(list, NR_R0);
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@@ -964,7 +968,7 @@ var
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end else begin
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end else begin
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getmagic_unsignedN(sizeof(aWord)*8, a, u_magic, u_add, u_shift);
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getmagic_unsignedN(sizeof(aWord)*8, a, u_magic, u_add, u_shift);
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{ load magic in divreg }
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{ load magic in divreg }
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- cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, u_magic, divreg);
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+ cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, aint(u_magic), divreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULHDU, dst, src, divreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULHDU, dst, src, divreg));
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if (u_add) then begin
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if (u_add) then begin
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, dst, src, divreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, dst, src, divreg);
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@@ -1209,8 +1213,17 @@ begin
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end;
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end;
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procedure tcgppc.a_jmp_name(list: TAsmList; const s: string);
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procedure tcgppc.a_jmp_name(list: TAsmList; const s: string);
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+var
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+ p: taicpu;
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begin
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begin
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- a_jmp_name_direct(list, s, true);
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+ if (target_info.system = system_powerpc64_darwin) then
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+ begin
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+ p := taicpu.op_sym(A_B,get_darwin_call_stub(s));
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+ p.is_jmp := true;
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+ list.concat(p)
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+ end
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+ else
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+ a_jmp_name_direct(list, s, true);
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end;
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end;
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procedure tcgppc.a_jmp_always(list: TAsmList; l: tasmlabel);
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procedure tcgppc.a_jmp_always(list: TAsmList; l: tasmlabel);
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@@ -1629,6 +1642,12 @@ var
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tempreg : TRegister;
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tempreg : TRegister;
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begin
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begin
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+ if (target_info.system = system_powerpc64_darwin) then
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+ begin
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+ inherited a_loadaddr_ref_reg(list,ref,r);
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+ exit;
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+ end;
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+
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ref2 := ref;
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ref2 := ref;
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fixref(list, ref2);
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fixref(list, ref2);
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{ load a symbol }
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{ load a symbol }
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@@ -1849,83 +1868,6 @@ begin
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end;
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end;
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-procedure tcgppc.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const
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- labelname: string; ioffset: longint);
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-
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- procedure loadvmttor11;
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- var
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- href: treference;
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- begin
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- reference_reset_base(href, NR_R3, 0);
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- cg.a_load_ref_reg(list, OS_ADDR, OS_ADDR, href, NR_R11);
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- end;
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-
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- procedure op_onr11methodaddr;
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- var
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- href: treference;
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- begin
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- if (procdef.extnumber = $FFFF) then
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- Internalerror(200006139);
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- { call/jmp vmtoffs(%eax) ; method offs }
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- reference_reset_base(href, NR_R11,
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- procdef._class.vmtmethodoffset(procdef.extnumber));
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- if not (hasLargeOffset(href)) then begin
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- list.concat(taicpu.op_reg_reg_const(A_ADDIS, NR_R11, NR_R11,
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- smallint((href.offset shr 16) + ord(smallint(href.offset and $FFFF) <
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- 0))));
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- href.offset := smallint(href.offset and $FFFF);
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- end else
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- { add support for offsets > 16 bit }
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- internalerror(200510201);
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- list.concat(taicpu.op_reg_ref(A_LD, NR_R11, href));
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- { the loaded reference is a function descriptor reference, so deref again
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- (at ofs 0 there's the real pointer) }
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- {$warning ts:TODO: update GOT reference}
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- reference_reset_base(href, NR_R11, 0);
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- list.concat(taicpu.op_reg_ref(A_LD, NR_R11, href));
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-
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- list.concat(taicpu.op_reg(A_MTCTR, NR_R11));
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- list.concat(taicpu.op_none(A_BCTR));
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- { NOP needed for the linker...? }
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- list.concat(taicpu.op_none(A_NOP));
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- end;
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-
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-var
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- make_global: boolean;
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-begin
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- if (not (procdef.proctypeoption in [potype_function, potype_procedure])) then
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- Internalerror(200006137);
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- if not assigned(procdef._class) or
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- (procdef.procoptions * [po_classmethod, po_staticmethod,
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- po_methodpointer, po_interrupt, po_iocheck] <> []) then
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- Internalerror(200006138);
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- if procdef.owner.symtabletype <> ObjectSymtable then
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- Internalerror(200109191);
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-
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- make_global := false;
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- if (not current_module.is_unit) or
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- (cs_create_smart in current_settings.moduleswitches) or
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- (procdef.owner.defowner.owner.symtabletype = globalsymtable) then
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- make_global := true;
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-
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- if make_global then
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- List.concat(Tai_symbol.Createname_global(labelname, AT_FUNCTION, 0))
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- else
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- List.concat(Tai_symbol.Createname(labelname, AT_FUNCTION, 0));
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-
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- { set param1 interface to self }
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- g_adjust_self_value(list, procdef, ioffset);
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-
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- if po_virtualmethod in procdef.procoptions then begin
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- loadvmttor11;
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- op_onr11methodaddr;
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- end else
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- {$note ts:todo add GOT change?? - think not needed :) }
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- list.concat(taicpu.op_sym(A_B,current_asmdata.RefAsmSymbol('.' + procdef.mangledname)));
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-
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- List.concat(Tai_symbol_end.Createname(labelname));
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-end;
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-
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{***************** This is private property, keep out! :) *****************}
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{***************** This is private property, keep out! :) *****************}
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procedure tcgppc.maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
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procedure tcgppc.maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
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@@ -1999,9 +1941,28 @@ begin
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list.concat(tai_comment.create(strpnew('fixref0 ' + ref2string(ref))));
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list.concat(tai_comment.create(strpnew('fixref0 ' + ref2string(ref))));
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{$ENDIF EXTDEBUG}
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{$ENDIF EXTDEBUG}
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+ if (target_info.system = system_powerpc64_darwin) and
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+ assigned(ref.symbol) and
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+ (ref.symbol.bind = AB_EXTERNAL) then
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+ begin
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+ tmpreg := g_indirect_sym_load(list,ref.symbol.name);
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+ if (ref.base = NR_NO) then
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+ ref.base := tmpreg
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+ else if (ref.index = NR_NO) then
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+ ref.index := tmpreg
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+ else
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+ begin
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+ list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
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+ ref.base := tmpreg;
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+ end;
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+ ref.symbol := nil;
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+ end;
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+
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+
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{ if we have to create PIC, add the symbol to the TOC/GOT }
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{ if we have to create PIC, add the symbol to the TOC/GOT }
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{$WARNING Hack for avoiding too long manglednames enabled!!}
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{$WARNING Hack for avoiding too long manglednames enabled!!}
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- if (cs_create_pic in current_settings.moduleswitches) and (assigned(ref.symbol) and
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+ if (target_info.system <> system_powerpc64_darwin) and
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+ (cs_create_pic in current_settings.moduleswitches) and (assigned(ref.symbol) and
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(length(ref.symbol.name) < MAX_GOT_SYMBOL_NAME_LENGTH_HACK)) then begin
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(length(ref.symbol.name) < MAX_GOT_SYMBOL_NAME_LENGTH_HACK)) then begin
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tmpreg := load_got_symbol(list, ref.symbol.name);
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tmpreg := load_got_symbol(list, ref.symbol.name);
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if (ref.base = NR_NO) then
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if (ref.base = NR_NO) then
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@@ -2039,11 +2000,44 @@ end;
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procedure tcgppc.a_load_store(list: TAsmList; op: tasmop; reg: tregister;
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procedure tcgppc.a_load_store(list: TAsmList; op: tasmop; reg: tregister;
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ref: treference);
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ref: treference);
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+
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+ procedure maybefixup64bitoffset;
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+ var
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+ tmpreg: tregister;
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+ begin
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+ { for some instructions we need to check that the offset is divisible by at
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+ least four. If not, add the bytes which are "off" to the base register and
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+ adjust the offset accordingly }
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+ case op of
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+ A_LD, A_LDU, A_STD, A_STDU, A_LWA :
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|
|
+ if ((ref.offset mod 4) <> 0) then begin
|
|
|
|
+ tmpreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
|
|
|
|
+
|
|
|
|
+ if (ref.base <> NR_NO) then begin
|
|
|
|
+ a_op_const_reg_reg(list, OP_ADD, OS_ADDR, ref.offset mod 4, ref.base, tmpreg);
|
|
|
|
+ ref.base := tmpreg;
|
|
|
|
+ end else begin
|
|
|
|
+ list.concat(taicpu.op_reg_const(A_LI, tmpreg, ref.offset mod 4));
|
|
|
|
+ ref.base := tmpreg;
|
|
|
|
+ end;
|
|
|
|
+ ref.offset := (ref.offset div 4) * 4;
|
|
|
|
+ end;
|
|
|
|
+ end;
|
|
|
|
+ end;
|
|
|
|
+
|
|
var
|
|
var
|
|
tmpreg, tmpreg2: tregister;
|
|
tmpreg, tmpreg2: tregister;
|
|
tmpref: treference;
|
|
tmpref: treference;
|
|
largeOffset: Boolean;
|
|
largeOffset: Boolean;
|
|
begin
|
|
begin
|
|
|
|
+ if (target_info.system = system_powerpc64_darwin) then
|
|
|
|
+ begin
|
|
|
|
+ { darwin/ppc64 works with 32 bit relocatable symbol addresses }
|
|
|
|
+ maybefixup64bitoffset;
|
|
|
|
+ inherited a_load_store(list,op,reg,ref);
|
|
|
|
+ exit
|
|
|
|
+ end;
|
|
|
|
+
|
|
{ at this point there must not be a combination of values in the ref treference
|
|
{ at this point there must not be a combination of values in the ref treference
|
|
which is not possible to directly map to instructions of the PowerPC architecture }
|
|
which is not possible to directly map to instructions of the PowerPC architecture }
|
|
if (ref.index <> NR_NO) and ((ref.offset <> 0) or (assigned(ref.symbol))) then
|
|
if (ref.index <> NR_NO) and ((ref.offset <> 0) or (assigned(ref.symbol))) then
|
|
@@ -2061,24 +2055,7 @@ begin
|
|
exit;
|
|
exit;
|
|
end;
|
|
end;
|
|
|
|
|
|
- { for some instructions we need to check that the offset is divisible by at
|
|
|
|
- least four. If not, add the bytes which are "off" to the base register and
|
|
|
|
- adjust the offset accordingly }
|
|
|
|
- case op of
|
|
|
|
- A_LD, A_LDU, A_STD, A_STDU, A_LWA :
|
|
|
|
- if ((ref.offset mod 4) <> 0) then begin
|
|
|
|
- tmpreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
|
|
|
|
-
|
|
|
|
- if (ref.base <> NR_NO) then begin
|
|
|
|
- a_op_const_reg_reg(list, OP_ADD, OS_ADDR, ref.offset mod 4, ref.base, tmpreg);
|
|
|
|
- ref.base := tmpreg;
|
|
|
|
- end else begin
|
|
|
|
- list.concat(taicpu.op_reg_const(A_LI, tmpreg, ref.offset mod 4));
|
|
|
|
- ref.base := tmpreg;
|
|
|
|
- end;
|
|
|
|
- ref.offset := (ref.offset div 4) * 4;
|
|
|
|
- end;
|
|
|
|
- end;
|
|
|
|
|
|
+ maybefixup64bitoffset;
|
|
{$IFDEF EXTDEBUG}
|
|
{$IFDEF EXTDEBUG}
|
|
list.concat(tai_comment.create(strpnew('a_load_store1 ' + BoolToStr(ref.refaddr = addr_pic))));
|
|
list.concat(tai_comment.create(strpnew('a_load_store1 ' + BoolToStr(ref.refaddr = addr_pic))));
|
|
{$ENDIF EXTDEBUG}
|
|
{$ENDIF EXTDEBUG}
|
|
@@ -2183,12 +2160,6 @@ begin
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
-function tcgppc.hasLargeOffset(const ref : TReference) : Boolean; {$ifdef ver2_0}inline;{$endif}
|
|
|
|
-begin
|
|
|
|
- { this rather strange calculation is required because offsets of TReferences are unsigned }
|
|
|
|
- result := aword(ref.offset-low(smallint)) > high(smallint)-low(smallint);
|
|
|
|
-end;
|
|
|
|
-
|
|
|
|
procedure tcgppc.loadConstantPIC(list : TAsmList; size : TCGSize; a : aint; reg : TRegister);
|
|
procedure tcgppc.loadConstantPIC(list : TAsmList; size : TCGSize; a : aint; reg : TRegister);
|
|
var
|
|
var
|
|
l: tasmsymbol;
|
|
l: tasmsymbol;
|