the basic i8086 units: cpuinfo and cpubase

git-svn-id: branches/i8086@23716 -

.gitattributes

@@ -237,6 +237,8 @@ compiler/i386/ra386att.pas svneol=native#text/plain
 compiler/i386/ra386int.pas svneol=native#text/plain
 compiler/i386/rgcpu.pas svneol=native#text/plain
 compiler/i386/rropt386.pas svneol=native#text/plain
+compiler/i8086/cpubase.inc svneol=native#text/plain
+compiler/i8086/cpuinfo.pas svneol=native#text/plain
 compiler/ia64/aasmcpu.pas svneol=native#text/plain
 compiler/ia64/cpubase.pas svneol=native#text/plain
 compiler/ia64/cpuinfo.pas svneol=native#text/plain

compiler/i8086/cpubase.inc

@@ -0,0 +1,149 @@
+{
+    Copyright (c) 1998-2000 by Florian Klaempfl and Peter Vreman
+
+    Contains the basic declarations for the i8086 architecture
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+{ This include file contains the basic declarations for the i8086 architecture.
+}
+
+{*****************************************************************************
+                                Operand Sizes
+*****************************************************************************}
+
+    type
+      topsize = (S_NO,
+        S_B,S_W,S_L,S_Q,S_BW,S_BL,S_WL,
+        S_IS,S_IL,S_IQ,
+        S_FS,S_FL,S_FX,S_FV,S_FXX,
+        S_MD,
+        S_NEAR,S_FAR,S_SHORT,
+        S_T,
+        S_XMM,
+        S_YMM
+      );
+
+
+{*****************************************************************************
+                                Registers
+*****************************************************************************}
+  const
+      {# Standard opcode string table (for each tasmop enumeration). The
+         opcode strings should conform to the names as defined by the
+         processor manufacturer.
+      }
+      std_op2str:op2strtable={$i i386int.inc}
+
+{*****************************************************************************
+                               GDB Information
+*****************************************************************************}
+
+      {# Register indexes for stabs information, when some
+         parameters or variables are stored in registers.
+
+         Taken from i386.c (dbx_register_map) and i386.h
+          (FIXED_REGISTERS) from GCC 3.x source code
+
+      }
+      reg_stab_table : array[tregisterindex] of shortint = (
+        {$i r386stab.inc}
+      );
+
+
+{*****************************************************************************
+                          Default generic sizes
+*****************************************************************************}
+
+      {# Defines the default address size for a processor, }
+      OS_ADDR = OS_16;
+      {# the natural int size for a processor,
+         has to match osuinttype/ossinttype as initialized in psystem }
+      OS_INT = OS_16;
+      OS_SINT = OS_S16;
+      {# the maximum float size for a processor,           }
+      OS_FLOAT = OS_F80;
+      {# the size of a vector register for a processor     }
+      OS_VECTOR = OS_M128;
+
+{*****************************************************************************
+                          Generic Register names
+*****************************************************************************}
+
+      {# Stack pointer register }
+      NR_STACK_POINTER_REG = NR_SP;
+      RS_STACK_POINTER_REG = RS_SP;
+      {# Frame pointer register }
+      RS_FRAME_POINTER_REG = RS_BP;
+      NR_FRAME_POINTER_REG = NR_BP;
+      { Return address for DWARF }
+      NR_RETURN_ADDRESS_REG = NR_EIP;
+      {# Register for addressing absolute data in a position independant way,
+         such as in PIC code. The exact meaning is ABI specific. For
+         further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
+      }
+      NR_PIC_OFFSET_REG = NR_BX;
+      { Results are returned in this register (32-bit values) }
+      NR_FUNCTION_RETURN_REG = NR_AX;
+      RS_FUNCTION_RETURN_REG = RS_AX;
+      { Low part of 64bit return value }
+      NR_FUNCTION_RETURN64_LOW_REG = NR_AX;
+      RS_FUNCTION_RETURN64_LOW_REG = RS_AX;
+      { High part of 64bit return value }
+      NR_FUNCTION_RETURN64_HIGH_REG = NR_DX;
+      RS_FUNCTION_RETURN64_HIGH_REG = RS_DX;
+      { The value returned from a function is available in this register }
+      NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
+      RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
+      { The lowh part of 64bit value returned from a function }
+      NR_FUNCTION_RESULT64_LOW_REG = NR_FUNCTION_RETURN64_LOW_REG;
+      RS_FUNCTION_RESULT64_LOW_REG = RS_FUNCTION_RETURN64_LOW_REG;
+      { The high part of 64bit value returned from a function }
+      NR_FUNCTION_RESULT64_HIGH_REG = NR_FUNCTION_RETURN64_HIGH_REG;
+      RS_FUNCTION_RESULT64_HIGH_REG = RS_FUNCTION_RETURN64_HIGH_REG;
+
+      { WARNING: don't change to R_ST0!! See comments above implementation of }
+      { a_loadfpu* methods in rgcpu (JM)                                      }
+      NR_fpu_result_reg = NR_ST;
+      NR_mm_result_reg = NR_MM0;
+
+      { Offset where the parent framepointer is pushed }
+      PARENT_FRAMEPOINTER_OFFSET = 8;
+
+{*****************************************************************************
+                       GCC /ABI linking information
+*****************************************************************************}
+
+    const
+      {# Registers which must be saved when calling a routine declared as
+         cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
+         saved should be the ones as defined in the target ABI and / or GCC.
+
+         This value can be deduced from the CALLED_USED_REGISTERS array in the
+         GCC source.
+      }
+      saved_standard_registers : array[0..3] of tsuperregister = (RS_BX,RS_SI,RS_DI,RS_BP);
+
+      saved_mm_registers : array[0..0] of tsuperregister = (RS_INVALID);
+      {# Required parameter alignment when calling a routine declared as
+         stdcall and cdecl. The alignment value should be the one defined
+         by GCC or the target ABI.
+
+         The value of this constant is equal to the constant
+         PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
+      }
+      std_param_align = 4;

compiler/i8086/cpuinfo.pas

@@ -0,0 +1,130 @@
+{
+    Copyright (c) 1998-2004 by Florian Klaempfl
+
+    Basic Processor information
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+Unit cpuinfo;
+
+{$i fpcdefs.inc}
+
+Interface
+
+  uses
+    globtype;
+
+Type
+   bestreal = extended;
+   ts32real = single;
+   ts64real = double;
+   ts80real = extended;
+   ts128real = type extended;
+   ts64comp = type extended;
+
+   pbestreal=^bestreal;
+
+   { possible supported processors for this target }
+   tcputype =
+      (cpu_none,
+       cpu_8086,
+       cpu_186,
+       cpu_286,
+       cpu_386,
+       cpu_Pentium,
+       cpu_Pentium2,
+       cpu_Pentium3,
+       cpu_Pentium4,
+       cpu_PentiumM
+      );
+
+   tfputype =
+     (fpu_none,
+//      fpu_soft,
+      fpu_x87,
+      fpu_sse,
+      fpu_sse2,
+      fpu_sse3,
+      fpu_ssse3,
+      fpu_sse41,
+      fpu_sse42,
+      fpu_avx
+     );
+
+
+Const
+   { calling conventions supported by the code generator }
+   supported_calling_conventions : tproccalloptions = [
+     pocall_internproc,
+     pocall_register,
+     pocall_safecall,
+     pocall_stdcall,
+     pocall_cdecl,
+     pocall_cppdecl,
+     pocall_far16,
+     pocall_pascal,
+     pocall_oldfpccall,
+     pocall_mwpascal
+   ];
+
+   cputypestr : array[tcputype] of string[10] = ('',
+     '8086',
+     '80186',
+     '80286',
+     '80386',
+     'PENTIUM',
+     'PENTIUM2',
+     'PENTIUM3',
+     'PENTIUM4',
+     'PENTIUMM'
+   );
+
+   fputypestr : array[tfputype] of string[6] = ('',
+//     'SOFT',
+     'X87',
+     'SSE',
+     'SSE2',
+     'SSE3',
+     'SSSE3',
+     'SSE41',
+     'SSE42',
+     'AVX'
+   );
+
+   sse_singlescalar : set of tfputype = [fpu_sse,fpu_sse2,fpu_sse3];
+   sse_doublescalar : set of tfputype = [fpu_sse2,fpu_sse3];
+
+   { Supported optimizations, only used for information }
+   supported_optimizerswitches = genericlevel1optimizerswitches+
+                                 genericlevel2optimizerswitches+
+                                 genericlevel3optimizerswitches-
+                                 { no need to write info about those }
+                                 [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
+                                 [cs_opt_peephole,cs_opt_regvar,cs_opt_stackframe,
+                                  cs_opt_asmcse,cs_opt_loopunroll,cs_opt_uncertain,
+                                  cs_opt_tailrecursion,cs_opt_nodecse,cs_useebp,
+				  cs_opt_reorder_fields,cs_opt_fastmath];
+
+   level1optimizerswitches = genericlevel1optimizerswitches + [cs_opt_peephole];
+   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
+     [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
+   level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
+   level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_useebp];
+
+Implementation
+
+end.