* improved register usage

  + implemented second_cmp64bit

compiler/arm/cgcpu.pas

@@ -124,9 +124,10 @@ unit cgcpu;
     procedure tcgarm.init_register_allocators;
       begin
         inherited init_register_allocators;
+        { currently, we save R14 always, so we can use it }
         rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
             [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
-             RS_R9,RS_R10,RS_R12],first_int_imreg,[]);
+             RS_R9,RS_R10,RS_R12,RS_R14],first_int_imreg,[]);
         rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
             [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
         rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
@@ -1207,7 +1208,11 @@ begin
 end.
 {
   $Log$
-  Revision 1.34  2004-01-21 19:01:03  florian
+  Revision 1.35  2004-01-22 01:47:15  florian
+    * improved register usage
+    + implemented second_cmp64bit
+
+  Revision 1.34  2004/01/21 19:01:03  florian
     * fixed handling of max. distance of pc relative symbols
 
   Revision 1.33  2004/01/21 15:41:56  florian

compiler/arm/narmadd.pas

@@ -230,14 +230,47 @@ interface
     procedure tarmaddnode.second_cmp64bit;
       var
         unsigned : boolean;
+        tmpreg : tregister;
       begin
-{$warning TODO 64bit compare}
+        pass_left_right;
+        force_reg_left_right(false,false);
+
         unsigned:=not(is_signed(left.resulttype.def)) or
                   not(is_signed(right.resulttype.def));
 
         location_reset(location,LOC_FLAGS,OS_NO);
         location.resflags:=getresflags(unsigned);
 
+        { operation requiring proper N, Z and C flags ? }
+        if unsigned or (nodetype in [equaln,unequaln]) then
+          begin
+            exprasmlist.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo));
+            exprasmlist.concat(setcondition(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi),C_EQ));
+          end
+        { operation requiring proper N, V and C flags ? }
+        else if nodetype in [gten,ltn] then
+          begin
+            tmpreg:=cg.getintregister(exprasmlist,location.size);
+            exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,tmpreg,left.location.register64.reglo,right.location.register64.reglo),PF_S));
+            exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,tmpreg,left.location.register64.reghi,right.location.register64.reghi),PF_S));
+            cg.ungetregister(exprasmlist,tmpreg);
+          end
+        else
+        { operation requiring proper N, Z and V flags ? }
+          begin
+            { this isn't possible so swap operands and use the "reverse" operation }
+            tmpreg:=cg.getintregister(exprasmlist,location.size);
+            exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,tmpreg,right.location.register64.reglo,left.location.register64.reglo),PF_S));
+            exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,tmpreg,right.location.register64.reghi,left.location.register64.reghi),PF_S));
+            cg.ungetregister(exprasmlist,tmpreg);
+            if location.resflags=F_GT then
+              location.resflags:=F_LT
+            else if location.resflags=F_LE then
+              location.resflags:=F_GE
+            else
+              internalerror(200401221);
+          end;
+
         release_reg_left_right;
       end;
 
@@ -281,7 +314,11 @@ begin
 end.
 {
   $Log$
-  Revision 1.5  2003-11-02 14:30:03  florian
+  Revision 1.6  2004-01-22 01:47:15  florian
+    * improved register usage
+    + implemented second_cmp64bit
+
+  Revision 1.5  2003/11/02 14:30:03  florian
     * fixed ARM for new reg. allocation scheme
 
   Revision 1.4  2003/09/01 15:11:16  florian