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@@ -2564,16 +2564,16 @@ implementation
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{$else x86}
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{$else x86}
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result:=(typ=floatdef) and not(cs_fp_emulation in current_settings.moduleswitches)
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result:=(typ=floatdef) and not(cs_fp_emulation in current_settings.moduleswitches)
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{$ifdef xtensa}
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{$ifdef xtensa}
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- and (FPUXTENSA_SINGLE in fpu_capabilities[init_settings.fputype]) and (tfloatdef(self).floattype=s32real)
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+ and (FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) and (tfloatdef(self).floattype=s32real)
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{$endif xtensa}
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{$endif xtensa}
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{$ifdef riscv}
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{$ifdef riscv}
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- and (((CPURV_HAS_F in cpu_capabilities[init_settings.cputype]) and (tfloatdef(self).floattype=s32real)) or
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- ((CPURV_HAS_D in cpu_capabilities[init_settings.cputype]) and (tfloatdef(self).floattype=s64real)) or
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- ((CPURV_HAS_Q in cpu_capabilities[init_settings.cputype]) and (tfloatdef(self).floattype=s128real)))
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+ and (((CPURV_HAS_F in cpu_capabilities[current_settings.cputype]) and (tfloatdef(self).floattype=s32real)) or
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+ ((CPURV_HAS_D in cpu_capabilities[current_settings.cputype]) and (tfloatdef(self).floattype=s64real)) or
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+ ((CPURV_HAS_Q in cpu_capabilities[current_settings.cputype]) and (tfloatdef(self).floattype=s128real)))
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{$endif riscv}
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{$endif riscv}
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{$ifdef arm}
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{$ifdef arm}
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- and (((FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[init_settings.fputype]) and (tfloatdef(self).floattype=s32real)) or
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- (FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[init_settings.fputype]))
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+ and (((FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype]) and (tfloatdef(self).floattype=s32real)) or
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+ (FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype]))
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{$endif arm}
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{$endif arm}
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;
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;
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{$endif x86}
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{$endif x86}
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