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* changed dcbst to dcbtst (former means "flush cache block to memory,
the latter means "I will soon store something to that cache block")

Jonas Maebe hace 22 años
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commit
71bd041932
Se han modificado 2 ficheros con 17 adiciones y 10 borrados
  1. 7 4
      rtl/powerpc/powerpc.inc
  2. 10 6
      rtl/powerpc/set.inc

+ 7 - 4
rtl/powerpc/powerpc.inc

@@ -145,7 +145,7 @@ asm
           {  load the begin of the source in the data cache }
           {  load the begin of the source in the data cache }
           dcbt    0,r3
           dcbt    0,r3
           { and the dest as well }
           { and the dest as well }
-          dcbst   0,r4
+          dcbtst  0,r4
 
 
           {  if overlap, then r0 := count else r0 := 0  }
           {  if overlap, then r0 := count else r0 := 0  }
           and     r0,r5,r10
           and     r0,r5,r10
@@ -234,7 +234,6 @@ LMove32BytesAligned:
 
 
           {  adjust the update count: it will now be 8 or -8 depending on overlap  }
           {  adjust the update count: it will now be 8 or -8 depending on overlap  }
           slwi    r10,r10,1
           slwi    r10,r10,1
-          { get dcbz offset }
 
 
           {  adjust source and dest pointers: because of the above loop, dest is now   }
           {  adjust source and dest pointers: because of the above loop, dest is now   }
           {  aligned to 8 bytes. So if we add r6 we will still have an 8 bytes         }
           {  aligned to 8 bytes. So if we add r6 we will still have an 8 bytes         }
@@ -347,7 +346,7 @@ asm
         ble       cr6,LFillCharDone
         ble       cr6,LFillCharDone
         { get the start of the data in the cache (and mark it as "will be }
         { get the start of the data in the cache (and mark it as "will be }
         { modified")                                                      }
         { modified")                                                      }
-        dcbst     0,r3
+        dcbtst    0,r3
         subfic    r10,r10,4
         subfic    r10,r10,4
         blt       cr7,LFillCharVerySmall
         blt       cr7,LFillCharVerySmall
         { just store 4 bytes instead of using a loop to align (there are }
         { just store 4 bytes instead of using a loop to align (there are }
@@ -933,7 +932,11 @@ end ['R3','R10'];
 
 
 {
 {
   $Log$
   $Log$
-  Revision 1.47  2003-05-29 12:14:02  jonas
+  Revision 1.48  2003-05-29 14:32:54  jonas
+    * changed dcbst to dcbtst (former means "flush cache block to memory,
+      the latter means "I will soon store something to that cache block")
+
+  Revision 1.47  2003/05/29 12:14:02  jonas
     * move() now uses dcbz if possible
     * move() now uses dcbz if possible
 
 
   Revision 1.46  2003/05/17 00:19:51  jonas
   Revision 1.46  2003/05/17 00:19:51  jonas

+ 10 - 6
rtl/powerpc/set.inc

@@ -158,7 +158,7 @@ asm
   bgt    cr0,Lset_range_exit
   bgt    cr0,Lset_range_exit
   rlwinm r4,r5,31-3+1,3,31-2  // divide by 8 to get starting and ending byte-
   rlwinm r4,r5,31-3+1,3,31-2  // divide by 8 to get starting and ending byte-
   { load the set the data cache }
   { load the set the data cache }
-  dcbst  r3,r4
+  dcbtst r3,r4
   rlwinm r9,r6,31-3+1,3,31-2  // address and clear two lowest bits to get
   rlwinm r9,r6,31-3+1,3,31-2  // address and clear two lowest bits to get
                               //  start/end longint address
                               //  start/end longint address
   sub.   r9,r9,r4             // are bit lo and hi in the same longint?
   sub.   r9,r9,r4             // are bit lo and hi in the same longint?
@@ -230,7 +230,7 @@ function fpc_set_add_sets(const set1,set2: fpc_normal_set): fpc_normal_set;assem
 }
 }
 asm
 asm
        {  load the begin of the result set in the data cache }
        {  load the begin of the result set in the data cache }
-       dcbst    0,r3
+       dcbtst   0,r3
        li       r0,8
        li       r0,8
        mtctr    r0
        mtctr    r0
        subi     r5,r5,4
        subi     r5,r5,4
@@ -253,7 +253,7 @@ function fpc_set_mul_sets(const set1,set2: fpc_normal_set): fpc_normal_set;assem
 }
 }
 asm
 asm
        {  load the begin of the result set in the data cache }
        {  load the begin of the result set in the data cache }
-       dcbst    0,r3
+       dcbtst   0,r3
        li       r0,8
        li       r0,8
        mtctr    r0
        mtctr    r0
        subi     r5,r5,4
        subi     r5,r5,4
@@ -276,7 +276,7 @@ function fpc_set_sub_sets(const set1,set2: fpc_normal_set): fpc_normal_set;assem
 }
 }
 asm
 asm
        {  load the begin of the result set in the data cache }
        {  load the begin of the result set in the data cache }
-       dcbst    0,r3
+       dcbtst   0,r3
        li       r0,8
        li       r0,8
        mtctr    r0
        mtctr    r0
        subi     r5,r5,4
        subi     r5,r5,4
@@ -299,7 +299,7 @@ function fpc_set_symdif_sets(const set1,set2: fpc_normal_set): fpc_normal_set;as
 }
 }
 asm
 asm
        {  load the begin of the result set in the data cache }
        {  load the begin of the result set in the data cache }
-       dcbst    0,r3
+       dcbtst   0,r3
        li       r0,8
        li       r0,8
        mtctr    r0
        mtctr    r0
        subi     r5,r5,4
        subi     r5,r5,4
@@ -523,7 +523,11 @@ end;
 
 
 {
 {
   $Log$
   $Log$
-  Revision 1.20  2003-05-11 11:06:34  jonas
+  Revision 1.21  2003-05-29 14:32:54  jonas
+    * changed dcbst to dcbtst (former means "flush cache block to memory,
+      the latter means "I will soon store something to that cache block")
+
+  Revision 1.20  2003/05/11 11:06:34  jonas
     * fixed fpc_set_set_byte and fpc_set_unset_byte
     * fixed fpc_set_set_byte and fpc_set_unset_byte
 
 
   Revision 1.19  2003/05/02 15:10:53  jonas
   Revision 1.19  2003/05/02 15:10:53  jonas