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@@ -202,8 +202,7 @@ unit rgcpu;
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and 'and A,orgreg' with 'and A,spilltemp'
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and 'or A,orgreg' with 'or A,spilltemp'
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and 'xor A,orgreg' with 'xor A,spilltemp'
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- and 'cp A,orgreg' with 'cp A,spilltemp'
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- }
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+ and 'cp A,orgreg' with 'cp A,spilltemp' }
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else if (opcode in [A_ADD,A_ADC,A_SUB,A_SBC,A_AND,A_OR,A_XOR,A_CP]) and (ops=2) and (oper[1]^.typ=top_reg) and (oper[0]^.typ=top_reg) then
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begin
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{ we don't really need to check whether the first register is 'A',
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@@ -217,6 +216,18 @@ unit rgcpu;
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result:=true;
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end;
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end
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+ { Replace 'bit const,orgreg' with 'bit const,spilltemp'
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+ and 'set const,orgreg' with 'set const,spilltemp'
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+ and 'res const,orgreg' with 'res const,spilltemp' }
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+ else if (opcode in [A_BIT,A_SET,A_RES]) and (ops=2) and (oper[1]^.typ=top_reg) and (oper[0]^.typ=top_const) then
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+ begin
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+ if (getregtype(oper[1]^.reg)=regtype) and
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+ (get_alias(getsupreg(oper[1]^.reg))=orgreg) then
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+ begin
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+ instr.loadref(1,spilltemp);
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+ result:=true;
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+ end;
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+ end
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{ Replace 'inc orgreg' with 'inc spilltemp'
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and 'dec orgreg' with 'dec spilltemp'
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and 'add orgreg' with 'add spilltemp'
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nickysn