--- Merging r23700 into '.':

U    compiler/x86_64/cpupara.pas
U    compiler/x86/aasmcpu.pas
U    compiler/x86/cgx86.pas
A    tests/webtbs/tw23962.pp
--- Merging r23705 into '.':
A    tests/webtbs/tw24007.pp
U    compiler/nutils.pas
--- Merging r24465 into '.':
U    compiler/systems/t_linux.pas

# revisions: 23700,23705,24465
r23700 | jonas | 2013-03-06 13:42:46 +0100 (Wed, 06 Mar 2013) | 9 lines
Changed paths:
   M /trunk/compiler/x86/aasmcpu.pas
   M /trunk/compiler/x86/cgx86.pas
   M /trunk/compiler/x86_64/cpupara.pas
   A /trunk/tests/webtbs/tw23962.pp

  * set the subregsize of OS_M64 SSE registers to R_SUBQ so we can
    differentiate between 64 bit and 128 bit (R_SUBMMWHOLE) SSE vector regs,
    and support spilling/assembling for R_SUBQ SSE registers (8 bytes)
    (mantis #23962)

    We currently never use the full 128 bit of an SSE register, and
    spilling for those hasn't been implemented yet either (R_SUBMMWHOLE
    SSE regs are spilled into a 4-byte temp currently -> can overwrite data)
r23705 | jonas | 2013-03-07 16:44:41 +0100 (Thu, 07 Mar 2013) | 2 lines
Changed paths:
   M /trunk/compiler/nutils.pas
   A /trunk/tests/webtbs/tw24007.pp

  * fixed check for bitpacked accesses (mantis #24007)
r24465 | jonas | 2013-05-07 22:28:54 +0200 (Tue, 07 May 2013) | 3 lines
Changed paths:
   M /trunk/compiler/systems/t_linux.pas

  * only pass --gc-sections to the linker if smart linking is enabled
    (mantis #24396)

git-svn-id: branches/fixes_2_6@25917 -

.gitattributes

@@ -12080,7 +12080,9 @@ tests/webtbs/tw2377.pp svneol=native#text/plain
 tests/webtbs/tw2378.pp svneol=native#text/plain
 tests/webtbs/tw2382.pp svneol=native#text/plain
 tests/webtbs/tw2388.pp svneol=native#text/plain
+tests/webtbs/tw23962.pp svneol=native#text/plain
 tests/webtbs/tw2397.pp svneol=native#text/plain
+tests/webtbs/tw24007.pp svneol=native#text/plain
 tests/webtbs/tw2409.pp svneol=native#text/plain
 tests/webtbs/tw2421.pp svneol=native#text/plain
 tests/webtbs/tw2423.pp svneol=native#text/plain

compiler/nutils.pas

@@ -1154,7 +1154,8 @@ implementation
               { only orddefs and enumdefs are actually bitpacked. Don't consider
                 e.g. an access to a 3-byte record as "bitpacked", since it
                 isn't }
-              (tvecnode(n).left.resultdef.typ in [orddef,enumdef]) and
+              (tvecnode(n).left.resultdef.typ = arraydef) and
+              (tarraydef(tvecnode(n).left.resultdef).elementdef.typ in [orddef,enumdef]) and
               not(tarraydef(tvecnode(n).left.resultdef).elepackedbitsize in [8,16,32,64]);
           subscriptn:
             result:=

compiler/systems/t_linux.pas

@@ -998,7 +998,8 @@ begin
    StripStr:='-s';
   if (cs_link_map in current_settings.globalswitches) then
    StripStr:='-Map '+maybequoted(ChangeFileExt(current_module.exefilename^,'.map'));
-  if create_smartlink_sections then
+  if (cs_link_smart in current_settings.globalswitches) and
+     create_smartlink_sections then
    GCSectionsStr:='--gc-sections';
   If (cs_profile in current_settings.moduleswitches) or
      ((Info.DynamicLinker<>'') and (not SharedLibFiles.Empty)) then

compiler/x86/aasmcpu.pas

@@ -2511,6 +2511,7 @@ implementation
                 result:=taicpu.op_ref_reg(A_MOVSD,reg2opsize(r),ref,r);
               R_SUBMMS:
                 result:=taicpu.op_ref_reg(A_MOVSS,reg2opsize(r),ref,r);
+              R_SUBQ,
               R_SUBMMWHOLE:
                 result:=taicpu.op_ref_reg(A_MOVQ,S_NO,ref,r);
               else
@@ -2547,6 +2548,7 @@ implementation
                 result:=taicpu.op_reg_ref(A_MOVSD,reg2opsize(r),r,ref);
               R_SUBMMS:
                 result:=taicpu.op_reg_ref(A_MOVSS,reg2opsize(r),r,ref);
+              R_SUBQ,
               R_SUBMMWHOLE:
                 result:=taicpu.op_reg_ref(A_MOVQ,S_NO,r,ref);
               else

compiler/x86/cgx86.pas

@@ -199,7 +199,8 @@ unit cgx86;
             result:=rg[R_MMREGISTER].getregister(list,R_SUBMMD);
           OS_F32:
             result:=rg[R_MMREGISTER].getregister(list,R_SUBMMS);
-          OS_M64,
+          OS_M64:
+            result:=rg[R_MMREGISTER].getregister(list,R_SUBQ);
           OS_M128:
             result:=rg[R_MMREGISTER].getregister(list,R_SUBMMWHOLE);
           else

compiler/x86_64/cpupara.pas

@@ -935,7 +935,7 @@ unit cpupara;
                           end;
                         else
                           begin
-                            setsubreg(paraloc^.register,R_SUBMMWHOLE);
+                            setsubreg(paraloc^.register,R_SUBQ);
                             paraloc^.size:=OS_M64;
                           end;
                       end;
@@ -1124,7 +1124,7 @@ unit cpupara;
                               end;
                             else
                               begin
-                                subreg:=R_SUBMMWHOLE;
+                                subreg:=R_SUBQ;
                                 paraloc^.size:=OS_M64;
                               end;
                           end;

tests/webtbs/tw23962.pp

@@ -0,0 +1,46 @@
+{$MODE ObjFpc}
+
+uses classes;
+
+type
+
+TVector3 = packed record
+  X, Y, Z: Single;
+end;
+
+TClassA = class
+protected
+  fVector: TVector3;
+public
+  procedure SetVector(AVector: TVector3); virtual; abstract;
+end;
+
+{ TClassB }
+
+TClassB = class(TClassA)
+public
+  procedure SetVector(AVector: TVector3); override;
+end;
+
+{ TClassB }
+
+procedure TClassB.SetVector(AVector: TVector3);
+begin
+  writeln('TClassB: ',AVector.X,',',AVector.Y,',',AVector.Z);
+  fVector:=AVector;
+end;
+
+var
+  MyVector: TVector3;
+  MyClassB: TClassB;
+begin
+  MyVector.X:=0;
+  MyVector.Y:=0;
+  MyVector.Z:=3;
+  MyClassB:=TClassB.Create;
+  MyClassB.SetVector(MyVector);
+  if (MyClassB.fvector.x<>0) or
+     (MyClassB.fvector.y<>0) or
+     (MyClassB.fvector.z<>3) then
+    halt(1);
+end.

tests/webtbs/tw24007.pp

@@ -0,0 +1,21 @@
+var
+    str: bitpacked array [1..6] of 'a'..'z';
+    i: integer;
+    ch: char;
+    error: boolean;
+begin
+    error := false;
+    for i := 1 to 6 do str[i] := chr(ord('a')+i-1);
+    
+    for i := 1 to 6 do begin
+        write('str[i] = ''', str[i], '''; ord(str[2]) = ',ord(str[i]));
+	ch:=str[i]; {if we had used directly str[i] in the expression below, the correct value would have been read}
+	if ch <> chr(ord(str[i])) then
+          begin
+           write(' ==> Bug: chr(',ord(ch),') read, excpected chr(',ord('a')+i-1,')');
+           error:=true;
+          end;
+	writeln;
+    end;
+  halt(ord(error));
+end.