Preparations to native threadvar support:

- i386/cgcpu.pas: removed segment check, rejecting references with segment here is too early. These references are passed to tcgx86.a_loadaddr_ref_reg, which can generate required code for them (or reject if they are not allowed for the target).
- ncgld.pas: removed "not tf_section_threadvars in target_info" condition, it is inverse to one on the following line, making non-generic branch impossible to execute.
+ Define FPC_SECTION_THREADVARS macro if corresponding flag is set for the target.

git-svn-id: trunk@21210 -

compiler/i386/cgcpu.pas

@@ -221,8 +221,6 @@ unit cgcpu;
       begin
         with r do
           begin
-            if (segment<>NR_NO) then
-              cgmessage(cg_e_cant_use_far_pointer_there);
             if use_push(cgpara) then
               begin
                 cgpara.check_simple_location;

compiler/ncgld.pas

@@ -326,8 +326,7 @@ implementation
                    reference_reset_base(location.reference,hregister,0,location.reference.alignment);
                  end
                { Thread variable }
-               else if (vo_is_thread_var in gvs.varoptions) and
-                       not(tf_section_threadvars in target_info.flags) then
+               else if (vo_is_thread_var in gvs.varoptions) then
                  begin
                     if (tf_section_threadvars in target_info.flags) then
                       begin

compiler/options.pas

@@ -2502,6 +2502,12 @@ begin
     else
       undef_system_macro('FPC_NO_GENERIC_STACK_CHECK');
 
+  if (tf_section_threadvars in target_info.flags) then
+    if def then
+      def_system_macro('FPC_SECTION_THREADVARS')
+    else
+      undef_system_macro('FPC_SECTION_THREADVARS');
+
   { Code generation flags }
   if def and
      (tf_pic_default in target_info.flags) then