* some mips rtl compilation issues fixed

git-svn-id: trunk@20277 -

.gitattributes

@@ -7669,6 +7669,8 @@ rtl/macos/sysutils.pp svneol=native#text/plain
 rtl/mips/int64p.inc svneol=native#text/plain
 rtl/mips/makefile.cpu svneol=native#text/plain
 rtl/mips/math.inc svneol=native#text/plain
+rtl/mips/mathu.inc svneol=native#text/plain
+rtl/mips/mathuh.inc svneol=native#text/plain
 rtl/mips/mips.inc svneol=native#text/plain
 rtl/mips/set.inc svneol=native#text/plain
 rtl/mips/setjump.inc svneol=native#text/plain

rtl/linux/bunxsysc.inc

@@ -545,11 +545,18 @@ begin
 {$ifdef CPU64}
   Fppread:=do_syscall(syscall_nr_pread64,Fd,TSysParam(buf),nbytes,TSysParam(OffSet));
 {$else}
+{$ifdef CPUMIPS32}
+  Fppread:=do_syscall(syscall_nr_pread64,Fd,TSysParam(buf),nbytes,0,  { align parameters as required with dummy }
+    {$ifdef FPC_BIG_ENDIAN}    hi(offset),lo(offset){$endif}
+    {$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
+   );
+{$else CPUMIPS32}
   Fppread:=do_syscall(syscall_nr_pread,Fd,TSysParam(buf),nbytes,
     {$ifdef FPC_ABI_EABI}      0,  { align parameters as required with dummy } {$endif FPC_ABI_EABI}
     {$ifdef FPC_BIG_ENDIAN}    hi(offset),lo(offset){$endif}
     {$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
    );
+{$endif CPUMIPS32}
 {$endif}
 end;
 
@@ -559,11 +566,17 @@ begin
 {$ifdef CPU64}
   Fppwrite:=do_syscall(syscall_nr_pwrite64,Fd,TSysParam(buf),nbytes,TSysParam(OffSet));
 {$else}
-  Fppwrite:=do_syscall(syscall_nr_pwrite,Fd,TSysParam(buf),nbytes,
+{$ifdef CPUMIPS32}
+  Fppwrite:=do_syscall(syscall_nr_pwrite64,Fd,TSysParam(buf),nbytes,
     {$ifdef FPC_ABI_EABI}      0,  { align parameters as required with dummy } {$endif FPC_ABI_EABI}
     {$ifdef FPC_BIG_ENDIAN}    hi(offset),lo(offset){$endif}
     {$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
    );
+{$else CPUMIPS32}
+  Fppwrite:=do_syscall(syscall_nr_pwrite,Fd,TSysParam(buf),nbytes,0,  { align parameters as required with dummy }
+    {$ifdef FPC_BIG_ENDIAN}    hi(offset),lo(offset){$endif}
+    {$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
+{$endif CPUMIPS32}
 {$endif}
 end;
 

rtl/linux/termios.inc

@@ -1222,6 +1222,246 @@ Const
 
 {$endif cpuarm}
 
+
+{$ifdef cpumips}
+const
+  TCGETA = $5401;
+  TCSETA = $5402;
+  TCSETAW = $5403;
+  TCSETAF = $5404;
+  TCSBRK = $5405;
+  TCXONC = $5406;
+  TCFLSH = $5407;
+  TCGETS = $540d;
+  TCSETS = $540e;
+  TCSETSW = $540f;
+  TCSETSF = $5410;
+
+  TIOCEXCL = $740d;
+  TIOCNXCL = $740e;
+  TIOCOUTQ = $7472;
+  TIOCSTI = $5472;
+  TIOCMGET = $741d;
+  TIOCMBIS = $741b;
+  TIOCMBIC = $741c;
+  TIOCMSET = $741a;
+  TIOCPKT = $5470;
+  TIOCPKT_DATA = $00;
+  TIOCPKT_FLUSHREAD = $01;
+  TIOCPKT_FLUSHWRITE = $02;
+  TIOCPKT_STOP = $04;
+  TIOCPKT_START = $08;
+  TIOCPKT_NOSTOP = $10;
+  TIOCPKT_DOSTOP = $20;
+  TIOCPKT_IOCTL = $40;
+  {$warning Check TIOCGWINSZ and TIOCSWINSZ on a real mips system }
+  TIOCGWINSZ = $5414;
+  TIOCSWINSZ = $5414;
+
+  TIOCNOTTY = $5471;
+  TIOCSETD = $7401;
+  TIOCGETD = $7400;
+  FIOCLEX = $6601;
+  FIONCLEX = $6602;
+  FIOASYNC = $667d;
+  FIONBIO = $667e;
+  FIOQSIZE = $667f;
+
+  TIOCGLTC = $7474;
+  TIOCSLTC = $7475;
+  {$warning Check TIOCGPGRP and TIOCSPGRP on a real mips system }
+  TIOCGPGRP = $540F;
+  TIOCSPGRP = $5410;
+
+  FIONREAD = $467f;
+  TIOCINQ = FIONREAD;
+  TIOCGETP = $7408;
+  TIOCSETP = $7409;
+  TIOCSETN = $740a;
+  TIOCSBRK = $5427;
+  TIOCCBRK = $5428;
+  TIOCGSID = $7416;
+  TIOCVHANGUP = $5437;
+  TIOCSCTTY = $5480;
+  TIOCGSOFTCAR = $5481;
+  TIOCSSOFTCAR = $5482;
+  TIOCLINUX = $5483;
+  TIOCGSERIAL = $5484;
+  TIOCSSERIAL = $5485;
+  TCSBRKP = $5486;
+  TIOCSERCONFIG = $5488;
+  TIOCSERGWILD = $5489;
+  TIOCSERSWILD = $548a;
+  TIOCGLCKTRMIOS = $548b;
+  TIOCSLCKTRMIOS = $548c;
+  TIOCSERGSTRUCT = $548d;
+  TIOCSERGETLSR = $548e;
+  TIOCSERGETMULTI = $548f;
+  TIOCSERSETMULTI = $5490;
+  TIOCMIWAIT = $5491;
+  TIOCGICOUNT = $5492;
+
+  VINTR = 0;
+  VQUIT = 1;
+  VERASE = 2;
+  VKILL = 3;
+  VMIN = 4;
+  VTIME = 5;
+  VEOL2 = 6;
+  VSWTC = 7;
+  VSWTCH = VSWTC;
+  VSTART = 8;
+  VSTOP = 9;
+  VSUSP = 10;
+
+
+const
+  VREPRINT = 12;
+  VDISCARD = 13;
+  VWERASE = 14;
+  VLNEXT = 15;
+  VEOF = 16;
+  VEOL = 17;
+
+  IGNBRK = $0000001;
+  BRKINT = $0000002;
+  IGNPAR = $0000004;
+  PARMRK = $0000010;
+  INPCK = $0000020;
+  ISTRIP = $0000040;
+  INLCR = $0000100;
+  IGNCR = $0000200;
+  ICRNL = $0000400;
+  IUCLC = $0001000;
+  IXON = $0002000;
+  IXANY = $0004000;
+  IXOFF = $0010000;
+  IMAXBEL = $0020000;
+  IUTF8 = $0040000;
+
+  OPOST = $0000001;
+  OLCUC = $0000002;
+
+  ONLCR = $0000004;
+  OCRNL = $0000010;
+  ONOCR = $0000020;
+  ONLRET = $0000040;
+  OFILL = $0000100;
+  OFDEL = $0000200;
+  NLDLY = $0000400;
+  NL0 = $0000000;
+  NL1 = $0000400;
+  CRDLY = $0003000;
+  CR0 = $0000000;
+  CR1 = $0001000;
+  CR2 = $0002000;
+  CR3 = $0003000;
+  TABDLY = $0014000;
+  TAB0 = $0000000;
+  TAB1 = $0004000;
+  TAB2 = $0010000;
+  TAB3 = $0014000;
+  XTABS = $0014000;
+  BSDLY = $0020000;
+  BS0 = $0000000;
+  BS1 = $0020000;
+  VTDLY = $0040000;
+  VT0 = $0000000;
+  VT1 = $0040000;
+  FFDLY = $0100000;
+  FF0 = $0000000;
+  FF1 = $0100000;
+
+
+  CBAUD = $0010017;
+
+  B0 = $0000000;
+  B50 = $0000001;
+  B75 = $0000002;
+  B110 = $0000003;
+  B134 = $0000004;
+  B150 = $0000005;
+  B200 = $0000006;
+  B300 = $0000007;
+  B600 = $0000010;
+  B1200 = $0000011;
+  B1800 = $0000012;
+  B2400 = $0000013;
+  B4800 = $0000014;
+  B9600 = $0000015;
+  B19200 = $0000016;
+  B38400 = $0000017;
+  EXTA = $B19200;
+  EXTB = $B38400;
+
+  CSIZE = $0000060;
+  CS5 = $0000000;
+  CS6 = $0000020;
+  CS7 = $0000040;
+  CS8 = $0000060;
+  CSTOPB = $0000100;
+  CREAD = $0000200;
+  PARENB = $0000400;
+  PARODD = $0001000;
+  HUPCL = $0002000;
+  CLOCAL = $0004000;
+  CBAUDEX = $0010000;
+  BOTHER = $0010000;
+  B57600 = $0010001;
+  B115200 = $0010002;
+  B230400 = $0010003;
+  B460800 = $0010004;
+  B500000 = $0010005;
+  B576000 = $0010006;
+  B921600 = $0010007;
+  B1000000 = $0010010;
+  B1152000 = $0010011;
+  B1500000 = $0010012;
+  B2000000 = $0010013;
+  B2500000 = $0010014;
+  B3000000 = $0010015;
+  B3500000 = $0010016;
+  B4000000 = $0010017;
+
+  CIBAUD = $002003600000;
+  CMSPAR = $010000000000;
+  CRTSCTS = $020000000000;
+  IBSHIFT = 16;
+
+  ISIG = $0000001;
+  ICANON = $0000002;
+  XCASE = $0000004;
+  ECHO = $0000010;
+  ECHOE = $0000020;
+  ECHOK = $0000040;
+  ECHONL = $0000100;
+  NOFLSH = $0000200;
+  IEXTEN = $0000400;
+  ECHOCTL = $0001000;
+  ECHOPRT = $0002000;
+  ECHOKE = $0004000;
+  FLUSHO = $0020000;
+  PENDIN = $0040000;
+  TOSTOP = $0100000;
+  ITOSTOP = TOSTOP;
+  EXTPROC = $0200000;
+  TIOCSER_TEMT = $01;
+
+  TCOOFF = 0;
+  TCOON = 1;
+  TCIOFF = 2;
+  TCION = 3;
+
+
+  TCIFLUSH = 0;
+  TCOFLUSH = 1;
+  TCIOFLUSH = 2;
+
+  TCSANOW = TCSETS;
+  TCSADRAIN = TCSETSW;
+  TCSAFLUSH = TCSETSF;
+{$endif CPUMIPS}
+
 Type
   winsize = record
     ws_row,

rtl/mips/mathu.inc

@@ -0,0 +1,146 @@
+{
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 1999-2000 by Florian Klaempfl
+    member of the Free Pascal development team
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+{ exported by the system unit }
+//!!!function get_fsr : dword;external name 'FPC_GETFSR';
+//!!!procedure set_fsr(fsr : dword);external name 'FPC_SETFSR';
+
+function FPUExceptionMaskToSoftFloatMask(const Mask: TFPUExceptionMask): byte;
+begin
+    result:=0;
+    if exInvalidOp in Mask then
+      result:=result or (1 shl ord(exInvalidOp));
+    if exDenormalized in Mask then
+      result:=result or (1 shl ord(exDenormalized));
+    if exZeroDivide in Mask then
+      result:=result or (1 shl ord(exZeroDivide));
+    if exOverflow in Mask then
+      result:=result or (1 shl ord(exOverflow));
+    if exUnderflow in Mask then
+      result:=result or (1 shl ord(exUnderflow));
+    if exPrecision in Mask then
+      result:=result or (1 shl ord(exPrecision));
+end;
+
+function GetRoundMode: TFPURoundingMode;
+  begin
+//!!!    result:=TFPURoundingMode(get_fsr shr 30);
+  end;
+
+function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
+  begin
+    case (RoundMode) of
+      rmNearest :
+        softfloat_rounding_mode := float_round_nearest_even;
+      rmTruncate :
+        softfloat_rounding_mode := float_round_to_zero;
+      rmUp :
+        softfloat_rounding_mode := float_round_up;
+      rmDown :
+        softfloat_rounding_mode := float_round_down;
+    end;
+//!!!    set_fsr((get_fsr and $3fffffff) or (dword(RoundMode) shl 30));
+//!!!    result:=TFPURoundingMode(get_fsr shr 30);
+  end;
+
+
+function GetPrecisionMode: TFPUPrecisionMode;
+  begin
+    result:=pmDouble;
+  end;
+
+
+function SetPrecisionMode(const Precision: TFPUPrecisionMode): TFPUPrecisionMode;
+  begin
+    result:=pmDouble;
+  end;
+
+
+function GetExceptionMask: TFPUExceptionMask;
+  var
+    fsr : dword;
+  begin
+//!!!    fsr:=get_fsr;
+    result:=[];
+    { invalid operation: bit 27 }
+    if (fsr and (1 shl 27))=0 then
+      include(result,exInvalidOp);
+
+    { zero divide: bit 24 }
+    if (fsr and (1 shl 24))=0 then
+      include(result,exInvalidOp);
+
+    { overflow: bit 26 }
+    if (fsr and (1 shl 26))=0 then
+      include(result,exInvalidOp);
+
+    { underflow: bit 25 }
+    if (fsr and (1 shl 25))=0 then
+      include(result,exUnderflow);
+
+    { Precision (inexact result): bit 23 }
+    if (fsr and (1 shl 23))=0 then
+      include(result,exPrecision);
+  end;
+
+
+
+function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
+  var
+    fsr : dword;
+  begin
+//!!!    fsr:=get_fsr;
+
+    { invalid operation: bit 27 }
+    if (exInvalidOp in mask) then
+      fsr:=fsr and not(1 shl 27)
+    else
+      fsr:=fsr or (1 shl 27);
+
+    { zero divide: bit 24 }
+    if (exZeroDivide in mask) then
+      fsr:=fsr and not(1 shl 24)
+    else
+      fsr:=fsr or (1 shl 24);
+
+    { overflow: bit 26 }
+    if (exOverflow in mask) then
+      fsr:=fsr and not(1 shl 26)
+    else
+      fsr:=fsr or (1 shl 26);
+
+    { underflow: bit 25 }
+    if (exUnderflow in mask) then
+      fsr:=fsr and not(1 shl 25)
+    else
+      fsr:=fsr or (1 shl 25);
+
+    { Precision (inexact result): bit 23 }
+    if (exPrecision in mask) then
+      fsr:=fsr and not(1 shl 23)
+    else
+      fsr:=fsr or (1 shl 23);
+
+    { update control register contents }
+//!!!    set_fsr(fsr);
+
+    softfloat_exception_mask:=FPUExceptionMaskToSoftFloatMask(mask);
+  end;
+
+
+procedure ClearExceptions(RaisePending: Boolean =true);
+  begin
+//!!!    set_fsr(get_fsr and $fffffc1f);
+  end;
+

rtl/mips/mathuh.inc

@@ -0,0 +1,29 @@
+{
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 1999-2000 by Florian Klaempfl
+    member of the Free Pascal development team
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+ type
+  TFPURoundingMode = (rmNearest, rmDown, rmUp, rmTruncate);
+  TFPUPrecisionMode = (pmSingle, pmReserved, pmDouble, pmExtended);
+  TFPUException = (exInvalidOp, exDenormalized, exZeroDivide,
+                   exOverflow, exUnderflow, exPrecision);
+  TFPUExceptionMask = set of TFPUException;
+
+function GetRoundMode: TFPURoundingMode;
+function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
+function GetPrecisionMode: TFPUPrecisionMode;
+function SetPrecisionMode(const Precision: TFPUPrecisionMode): TFPUPrecisionMode;
+function GetExceptionMask: TFPUExceptionMask;
+function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
+procedure ClearExceptions(RaisePending: Boolean =true);
+