Merge branch source:main into main

compiler/msg/errore.msg

@@ -2696,6 +2696,9 @@ cg_w_interrupt_does_not_save_registers=06062_W_The target CPU does not support p
 cg_f_unknown_internal_procedure_number=06063_F_Unknown internal procedure number "$1"
 % The directive \var{internproc} is used with a number not known by the compiler. \var{internproc} should be used only by the
 % supplied RTL or by users really knowing what they are doing.
+cg_e_intrinsic_not_supported_by_instruction_set=06064_E_Intrinsic not supported by the currently selected instruction set
+% The intrinsic translates into an assembler instruction which is not supported by the instruction set
+% selected by \var{-Cp}
 %
 % \end{description}
 # EndOfTeX
@@ -4583,7 +4586,8 @@ P*2WT_Specify MPW tool type application (Classic Mac OS)
 **2Xf_Substitute pthread library name for linking (BSD)
 **2Xg_Create debuginfo in a separate file and add a debuglink section to executable
 **2Xi_Use internal linker
-L*2XlS<x>_LLVM utilties suffix (e.g. -7 in case clang is called clang-7)
+L*2XlS<x>_LLVM utilities suffix (e.g. -7 in case clang is called clang-7)
+W*2XlS<x>_LLVM utilities suffix (e.g. -17 in case llvm-mc is called llvm-mc-17)
 **2XLA_Define library substitutions for linking
 **2XLD_Exclude default order of standard libraries
 **2XLO_Define order of library linking

compiler/options.pas

@@ -4286,7 +4286,7 @@ begin
            else
              include(init_settings.globalswitches,cs_link_native);
          end;
-{$ifdef llvm}
+{$if defined(llvm) or defined(wasm32)}
        'l' :
          begin
            if j=length(more) then

compiler/riscv/cpuinfo.inc

@@ -0,0 +1,70 @@
+{
+    Copyright (c) 1998-2002 by the Free Pascal development team
+
+    Basic Processor information common for all RiscV variants
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+type
+  bestreal = double;
+  bestrealrec = TDoubleRec;
+  ts32real = single;
+  ts64real = double;
+  ts80real = extended;
+  ts128real = extended;
+  ts64comp = comp;
+
+  pbestreal = ^bestreal;
+
+  tcpuflags =
+     (CPURV_HAS_MUL,
+      CPURV_HAS_ATOMIC,
+      CPURV_HAS_COMPACT,
+      CPURV_HAS_16REGISTERS,
+      CPURV_HAS_ZBA,
+      CPURV_HAS_ZBB,
+      CPURV_HAS_ZBC,
+      CPURV_HAS_ZBS,
+      CPURV_HAS_ZBKB,
+      CPURV_HAS_ZBKC,
+      CPURV_HAS_ZBKX,
+      CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
+      CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
+      CPURV_HAS_ZIHINTPAUSE,
+      CPURV_HAS_F,
+      CPURV_HAS_D,
+      CPURV_HAS_Q,
+      CPURV_HAS_ZFH,
+      CPURV_HAS_ZFHMIN,
+      CPURV_HAS_ZFA,
+      CPURV_HAS_ZFINX,
+      CPURV_HAS_ZDINX,
+      CPURV_HAS_ZHINX,
+      CPURV_HAS_ZHINXMIN,
+      CPURV_HAS_ZICOND,
+      CPURV_HAS_ZMMUL
+     );
+
+  tfputype =
+    (fpu_none,
+    fpu_libgcc,
+    fpu_soft,
+    fpu_fd
+    );
+
+const
+  fputypestr: array[tfputype] of string[8] = (
+    'NONE',
+    'LIBGCC',
+    'SOFT',
+    'FD'
+    );
+
+

compiler/riscv/nrvinl.pas

@@ -83,7 +83,11 @@ implementation
          Result:=nil;
          case inlinenumber of
            in_riscv_pause:
-             resultdef:=voidtype;
+             begin
+               if not(CPURV_HAS_ZIHINTPAUSE in cpu_capabilities[current_settings.cputype]) then
+                 Message(cg_e_intrinsic_not_supported_by_instruction_set);
+               resultdef:=voidtype;
+             end;
            else
              result:=inherited;
          end;

compiler/riscv/nrvutil.pas

@@ -93,6 +93,8 @@ implementation
             attr_arch:=attr_arch+'_zicsr2p0';
           if CPURV_HAS_FETCH_FENCE in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zifencei2p0';
+          if CPURV_HAS_ZIHINTPAUSE in cpu_capabilities[current_settings.cputype] then
+            attr_arch:=attr_arch+'_zihintpause1p0';
           if CPURV_HAS_ZMMUL in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zmmul1p0';
           if CPURV_HAS_ZFA in cpu_capabilities[current_settings.cputype] then

compiler/riscv32/cpuinfo.pas

@@ -21,17 +21,9 @@ Interface
   uses
     globtype;
 
-Type
-   bestreal = double;
-   bestrealrec = TDoubleRec;
-   ts32real = single;
-   ts64real = double;
-   ts80real = extended;
-   ts128real = extended;
-   ts64comp = comp;
-
-   pbestreal=^bestreal;
+{$I ../riscv/cpuinfo.inc}
 
+Type
    { possible supported processors for this target }
    tcputype =
       (cpu_none,
@@ -52,13 +44,6 @@ Type
        cpu_rv32gcb
       );
 
-   tfputype =
-     (fpu_none,  
-      fpu_libgcc,
-      fpu_soft,
-      fpu_fd
-     );
-
    tcontrollertype =
      (ct_none,
       ct_fe310g000,
@@ -191,13 +176,6 @@ Const
      'RV32GCB'
    );
 
-   fputypestr : array[tfputype] of string[8] = (         
-     'LIBGCC',
-     'NONE',
-     'SOFT',
-     'FD'
-   );
-
    { Supported optimizations, only used for information }
    supported_optimizerswitches = genericlevel1optimizerswitches+
                                  genericlevel2optimizerswitches+
@@ -213,35 +191,6 @@ Const
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe]; 
 
- type
-   tcpuflags =
-      (CPURV_HAS_MUL,
-       CPURV_HAS_ATOMIC,
-       CPURV_HAS_COMPACT,
-       CPURV_HAS_16REGISTERS,
-       CPURV_HAS_ZBA,
-       CPURV_HAS_ZBB,
-       CPURV_HAS_ZBC,
-       CPURV_HAS_ZBS,
-       CPURV_HAS_ZBKB,
-       CPURV_HAS_ZBKC,
-       CPURV_HAS_ZBKX,
-       CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
-       CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
-       CPURV_HAS_F,
-       CPURV_HAS_D,
-       CPURV_HAS_Q,
-       CPURV_HAS_ZFH,
-       CPURV_HAS_ZFHMIN,
-       CPURV_HAS_ZFA,
-       CPURV_HAS_ZFINX,
-       CPURV_HAS_ZDINX,
-       CPURV_HAS_ZHINX,
-       CPURV_HAS_ZHINXMIN,
-       CPURV_HAS_ZICOND,
-       CPURV_HAS_ZMMUL
-      );
-
  const
    cpu_capabilities : array[tcputype] of set of tcpuflags =
      ( { cpu_none      } [],

compiler/riscv64/cpuinfo.pas

@@ -21,17 +21,9 @@ interface
 uses
   globtype;
 
-type
-  bestreal = double;
-  bestrealrec = TDoubleRec;
-  ts32real = single;
-  ts64real = double;
-  ts80real = extended;
-  ts128real = extended;
-  ts64comp = comp;
-
-  pbestreal = ^bestreal;
+{$I ../riscv/cpuinfo.inc}
 
+type
   { possible supported processors for this target }
   tcputype = (cpu_none,
     cpu_rv64imac,
@@ -44,23 +36,15 @@ type
     cpu_rv64gcb
   );
 
-  tfputype =
-    (fpu_none,
-    fpu_libgcc,
-    fpu_soft,
-    fpu_fd
+  tcontrollertype =
+    (ct_none
     );
 
-   tcontrollertype =
-     (ct_none
-     );
-
-   tcontrollerdatatype = record
-      controllertypestr, controllerunitstr: string[20];
-      cputype: tcputype; fputype: tfputype;
-      flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
-   end;
-
+  tcontrollerdatatype = record
+     controllertypestr, controllerunitstr: string[20];
+     cputype: tcputype; fputype: tfputype;
+     flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
+  end;
 
 Const
   { Is there support for dealing with multiple microcontrollers available }
@@ -101,13 +85,6 @@ Const
     'RV64GCB'
     );
 
-  fputypestr: array[tfputype] of string[8] = (
-    'NONE',
-    'LIBGCC',
-    'SOFT',
-    'FD'
-    );
-
    { Supported optimizations, only used for information }
    supported_optimizerswitches = genericlevel1optimizerswitches+
                                  genericlevel2optimizerswitches+
@@ -124,35 +101,6 @@ Const
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe];
 
- type
-   tcpuflags =
-      (CPURV_HAS_MUL,
-       CPURV_HAS_ATOMIC,
-       CPURV_HAS_COMPACT,
-       CPURV_HAS_16REGISTERS,
-       CPURV_HAS_ZBA,
-       CPURV_HAS_ZBB,
-       CPURV_HAS_ZBC,
-       CPURV_HAS_ZBS,
-       CPURV_HAS_ZBKB,
-       CPURV_HAS_ZBKC,
-       CPURV_HAS_ZBKX,
-       CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
-       CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
-       CPURV_HAS_F,
-       CPURV_HAS_D,
-       CPURV_HAS_Q,
-       CPURV_HAS_ZFH,
-       CPURV_HAS_ZFHMIN,
-       CPURV_HAS_ZFA,
-       CPURV_HAS_ZFINX,
-       CPURV_HAS_ZDINX,
-       CPURV_HAS_ZHINX,
-       CPURV_HAS_ZHINXMIN,
-       CPURV_HAS_ZICOND,
-       CPURV_HAS_ZMMUL
-      );
-
  const
    cpu_capabilities : array[tcputype] of set of tcpuflags =
      ( { cpu_none       } [],

compiler/utils/vppcx64.pp

@@ -127,7 +127,10 @@ begin
       CompilerName:=DefaultCompilerName;
     end;
 
-  FullCompilerName:=filesearch(CompilerName,Dir+PathSep+GetEnvironmentVariable('PATH'));
+  if FileExists(Dir+CompilerName) then
+    FullCompilerName:=Dir+CompilerName
+  else
+    FullCompilerName:=filesearch(CompilerName,Dir+PathSep+GetEnvironmentVariable('PATH'));
 
   if FullCompilerName='' then
     begin

compiler/wasm32/agllvmmc.pas

@@ -596,7 +596,7 @@ implementation
          asmbin : 'llvm-mc';
          asmcmd : '--assemble --arch=wasm32 -mattr=+sign-ext,+exception-handling,+bulk-memory,+atomics,+reference-types --filetype=obj --no-type-check -o $OBJ $EXTRAOPT $ASM';
          supported_targets : [system_wasm32_embedded,system_wasm32_wasip1,system_wasm32_wasip1threads,system_wasm32_wasip2];
-         flags : [af_smartlink_sections];
+         flags : [af_smartlink_sections, af_llvm];
          labelprefix : '.L';
          labelmaxlen : -1;
          comment : '# ';