-- Zusammenführen der Unterschiede zwischen Projektarchiv-URLs in ».«:

U    rtl/objpas/sysutils/dati.inc
U    rtl/objpas/sysutils/syssbh.inc
U    rtl/objpas/sysutils/sysstrh.inc
U    rtl/objpas/sysutils/filutil.inc
U    rtl/objpas/sysutils/syshelp.inc
U    rtl/arm/mathu.inc
U    rtl/win/wininc/redef.inc
U    rtl/win/systhrd.inc
U    rtl/aarch64/math.inc
U    rtl/linux/ossysc.inc
U    rtl/linux/ostypes.inc
U    rtl/linux/system.pp
U    rtl/linux/m68k/sysnr.inc
U    rtl/linux/m68k/gprt0.as
U    rtl/linux/m68k/gprt21.as
U    rtl/objpas/sysutils/datih.inc
U    rtl/objpas/sysconst.pp
U    rtl/win/sysutils.pp
U    rtl/win/wininc/struct.inc
U    rtl/aarch64/mathu.inc
U    rtl/linux/m68k/sighnd.inc
D    rtl/linux/m68k/cprt21.as
U    rtl/linux/riscv64/si_c.inc
U    rtl/linux/riscv64/si_prc.inc
U    rtl/linux/xtensa/si_c.inc
U    rtl/linux/xtensa/si_prc.inc
U    rtl/linux/Makefile
U    rtl/linux/t_linux.h2paschk
U    rtl/linux/arm/sysnr.inc
U    rtl/linux/i386/sysnr.inc
U    rtl/linux/i386/sighnd.inc
U    rtl/linux/powerpc/sysnr.inc
U    rtl/linux/powerpc64/sysnr.inc
U    rtl/linux/sparcgen/sysnr.inc
U    rtl/linux/x86_64/sysnr.inc
U    rtl/linux/x86_64/sighnd.inc
U    rtl/linux/Makefile.fpc
U    rtl/objpas/classes/classesh.inc
U    rtl/objpas/classes/streams.inc
U    rtl/objpas/classes/classes.inc
U    rtl/objpas/sysutils/syssb.inc
U    rtl/objpas/sysutils/sysstr.inc
A    rtl/objpas/sysutils/tzenv.inc
U    rtl/objpas/sysutils/filutilh.inc
U    rtl/objpas/sysutils/syshelph.inc
U    rtl/win/syswin.inc
U    rtl/win/wininc/base.inc
U    rtl/win/sysfile.inc
U    rtl/aarch64/aarch64.inc
U    rtl/i386/cpu.pp
U    rtl/powerpc/mathu.inc
U    rtl/i386/mathu.inc
U    rtl/mips/mathu.inc
U    rtl/m68k/mathu.inc
U    rtl/riscv64/mathu.inc
U    rtl/i8086/mathu.inc
U    rtl/powerpc64/mathu.inc
U    rtl/sparc64/mathu.inc
U    rtl/xtensa/mathu.inc
U    rtl/inc/genmath.inc
U    rtl/inc/ustrings.inc
U    rtl/inc/text.inc
U    rtl/inc/ufloatx80.pp
U    rtl/inc/except.inc
U    rtl/freertos/xtensa/esp8266.pp
U    rtl/unix/sysutils.pp
U    rtl/sparc/mathu.inc
U    rtl/x86_64/math.inc
U    rtl/inc/gencurr.inc
U    rtl/inc/ustringh.inc
U    rtl/inc/file.inc
U    rtl/inc/ufloat128.pp
U    rtl/inc/threadvr.inc
U    rtl/darwin/Makefile.fpc
U    rtl/unix/dos.pp
U    rtl/x86_64/cpu.pp
U    rtl/inc/currh.inc
U    rtl/inc/systemh.inc
U    rtl/inc/threadh.inc
U    rtl/inc/textrec.inc
U    rtl/inc/iso7185.pp
U    rtl/darwin/Makefile
U    rtl/unix/cwstring.pp
U    rtl/x86_64/mathu.inc
U    rtl/inc/astrings.inc
U    rtl/inc/system.inc
U    rtl/inc/thread.inc
U    rtl/inc/filerec.inc
U    rtl/inc/softfpu.pp
U    rtl/darwin/aarch64/sighnd.inc
U    rtl/freertos/Makefile
U    rtl/unix/unixutil.pp
U    rtl/unix/cthreads.pp
U    rtl/unix/unix.pp
U    rtl/unix/bunxovl.inc
U    rtl/unix/timezone.inc
U    rtl/unix/scripts/check_rtl_types.sh
U    rtl/aix/Makefile.fpc
U    rtl/aros/Makefile
U    rtl/beos/Makefile
U    rtl/bsd/sysos.inc
U    rtl/emx/Makefile.fpc
U    rtl/go32v2/Makefile
U    rtl/haiku/x86_64/sighnd.inc
U    rtl/morphos/Makefile
U    rtl/msdos/Makefile
U    rtl/aix/Makefile
U    rtl/amiga/buildrtl.pp
U    rtl/atari/Makefile
U    rtl/beos/Makefile.fpc
U    rtl/emx/Makefile
U    rtl/go32v2/v2prt0.as
U    rtl/haiku/i386/sighnd.inc
U    rtl/macos/Makefile.fpc
U    rtl/msdos/sysutils.pp
U    rtl/amiga/Makefile.fpc
U    rtl/aros/buildrtl.pp
U    rtl/beos/i386/sighnd.inc
U    rtl/emx/sysutils.pp
U    rtl/go32v2/sysutils.pp
U    rtl/haiku/Makefile
U    rtl/macos/Makefile
U    rtl/morphos/buildrtl.pp
U    rtl/amiga/Makefile
U    rtl/aros/Makefile.fpc
U    rtl/beos/bethreads.pp
U    rtl/embedded/Makefile
U    rtl/gba/Makefile
U    rtl/go32v2/Makefile.fpc
U    rtl/haiku/Makefile.fpc
U    rtl/morphos/Makefile.fpc
U    rtl/msxdos/Makefile
A    rtl/sinclairql
U    rtl/nativent/buildrtl.pp
U    rtl/nativent/Makefile.fpc
U    rtl/nativent/Makefile
U    rtl/netware/Makefile
U    rtl/nds/Makefile
U    rtl/netware/Makefile.fpc
U    rtl/os2/sysutils.pp
A    rtl/sinclairql/system.pp
A    rtl/sinclairql/qdosfuncs.inc
A    rtl/sinclairql/buildrtl.pp
A    rtl/sinclairql/rtldefs.inc
U    rtl/solaris/Makefile
U    rtl/watcom/Makefile
U    rtl/wince/Makefile
U    rtl/Makefile
U    rtl/netware/systhrd.inc
U    rtl/netwlibc/Makefile.fpc
U    rtl/palmos/Makefile
A    rtl/sinclairql/sysfile.inc
A    rtl/sinclairql/Makefile.fpc
A    rtl/sinclairql/rtl.cfg
A    rtl/sinclairql/tthread.inc
U    rtl/watcom/sysutils.pp
U    rtl/win16/Makefile.fpc
U    rtl/zxspectrum/Makefile
U    rtl/netwlibc/systhrd.inc
U    rtl/os2/Makefile.fpc
A    rtl/sinclairql/qdos.inc
A    rtl/sinclairql/qdosh.inc
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A    rtl/sinclairql/sysosh.inc
U    rtl/symbian/Makefile
U    rtl/win16/Makefile
U    rtl/wince/Makefile.fpc
U    rtl/netwlibc/Makefile
U    rtl/os2/Makefile
A    rtl/sinclairql/si_prc.pp
A    rtl/sinclairql/Makefile
A    rtl/sinclairql/sysheap.inc
A    rtl/sinclairql/sysdir.inc
U    rtl/solaris/Makefile.fpc
U    rtl/wii/Makefile
U    rtl/wince/sysutils.pp
U    rtl/android/Makefile.fpc
U    rtl/android/unixandroid.inc
U    rtl/android/jvm/Makefile
U    rtl/android/Makefile
U    rtl/dragonfly/Makefile
U    rtl/freebsd/Makefile.fpc
U    rtl/java/jsystemh.inc
U    rtl/netbsd/Makefile.fpc
U    rtl/openbsd/x86_64/sighnd.inc
U    rtl/qnx/osposix.inc
U    rtl/qnx/signal.inc
U    rtl/win32/buildrtl.pp
U    rtl/win64/system.pp
U    packages/regexpr/Makefile
U    rtl/freebsd/Makefile
U    rtl/java/Makefile
U    rtl/netbsd/x86_64/sighnd.inc
U    rtl/openbsd/i386/sighnd.inc
U    rtl/qnx/errno.inc
U    rtl/qnx/qnx.inc
U    rtl/win32/Makefile.fpc
U    rtl/win64/buildrtl.pp
U    packages/regexpr/tests/testregexpr.pp
U    rtl/dragonfly/Makefile.fpc
U    rtl/freebsd/x86_64/sighnd.inc
U    rtl/netbsd/i386/sighnd.inc
U    rtl/openbsd/Makefile.fpc
U    rtl/qnx/dos.inc
U    rtl/qnx/posix.pp
U    rtl/win32/Makefile
U    rtl/win64/Makefile.fpc
U    packages/regexpr/tests/tcregexp.pp
U    rtl/freebsd/i386/sighnd.inc
U    rtl/netbsd/Makefile
U    rtl/openbsd/Makefile
U    rtl/qnx/Makefile
U    rtl/qnx/osposixh.inc
U    rtl/qnx/system.pp
U    rtl/win64/Makefile
U    rtl/Makefile.fpc
U    packages/cocoaint/Makefile
U    packages/fcl-passrc/src/pasresolver.pp
U    packages/cocoaint/src/foundation/NSProcessInfo.inc
U    packages/fcl-passrc/src/pasresolveeval.pas
U    packages/regexpr/fpmake.pp
U    packages/fcl-passrc/src/pparser.pp
U    packages/regexpr/examples/Makefile
U    packages/fcl-passrc/src/pastree.pp
U    packages/fcl-passrc/src/pscanner.pp
U    packages/fcl-passrc/src/passrcutil.pp
U    packages/fcl-passrc/tests/tcuseanalyzer.pas
U    packages/fcl-passrc/tests/tcgenerics.pp
U    packages/fcl-passrc/tests/tcbaseparser.pas
U    packages/rtl-objpas/src/inc/widestrutils.pp
U    packages/rtl-objpas/Makefile
U    packages/pastojs/src/pas2jscompiler.pp
U    packages/pastojs/tests/tcfiler.pas
U    packages/fcl-passrc/src/paswrite.pp
U    packages/fcl-passrc/tests/tcscanner.pas
U    packages/fcl-passrc/tests/tctypeparser.pas
U    packages/fcl-passrc/tests/tcclasstype.pas
U    packages/rtl-objpas/src/inc/nullable.pp
U    packages/rtl-objpas/src/inc/stdconvs.pp
U    packages/pastojs/src/pas2jsfilecache.pp
U    packages/pastojs/src/pas2jsfs.pp
U    packages/pastojs/tests/tcoptimizations.pas
U    packages/fcl-passrc/src/pasuseanalyzer.pas
U    packages/fcl-passrc/tests/tcprocfunc.pas
A    packages/fcl-passrc/tests/tcpaswritestatements.pas
U    packages/fcl-passrc/tests/tconstparser.pas
U    packages/fcl-passrc/fpmake.pp
U    packages/rtl-objpas/src/inc/dateutil.inc
U    packages/pastojs/src/fppas2js.pp
U    packages/pastojs/src/pas2jspcucompiler.pp
U    packages/pastojs/tests/tcmodules.pas
U    packages/fcl-passrc/tests/tcresolver.pas
U    packages/fcl-passrc/tests/tcresolvegenerics.pas
U    packages/fcl-passrc/tests/tcvarparser.pas
U    packages/fcl-passrc/Makefile
U    packages/rtl-objpas/src/inc/strutils.pp
U    packages/pastojs/src/pas2jsfiler.pp
U    packages/pastojs/src/pas2jslibcompiler.pp
U    packages/pastojs/tests/tcgenerics.pas
U    packages/pastojs/tests/tcprecompile.pas
U    packages/hash/src/sha1.pp
U    packages/chm/src/chmls.lpi
U    packages/hash/tests/tests.pp
U    packages/hash/fpmake.pp
U    packages/pastojs/Makefile
U    packages/hash/examples/Makefile
U    packages/pastojs/tests/tcunitsearch.pas
U    packages/hash/Makefile
U    packages/chm/Makefile
U    packages/winunits-base/Makefile
U    packages/fcl-js/fpmake.pp
U    packages/fcl-res/src/rcparser.y
U    packages/fcl-res/Makefile
U    packages/fcl-net/src/sslsockets.pp
U    packages/fcl-net/fpmake.pp
U    packages/fcl-db/src/sqldb/interbase/Makefile
U    packages/fcl-db/src/sqldb/sqldb.pp
U    packages/chm/src/chmreader.pas
U    packages/winunits-base/src/comobj.pp
U    packages/fcl-js/Makefile
U    packages/fcl-res/src/rcparser.pas
U    packages/fcl-res/src/coffwriter.pp
U    packages/fcl-net/src/sslbase.pp
U    packages/fcl-net/examples/Makefile
U    packages/fcl-db/src/sqldb/interbase/ibconnection.pp
U    packages/fcl-db/src/sqldb/postgres/Makefile
U    packages/chm/src/itsftransform.pas
U    packages/winunits-base/src/activex.pp
U    packages/fcl-js/src/jstree.pp
U    packages/fcl-res/src/rclex.l
U    packages/fcl-res/src/cofftypes.pp
U    packages/fcl-net/src/cnetdb.pp
U    packages/fcl-net/Makefile
U    packages/fcl-db/src/sqldb/sqlite/Makefile
U    packages/fcl-db/src/sqldb/postgres/pqconnection.pp
U    packages/chm/src/chmls.lpr
U    packages/chm/fpmake.pp
U    packages/fcl-js/src/jswriter.pp
U    packages/fcl-res/src/rclex.inc
U    packages/fcl-res/src/coffconsts.pp
U    packages/fcl-res/fpmake.pp
U    packages/fcl-net/src/ssockets.pp
U    packages/fcl-db/src/sqldb/sqlite/sqlite3conn.pp
U    packages/fcl-db/src/sqldb/interbase/fbadmin.pp
U    packages/fcl-db/src/sqldb/mysql/mysqlconn.inc
U    packages/fcl-db/src/sqldb/mysql/Makefile
U    packages/fcl-db/src/sqldb/mssql/Makefile
U    packages/fcl-db/src/sqldb/Makefile
U    packages/fcl-db/src/sqldb/odbc/Makefile
U    packages/fcl-db/src/base/dbconst.pas
U    packages/fcl-db/src/base/db.pas
U    packages/fcl-db/src/codegen/fpddcodegen.pp
U    packages/fcl-db/src/dbase/dbf_common.inc
U    packages/fcl-db/src/export/fprtfexport.pp
U    packages/fcl-db/src/paradox/Makefile
U    packages/fcl-db/Makefile
U    packages/fcl-db/tests/sqldbtoolsunit.pas
U    packages/fpmkunit/Makefile
U    packages/fcl-db/src/base/bufdataset.pas
U    packages/fcl-db/src/base/xmldatapacketreader.pp
U    packages/fcl-db/src/codegen/Makefile
U    packages/fcl-db/src/dbase/Makefile
U    packages/fcl-db/src/export/fpfixedexport.pp
U    packages/fcl-db/src/memds/Makefile
U    packages/fcl-db/src/sqlite/Makefile
U    packages/fcl-db/tests/bufdatasettoolsunit.pas
U    packages/fpmkunit/src/fpmkunit.pp
U    packages/fcl-db/src/sqldb/oracle/Makefile
U    packages/fcl-db/src/base/sqlscript.pp
U    packages/fcl-db/src/base/dsparams.inc
U    packages/fcl-db/src/base/Makefile
U    packages/fcl-db/src/base/fields.inc
U    packages/fcl-db/src/datadict/Makefile
U    packages/fcl-db/src/dbase/dbf_fields.pas
U    packages/fcl-db/src/export/fptexexport.pp
U    packages/fcl-db/src/sdf/Makefile
U    packages/fcl-db/tests/Makefile
U    packages/fcl-db/tests/testfieldtypes.pas
A    packages/qlunits
A    packages/qlunits/examples
A    packages/qlunits/src
A    packages/fcl-sound/tests
A    packages/fcl-sound/tests/data
A    packages/fcl-sound/tests/data/wav
A    packages/fcl-sound/tests/data/wav/reader
A    packages/fcl-sound/tests/data/wav/reader/valid
U    packages/paszlib/examples/Makefile
U    packages/paszlib/Makefile
U    packages/fpmkunit/fpmake.pp
U    packages/paszlib/fpmake.pp
A    packages/qlunits/src/qdos.pas
U    packages/fcl-sound/src/fpwavreader.pas
A    packages/fcl-sound/tests/data/wav/reader/valid/odd_fmt_size.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_16.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_64float.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32float.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_32float.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/euphoric_tape.wav.raw
A    packages/qlunits/fpmake.pp
A    packages/qlunits/README.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/odd_fmt_size.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_24.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_8.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_32float.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32float.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_32float.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/euphoric_tape.wav
A    packages/qlunits/Makefile
A    packages/qlunits/Makefile.fpc
A    packages/fcl-sound/tests/data/wav/reader/valid/odd_fmt_size.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16_tag.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_64float.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_32.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/euphoric_tape.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_64float.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_64float.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_24.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_16.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_32.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_24.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_8.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_24.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16_tag.wav
A    packages/fcl-sound/tests/tcwavreader.pas
U    packages/fcl-sound/fpmake.pp
U    packages/fcl-stl/src/gdeque.pp
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16_tag.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_8.wav
U    packages/fcl-sound/Makefile
U    packages/fcl-stl/src/gtree.pp
U    packages/fcl-db/src/datadict/fpdatadict.pp
U    packages/fcl-db/src/export/Makefile
U    packages/fcl-db/src/json/Makefile
U    packages/fcl-db/src/sql/Makefile
U    packages/fcl-db/tests/toolsunit.pas
U    packages/fcl-db/fpmake.pp
U    packages/paszlib/src/zipper.pp
A    packages/qlunits/examples/qlcube.pas
A    packages/qlunits/src/qlfloat.pas
U    packages/fcl-sound/src/fpwavformat.pas
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32float.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_24.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_8.wav.info.txt
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_64float.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_64float.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_16.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_32.wav
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_8.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32.wav
A    packages/fcl-sound/tests/testfclsound.lpr
U    packages/rtl-extra/Makefile
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_8.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32.wav.raw
A    packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_24.wav
A    packages/fcl-sound/tests/testfclsound.lpi
U    packages/rtl-extra/src/win/serial.pp
U    packages/fcl-stl/Makefile
U    packages/a52/Makefile
U    packages/aspell/Makefile
U    packages/Makefile
U    packages/fcl-stl/fpmake.pp
U    packages/amunits/Makefile
U    packages/bzip2/Makefile
U    packages/ami-extra/Makefile
U    packages/bfd/Makefile
U    packages/cairo/Makefile
U    packages/dbus/Makefile
U    packages/fastcgi/Makefile
U    packages/cdrom/examples/Makefile
U    packages/dbus/src/dbuscomp.pp
U    packages/fcl-base/Makefile
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U    packages/fcl-fpcunit/fpmake.pp
U    packages/fcl-json/Makefile
U    packages/fcl-json/src/fpjson.pp
U    packages/fcl-pdf/src/fppdf.pp
U    packages/cdrom/Makefile
U    packages/dbus/examples/Makefile
U    packages/fcl-async/Makefile
U    packages/fcl-registry/Makefile
U    packages/fcl-registry/fpmake.pp
U    packages/fcl-sdo/src/das/sdo_das_utils.pas
U    packages/fcl-web/src/base/fpjwt.pp
U    packages/fcl-web/src/webdata/Makefile
U    packages/fcl-xml/fpmake.pp
U    packages/arosunits/Makefile
U    packages/bzip2/fpmake.pp
U    packages/dblib/Makefile
U    packages/dts/Makefile
U    packages/fcl-base/examples/Makefile
U    packages/fcl-fpcunit/Makefile
U    packages/fcl-image/Makefile
U    packages/fcl-json/fpmake.pp
U    packages/fcl-json/tests/testjsonreader.pp
U    packages/fcl-pdf/fpmake.pp
U    packages/fcl-registry/tests/Makefile
U    packages/fcl-report/Makefile
U    packages/fcl-web/Makefile
U    packages/fcl-web/src/base/fphttpclient.pp
U    packages/fcl-web/src/restbridge/sqldbrestschema.pp
U    packages/fcl-xml/src/sax_xml.pp
U    packages/fpgtk/examples/Makefile
U    packages/fcl-base/fpmake.pp
U    packages/fcl-fpcunit/src/exampletests/Makefile
U    packages/fcl-image/examples/Makefile
U    packages/fcl-json/src/jsonscanner.pp
U    packages/fcl-json/tests/testjsondata.pp
U    packages/fcl-process/Makefile
U    packages/fcl-registry/src/xregreg.inc
U    packages/fcl-sdo/Makefile
U    packages/fcl-web/src/base/Makefile
U    packages/fcl-web/src/base/custmicrohttpapp.pp
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U    utils/pas2jni/Makefile
U    utils/unicode/Makefile
U    compiler/llvm/llvmtype.pas
U    compiler/llvm/llvmpi.pas
U    compiler/ppu.pas
U    compiler/utils/samplecfg
U    compiler/utils/ppumove.pp
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U    compiler/i386/i386prop.inc
U    compiler/utils/gena64vfp.pp
U    compiler/i386/aoptcpu.pas
U    compiler/htypechk.pas
U    compiler/i386/i386atts.inc
U    compiler/i386/cpuelf.pas
U    compiler/i386/n386flw.pas
U    compiler/i386/cpuinfo.pas
U    compiler/i386/i386tab.inc
U    compiler/i386/hlcgcpu.pas
U    compiler/i386/i386int.inc
U    compiler/x86/nx86inl.pas
U    compiler/x86/nx86mat.pas
U    compiler/x86/agx86nsm.pas
U    compiler/x86/agx86int.pas
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U    compiler/x86_64/x8664att.inc
C    compiler/i386/i386nop.inc
U    compiler/i386/cpupara.pas
U    compiler/i386/n386mat.pas
U    compiler/x86/rgx86.pas
U    compiler/x86/cpubase.pas
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U    compiler/x86/nx86add.pas
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U    compiler/x86_64/x8664ats.inc
U    compiler/x86_64/cpuelf.pas
U    compiler/x86/aoptx86.pas
U    compiler/x86/x86ins.dat
U    compiler/x86/cgx86.pas
U    compiler/x86/rax86.pas
U    compiler/x86/symx86.pas
U    compiler/x86_64/cpuinfo.pas
U    compiler/x86_64/x8664tab.inc
U    compiler/i386/i386att.inc
U    compiler/i386/cgcpu.pas
U    compiler/i386/n386add.pas
U    compiler/i386/i386op.inc
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U    compiler/x86/rax86int.pas
U    compiler/x86/agx86att.pas
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U    compiler/x86_64/win64unw.pas
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U    compiler/x86_64/nx64flw.pas
U    compiler/nadd.pas
U    compiler/pgenutil.pas
U    compiler/avr/cgcpu.pas
U    compiler/avr/navrmat.pas
U    compiler/dirparse.pas
U    compiler/symbase.pas
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U    compiler/m68k/n68kcal.pas
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U    compiler/xtensa/ncpumat.pas
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C    compiler/i8086/i8086nop.inc
U    compiler/i8086/hlcgcpu.pas
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U    compiler/aarch64/cpupara.pas
U    compiler/aarch64/cpubase.pas
U    compiler/aarch64/a64op.inc
U    compiler/aarch64/ra64dwa.inc
U    compiler/nflw.pas
U    compiler/i8086/i8086atts.inc
U    compiler/i8086/cpupara.pas
U    compiler/i8086/n8086ld.pas
U    compiler/i8086/i8086int.inc
U    compiler/aarch64/agcpugas.pas
U    compiler/aarch64/ncpuinl.pas
U    compiler/aarch64/a64ins.dat
U    compiler/aarch64/ra64con.inc
U    compiler/xtensa/racpugas.pas
U    compiler/i8086/i8086att.inc
U    compiler/i8086/cgcpu.pas
U    compiler/i8086/n8086inl.pas
U    compiler/i8086/symcpu.pas
U    compiler/aarch64/ncpumat.pas
U    compiler/aarch64/aasmcpu.pas
U    compiler/aarch64/a64atts.inc
U    compiler/aarch64/cgcpu.pas
U    compiler/aarch64/ra64num.inc
U    compiler/xtensa/ncpumem.pas
U    compiler/i8086/n8086con.pas
U    compiler/i8086/i8086tab.inc
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U    compiler/i8086/n8086mem.pas
U    compiler/symdef.pas
U    compiler/aarch64/aoptcpu.pas
U    compiler/aarch64/a64att.inc
U    compiler/aarch64/a64reg.dat
U    compiler/aarch64/ra64nor.inc
U    compiler/aarch64/ra64sri.inc
U    compiler/aarch64/racpu.pas
U    compiler/aarch64/ra64rni.inc
U    compiler/aarch64/ra64sup.inc
U    compiler/aarch64/ra64std.inc
U    compiler/aarch64/ra64sta.inc
U    compiler/aarch64/racpugas.pas
U    compiler/sparcgen/cgsparc.pas
U    compiler/sparcgen/racpugas.pas
U    compiler/verbose.pas
U    compiler/pass_2.pas
U    compiler/systems/i_linux.pas
A    compiler/systems/i_sinclairql.pas
U    compiler/systems/t_win16.pas
U    compiler/link.pas
U    compiler/arm/aoptcpu.pas
U    compiler/aarch64/ncpuflw.pas
U    compiler/sparcgen/ncpucnv.pas
U    compiler/ncnv.pas
U    compiler/ncgflw.pas
U    compiler/systems/t_embed.pas
U    compiler/systems/t_zxspectrum.pas
U    compiler/systems/i_win.pas
U    compiler/cgobj.pas
U    compiler/optcse.pas
U    compiler/arm/cpubase.pas
U    compiler/aarch64/hlcgcpu.pas
U    compiler/sparcgen/cpugas.pas
U    compiler/nmat.pas
U    compiler/sparcgen/aasmcpu.pas
U    compiler/sparcgen/rgcpu.pas
U    compiler/ncal.pas
U    compiler/systems/t_amiga.pas
A    compiler/systems/t_sinclairql.pas
U    compiler/systems/t_msdos.pas
U    compiler/node.pas
A    compiler/ppcppc64le.lpi
U    compiler/arm/armins.dat
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U    compiler/arm/cpupara.pas
U    compiler/arm/cpuelf.pas
U    compiler/arm/agarmgas.pas
U    compiler/arm/hlcgcpu.pas
U    compiler/arm/narminl.pas
U    compiler/arm/rgcpu.pas
U    compiler/z80/aasmcpu.pas
U    compiler/z80/aoptcpub.pas
U    compiler/z80/nz80add.pas
U    compiler/rautils.pas
U    compiler/nmem.pas
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U    compiler/z80/cpuinfo.pas
U    compiler/z80/aoptcpu.pas
U    compiler/z80/cpupara.pas
U    compiler/raatt.pas
U    compiler/scandir.pas
U    compiler/arm/narmld.pas
U    compiler/aoptobj.pas
U    compiler/z80/agsdasz80.pas
U    compiler/z80/cgcpu.pas
U    compiler/z80/tgcpu.pas
U    compiler/pdecl.pas
U    compiler/globtype.pas
C    compiler/msgtxt.inc
C    compiler/msgidx.inc
U    compiler/fppu.pas
U    compiler/options.pas
U    compiler/ncgbas.pas
U    compiler/systems/t_linux.pas
U    compiler/systems/t_atari.pas
U    compiler/systems/i_macos.pas
U    compiler/compinnr.pas
U    compiler/ncginl.pas
U    compiler/arm/armtab.inc
U    compiler/arm/cgcpu.pas
U    compiler/arm/narmadd.pas
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U    compiler/z80/raz80asm.pas
U    compiler/z80/agz80vasm.pas
U    compiler/z80/cpubase.pas
U    compiler/aasmtai.pas
U    compiler/symtype.pas
C    compiler/msg/errore.msg
U    compiler/ppc68k.lpi
U    compiler/entfile.pas
U    compiler/riscv/hlcgrv.pas
U    compiler/armgen/aoptarm.pas
U    compiler/ncon.pas
U    compiler/pinline.pas
U    compiler/cstreams.pas
U    compiler/ncgutil.pas
U    compiler/fpcdefs.inc
U    compiler/comphook.pas
U    compiler/Makefile
U    compiler/nbas.pas
U    compiler/systems.inc
U    compiler/aggas.pas
U    compiler/scanner.pas
U    compiler/globals.pas
U    compiler/assemble.pas
U    compiler/systems.pas
U    compiler/psystem.pas
U    compiler/cutils.pas
U    compiler/cepiktimer.pas
U    compiler/riscv/agrvgas.pas
A    compiler/comptty.pas
U    compiler/generic/cpuinfo.pas
U    compiler/pmodules.pas
U    compiler/aasmcnst.pas
U    compiler/cgbase.pas
U    compiler/powerpc/cgcpu.pas
U    compiler/powerpc/rappcgas.pas
U    compiler/fpcp.pas
U    compiler/jvm/hlcgcpu.pas
U    compiler/Makefile.fpc
U    compiler/aopt.pas
U    compiler/powerpc/cpupara.pas
U    compiler/powerpc/nppcadd.pas
U    compiler/cg64f32.pas
U    compiler/hlcgobj.pas
U    compiler/jvm/njvmcnv.pas
U    compiler/ncgmat.pas
U    compiler/ngenutil.pas
U    compiler/powerpc/cpupi.pas
U    compiler/aasmbase.pas
U    compiler/hlcg2ll.pas
U    compiler/jvm/jvmdef.pas
U    compiler/mips/aasmcpu.pas
U    compiler/mips/hlcgcpu.pas
U    compiler/ncgadd.pas
U    compiler/ogcoff.pas
U    compiler/optloadmodifystore.pas
U    compiler/pkgutil.pas
U    compiler/powerpc64/rappcgas.pas
U    compiler/ppcgen/ngppcadd.pas
U    compiler/riscv32/rarv32gas.pas
U    Makefile
U    compiler/jvm/njvmtcon.pas
U    compiler/mips/cpuelf.pas
U    compiler/mips/ncpuinln.pas
U    compiler/ngtcon.pas
U    compiler/ogrel.pas
U    compiler/pbase.pas
U    compiler/powerpc64/nppcadd.pas
U    compiler/ppcgen/cgppc.pas
U    compiler/ppcgen/rgcpu.pas
U    compiler/sparc/cgcpu.pas
U    compiler/powerpc/agppcmpw.pas
U    compiler/powerpc/nppcmat.pas
U    compiler/dbgdwarf.pas
U    compiler/jvm/agjasmin.pas
U    compiler/jvm/njvmmem.pas
U    compiler/mips/cgcpu.pas
U    compiler/mips/ncpucnv.pas
U    compiler/ncgcal.pas
U    compiler/ogomf.pas
U    compiler/optvirt.pas
U    compiler/powerpc64/cgcpu.pas
U    compiler/ppcgen/agppcgas.pas
U    compiler/ppcgen/ngppcinl.pas
U    compiler/riscv64/rarv64gas.pas
U    installer/Makefile
U    compiler/jvm/pjvm.pas
U    compiler/mips/cpugas.pas
U    compiler/mips/racpugas.pas
U    compiler/ogbase.pas
U    compiler/omfbase.pas
U    compiler/pdecobj.pas
U    compiler/powerpc64/nppcmat.pas
U    compiler/ppcgen/hlcgppc.pas
U    compiler/rgobj.pas
U    compiler/sparc64/cpugas.pas
 U   .
-- Aufzeichnung der Informationen für Zusammenführung zwischen Projektarchiv-URLs in ».«:
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git-svn-id: branches/tg74/avx512-0037785@48108 -

.gitattributes

@@ -167,6 +167,7 @@ compiler/comphook.pas svneol=native#text/plain
 compiler/compiler.pas svneol=native#text/plain
 compiler/compinnr.pas svneol=native#text/plain
 compiler/comprsrc.pas svneol=native#text/plain
+compiler/comptty.pas svneol=native#text/plain
 compiler/constexp.pas svneol=native#text/x-pascal
 compiler/cprofile.pas svneol=native#text/pascal
 compiler/crefs.pas svneol=native#text/plain
@@ -674,6 +675,7 @@ compiler/ppcmips64el.lpi svneol=native#text/plain
 compiler/ppcmipsel.lpi svneol=native#text/plain
 compiler/ppcppc.lpi svneol=native#text/plain
 compiler/ppcppc64.lpi svneol=native#text/plain
+compiler/ppcppc64le.lpi svneol=native#text/plain
 compiler/ppcriscv32.lpi svneol=native#text/plain
 compiler/ppcriscv64.lpi svneol=native#text/plain
 compiler/ppcsparc.lpi svneol=native#text/plain
@@ -871,6 +873,7 @@ compiler/systems/i_nwl.pas svneol=native#text/plain
 compiler/systems/i_nwm.pas svneol=native#text/plain
 compiler/systems/i_os2.pas svneol=native#text/plain
 compiler/systems/i_palmos.pas svneol=native#text/plain
+compiler/systems/i_sinclairql.pas svneol=native#text/plain
 compiler/systems/i_sunos.pas svneol=native#text/plain
 compiler/systems/i_symbian.pas svneol=native#text/plain
 compiler/systems/i_watcom.pas svneol=native#text/plain
@@ -906,6 +909,7 @@ compiler/systems/t_nwl.pas svneol=native#text/plain
 compiler/systems/t_nwm.pas svneol=native#text/plain
 compiler/systems/t_os2.pas svneol=native#text/plain
 compiler/systems/t_palmos.pas svneol=native#text/plain
+compiler/systems/t_sinclairql.pas svneol=native#text/plain
 compiler/systems/t_sunos.pas svneol=native#text/plain
 compiler/systems/t_symbian.pas svneol=native#text/plain
 compiler/systems/t_watcom.pas svneol=native#text/plain
@@ -3859,6 +3863,7 @@ packages/fcl-passrc/tests/tcgenerics.pp svneol=native#text/plain
 packages/fcl-passrc/tests/tcmoduleparser.pas svneol=native#text/plain
 packages/fcl-passrc/tests/tconstparser.pas svneol=native#text/plain
 packages/fcl-passrc/tests/tcpassrcutil.pas svneol=native#text/plain
+packages/fcl-passrc/tests/tcpaswritestatements.pas svneol=native#text/plain
 packages/fcl-passrc/tests/tcprocfunc.pas svneol=native#text/plain
 packages/fcl-passrc/tests/tcresolvegenerics.pas svneol=native#text/plain
 packages/fcl-passrc/tests/tcresolver.pas svneol=native#text/plain
@@ -4314,6 +4319,54 @@ packages/fcl-sound/fpmake.pp svneol=native#text/plain
 packages/fcl-sound/src/fpwavformat.pas svneol=native#text/plain
 packages/fcl-sound/src/fpwavreader.pas svneol=native#text/plain
 packages/fcl-sound/src/fpwavwriter.pas svneol=native#text/plain
+packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16.wav -text svneol=unset#audio/x-wav
+packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16.wav.info.txt svneol=native#text/plain
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+packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_16_tag.wav.raw -text
+packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_24.wav -text svneol=unset#audio/x-wav
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+packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32.wav -text svneol=unset#audio/x-wav
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+packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32.wav.raw -text
+packages/fcl-sound/tests/data/wav/reader/valid/44k_mono_32float.wav -text svneol=unset#audio/x-wav
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+packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_16.wav -text svneol=unset#audio/x-wav
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+packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_16.wav.raw -text
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+packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_64float.wav.raw -text
+packages/fcl-sound/tests/data/wav/reader/valid/44k_stereo_8.wav -text svneol=unset#audio/x-wav
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+packages/fcl-sound/tests/data/wav/reader/valid/euphoric_tape.wav -text svneol=unset#audio/x-wav
+packages/fcl-sound/tests/data/wav/reader/valid/euphoric_tape.wav.info.txt svneol=native#text/plain
+packages/fcl-sound/tests/data/wav/reader/valid/euphoric_tape.wav.raw -text svneol=unset#application/octet-stream
+packages/fcl-sound/tests/data/wav/reader/valid/odd_fmt_size.wav -text svneol=unset#audio/x-wav
+packages/fcl-sound/tests/data/wav/reader/valid/odd_fmt_size.wav.info.txt svneol=native#text/plain
+packages/fcl-sound/tests/data/wav/reader/valid/odd_fmt_size.wav.raw -text svneol=unset#application/octet-stream
+packages/fcl-sound/tests/tcwavreader.pas svneol=native#text/plain
+packages/fcl-sound/tests/testfclsound.lpi svneol=native#text/plain
+packages/fcl-sound/tests/testfclsound.lpr svneol=native#text/plain
 packages/fcl-stl/Makefile svneol=native#text/plain
 packages/fcl-stl/Makefile.fpc svneol=native#text/plain
 packages/fcl-stl/Makefile.fpc.fpcmake svneol=native#text/plain
@@ -6223,6 +6276,7 @@ packages/ide/fp.pas svneol=native#text/plain
 packages/ide/fp.term -text svneol=unset#application/octet-stream
 packages/ide/fp32.ico -text
 packages/ide/fp32.rc -text
+packages/ide/fparm.lpi svneol=native#text/plain
 packages/ide/fpcalc.pas svneol=native#text/plain
 packages/ide/fpcatch.pas svneol=native#text/plain
 packages/ide/fpcodcmp.pas svneol=native#text/plain
@@ -8684,6 +8738,13 @@ packages/pxlib/examples/Makefile.fpc svneol=native#text/plain
 packages/pxlib/examples/ppxview.pp svneol=native#text/plain
 packages/pxlib/fpmake.pp svneol=native#text/plain
 packages/pxlib/src/pxlib.pp svneol=native#text/plain
+packages/qlunits/Makefile svneol=native#text/plain
+packages/qlunits/Makefile.fpc svneol=native#text/plain
+packages/qlunits/README.txt svneol=native#text/plain
+packages/qlunits/examples/qlcube.pas svneol=native#text/plain
+packages/qlunits/fpmake.pp svneol=native#text/plain
+packages/qlunits/src/qdos.pas svneol=native#text/plain
+packages/qlunits/src/qlfloat.pas svneol=native#text/plain
 packages/regexpr/Makefile svneol=native#text/plain
 packages/regexpr/Makefile.fpc svneol=native#text/plain
 packages/regexpr/Makefile.fpc.fpcmake svneol=native#text/plain
@@ -11142,7 +11203,6 @@ rtl/linux/linux.pp svneol=native#text/plain
 rtl/linux/linuxvcs.pp svneol=native#text/plain
 rtl/linux/m68k/bsyscall.inc svneol=native#text/plain
 rtl/linux/m68k/cprt0.as svneol=native#text/plain
-rtl/linux/m68k/cprt21.as svneol=native#text/plain
 rtl/linux/m68k/dllprt0.as svneol=native#text/plain
 rtl/linux/m68k/gprt0.as svneol=native#text/plain
 rtl/linux/m68k/gprt21.as svneol=native#text/plain
@@ -11690,6 +11750,7 @@ rtl/objpas/sysutils/sysutilh.inc svneol=native#text/plain
 rtl/objpas/sysutils/sysutils.inc svneol=native#text/plain
 rtl/objpas/sysutils/syswide.inc svneol=native#text/plain
 rtl/objpas/sysutils/syswideh.inc svneol=native#text/plain
+rtl/objpas/sysutils/tzenv.inc svneol=native#text/plain
 rtl/objpas/types.pp svneol=native#text/plain
 rtl/objpas/typinfo.pp svneol=native#text/plain
 rtl/objpas/unicodedata.inc svneol=native#text/pascal
@@ -11897,6 +11958,22 @@ rtl/riscv64/setjump.inc svneol=native#text/plain
 rtl/riscv64/setjumph.inc svneol=native#text/plain
 rtl/riscv64/strings.inc svneol=native#text/plain
 rtl/riscv64/stringss.inc svneol=native#text/plain
+rtl/sinclairql/Makefile svneol=native#text/plain
+rtl/sinclairql/Makefile.fpc svneol=native#text/plain
+rtl/sinclairql/buildrtl.pp svneol=native#text/plain
+rtl/sinclairql/qdos.inc svneol=native#text/plain
+rtl/sinclairql/qdosfuncs.inc svneol=native#text/plain
+rtl/sinclairql/qdosh.inc svneol=native#text/plain
+rtl/sinclairql/rtl.cfg svneol=native#text/plain
+rtl/sinclairql/rtldefs.inc svneol=native#text/plain
+rtl/sinclairql/si_prc.pp svneol=native#text/plain
+rtl/sinclairql/sysdir.inc svneol=native#text/plain
+rtl/sinclairql/sysfile.inc svneol=native#text/plain
+rtl/sinclairql/sysheap.inc svneol=native#text/plain
+rtl/sinclairql/sysos.inc svneol=native#text/plain
+rtl/sinclairql/sysosh.inc svneol=native#text/plain
+rtl/sinclairql/system.pp svneol=native#text/plain
+rtl/sinclairql/tthread.inc svneol=native#text/plain
 rtl/solaris/Makefile svneol=native#text/plain
 rtl/solaris/Makefile.fpc svneol=native#text/plain
 rtl/solaris/errno.inc svneol=native#text/plain
@@ -12657,6 +12734,8 @@ tests/tbf/tb0268.pp svneol=native#text/pascal
 tests/tbf/tb0269.pp svneol=native#text/pascal
 tests/tbf/tb0270.pp svneol=native#text/pascal
 tests/tbf/tb0271.pp svneol=native#text/pascal
+tests/tbf/tb0272.pp svneol=native#text/plain
+tests/tbf/tb0273.pp svneol=native#text/pascal
 tests/tbf/tb0588.pp svneol=native#text/pascal
 tests/tbf/ub0115.pp svneol=native#text/plain
 tests/tbf/ub0149.pp svneol=native#text/plain
@@ -13353,6 +13432,11 @@ tests/tbs/tb0676.pp svneol=native#text/pascal
 tests/tbs/tb0676a.pp svneol=native#text/plain
 tests/tbs/tb0677.pp svneol=native#text/pascal
 tests/tbs/tb0678.pp svneol=native#text/pascal
+tests/tbs/tb0679.pp svneol=native#text/pascal
+tests/tbs/tb0680.pp svneol=native#text/pascal
+tests/tbs/tb0681.pp svneol=native#text/pascal
+tests/tbs/tb0682.pp svneol=native#text/pascal
+tests/tbs/tb0683.pp svneol=native#text/plain
 tests/tbs/ub0060.pp svneol=native#text/plain
 tests/tbs/ub0069.pp svneol=native#text/plain
 tests/tbs/ub0119.pp svneol=native#text/plain
@@ -13864,6 +13948,7 @@ tests/test/cg/tderef.pp svneol=native#text/plain
 tests/test/cg/tdivz1.pp svneol=native#text/plain
 tests/test/cg/tdivz2.pp svneol=native#text/plain
 tests/test/cg/texit.pp svneol=native#text/plain
+tests/test/cg/texit2.pp svneol=native#text/plain
 tests/test/cg/tfor.pp svneol=native#text/plain
 tests/test/cg/tfor2.pp svneol=native#text/pascal
 tests/test/cg/tformfnc.pp svneol=native#text/plain
@@ -14357,6 +14442,7 @@ tests/test/packages/webtbs/tw14265.pp svneol=native#text/plain
 tests/test/packages/webtbs/tw1808.pp svneol=native#text/plain
 tests/test/packages/webtbs/tw3820.pp svneol=native#text/plain
 tests/test/packages/win-base/tdispvar1.pp svneol=native#text/plain
+tests/test/packages/win-base/tdispvar2.pp svneol=native#text/pascal
 tests/test/packages/zlib/tzlib1.pp svneol=native#text/plain
 tests/test/t4cc1.pp svneol=native#text/plain
 tests/test/t4cc2.pp svneol=native#text/plain
@@ -14865,6 +14951,7 @@ tests/test/tfma1.inc svneol=native#text/plain
 tests/test/tfma1a64.pp svneol=native#text/pascal
 tests/test/tfma1arm.pp svneol=native#text/pascal
 tests/test/tfma1x86.pp svneol=native#text/pascal
+tests/test/tfma1xtensa.pp svneol=native#text/pascal
 tests/test/tforin1.pp svneol=native#text/pascal
 tests/test/tforin10.pp svneol=native#text/plain
 tests/test/tforin11.pp svneol=native#text/plain
@@ -14979,6 +15066,8 @@ tests/test/tgeneric102.pp svneol=native#text/pascal
 tests/test/tgeneric103.pp svneol=native#text/pascal
 tests/test/tgeneric104.pp -text svneol=native#text/pascal
 tests/test/tgeneric105.pp svneol=native#text/pascal
+tests/test/tgeneric106.pp svneol=native#text/pascal
+tests/test/tgeneric107.pp svneol=native#text/pascal
 tests/test/tgeneric11.pp svneol=native#text/plain
 tests/test/tgeneric12.pp svneol=native#text/plain
 tests/test/tgeneric13.pp svneol=native#text/plain
@@ -15091,6 +15180,11 @@ tests/test/tgenfunc2.pp svneol=native#text/pascal
 tests/test/tgenfunc20.pp svneol=native#text/pascal
 tests/test/tgenfunc21.pp svneol=native#text/pascal
 tests/test/tgenfunc22.pp svneol=native#text/pascal
+tests/test/tgenfunc23.pp svneol=native#text/pascal
+tests/test/tgenfunc24.pp svneol=native#text/pascal
+tests/test/tgenfunc25.pp svneol=native#text/pascal
+tests/test/tgenfunc26.pp svneol=native#text/pascal
+tests/test/tgenfunc27.pp svneol=native#text/pascal
 tests/test/tgenfunc3.pp svneol=native#text/pascal
 tests/test/tgenfunc4.pp svneol=native#text/pascal
 tests/test/tgenfunc5.pp svneol=native#text/pascal
@@ -15273,6 +15367,7 @@ tests/test/tmacprocvar.pp svneol=native#text/plain
 tests/test/tmainnam.pp svneol=native#text/plain
 tests/test/tmath1.pp svneol=native#text/plain
 tests/test/tmcbool2.pp svneol=native#text/plain
+tests/test/tminmax.pp svneol=native#text/pascal
 tests/test/tmmx1.pp svneol=native#text/plain
 tests/test/tmoperator1.pp svneol=native#text/pascal
 tests/test/tmoperator10.pp svneol=native#text/pascal
@@ -15312,6 +15407,7 @@ tests/test/tnest1.pp svneol=native#text/plain
 tests/test/tnest2.pp svneol=native#text/plain
 tests/test/tnest3.pp svneol=native#text/plain
 tests/test/tnest4.pp svneol=native#text/plain
+tests/test/tnest5.pp svneol=native#text/plain
 tests/test/tnoext1.pp svneol=native#text/plain
 tests/test/tnoext2.pp svneol=native#text/plain
 tests/test/tnoext3.pp svneol=native#text/plain
@@ -15499,6 +15595,11 @@ tests/test/toperator88.pp svneol=native#text/pascal
 tests/test/toperator89.pp svneol=native#text/pascal
 tests/test/toperator9.pp svneol=native#text/pascal
 tests/test/toperator90.pp svneol=native#text/pascal
+tests/test/toperator91.pp svneol=native#text/pascal
+tests/test/toperator92.pp svneol=native#text/pascal
+tests/test/toperator93.pp svneol=native#text/pascal
+tests/test/toperator94.pp svneol=native#text/pascal
+tests/test/toperator95.pp svneol=native#text/pascal
 tests/test/toperatorerror.pp svneol=native#text/plain
 tests/test/tover1.pp svneol=native#text/plain
 tests/test/tover2.pp svneol=native#text/plain
@@ -15579,6 +15680,7 @@ tests/test/tpropdef.pp svneol=native#text/plain
 tests/test/tpushpop1.pp svneol=native#text/pascal
 tests/test/tpushpop2.pp svneol=native#text/pascal
 tests/test/tpushpop3.pp svneol=native#text/pascal
+tests/test/traa641.pp svneol=native#text/plain
 tests/test/trange1.pp svneol=native#text/plain
 tests/test/trange2.pp svneol=native#text/plain
 tests/test/trange3.pp svneol=native#text/plain
@@ -15750,6 +15852,7 @@ tests/test/tthlp26b.pp -text svneol=native#text/pascal
 tests/test/tthlp26c.pp -text svneol=native#text/pascal
 tests/test/tthlp27.pp svneol=native#text/pascal
 tests/test/tthlp28.pp svneol=native#text/pascal
+tests/test/tthlp29.pp svneol=native#text/pascal
 tests/test/tthlp3.pp svneol=native#text/pascal
 tests/test/tthlp4.pp svneol=native#text/pascal
 tests/test/tthlp5.pp svneol=native#text/pascal
@@ -16013,6 +16116,7 @@ tests/test/units/math/tmask2.pp svneol=native#text/plain
 tests/test/units/math/tminmaxconst.pp svneol=native#text/pascal
 tests/test/units/math/tnaninf.pp svneol=native#text/plain
 tests/test/units/math/tpower.pp svneol=native#text/pascal
+tests/test/units/math/trndcurr.pp svneol=native#text/plain
 tests/test/units/math/troundm.pp svneol=native#text/plain
 tests/test/units/math/tsincos.pp svneol=native#text/pascal
 tests/test/units/math/ttrig1.pp svneol=native#text/plain
@@ -16129,6 +16233,7 @@ tests/test/units/sysutils/tbytesof.pp svneol=native#text/pascal
 tests/test/units/sysutils/tdirex.pp svneol=native#text/plain
 tests/test/units/sysutils/tencodingerrors.pp svneol=native#text/pascal
 tests/test/units/sysutils/tencodingtest.pp svneol=native#text/pascal
+tests/test/units/sysutils/testspo.pp svneol=native#text/plain
 tests/test/units/sysutils/texec1.pp svneol=native#text/plain
 tests/test/units/sysutils/texec2.pp svneol=native#text/plain
 tests/test/units/sysutils/texpfncase.pp svneol=native#text/plain
@@ -16153,7 +16258,8 @@ tests/test/units/sysutils/twstralloc.pp svneol=native#text/plain
 tests/test/units/sysutils/twstrcmp.pp svneol=native#text/plain
 tests/test/units/types/ttbitconverter.pp svneol=native#text/pascal
 tests/test/units/ucomplex/tcsqr1.pp svneol=native#text/pascal
-tests/test/units/unixutil/tepoch1.pp svneol=native#text/pascal
+tests/test/units/unix/tepoch1.pp svneol=native#text/pascal
+tests/test/units/unix/ttimezone1.pp svneol=native#text/pascal
 tests/test/units/variants/tcustomvariant.pp svneol=native#text/plain
 tests/test/units/variants/tvararrayofintf.pp svneol=native#text/plain
 tests/test/units/variants/tw26370.pp svneol=native#text/plain
@@ -16595,6 +16701,8 @@ tests/webtbf/tw37476.pp svneol=native#text/pascal
 tests/webtbf/tw37763.pp svneol=native#text/pascal
 tests/webtbf/tw3790.pp svneol=native#text/plain
 tests/webtbf/tw3812.pp svneol=native#text/plain
+tests/webtbf/tw38289a.pp svneol=native#text/pascal
+tests/webtbf/tw38289b.pp svneol=native#text/pascal
 tests/webtbf/tw3930a.pp svneol=native#text/plain
 tests/webtbf/tw3931b.pp svneol=native#text/plain
 tests/webtbf/tw3969.pp svneol=native#text/plain
@@ -17967,6 +18075,7 @@ tests/webtbs/tw2886.pp svneol=native#text/plain
 tests/webtbs/tw2891.pp svneol=native#text/plain
 tests/webtbs/tw28916.pp svneol=native#text/pascal
 tests/webtbs/tw2892.pp svneol=native#text/plain
+tests/webtbs/tw28927.pp svneol=native#text/pascal
 tests/webtbs/tw28934.pp svneol=native#text/plain
 tests/webtbs/tw28948.pp svneol=native#text/plain
 tests/webtbs/tw28964.pp svneol=native#text/plain
@@ -18366,6 +18475,7 @@ tests/webtbs/tw3578.pp svneol=native#text/plain
 tests/webtbs/tw3579.pp svneol=native#text/plain
 tests/webtbs/tw35820.pp svneol=native#text/pascal
 tests/webtbs/tw3583.pp svneol=native#text/plain
+tests/webtbs/tw35841.pp svneol=native#text/pascal
 tests/webtbs/tw35862.pp svneol=native#text/pascal
 tests/webtbs/tw35878.pp svneol=native#text/plain
 tests/webtbs/tw35878a.pp svneol=native#text/plain
@@ -18393,6 +18503,7 @@ tests/webtbs/tw36212.pp svneol=native#text/pascal
 tests/webtbs/tw36215.pp svneol=native#text/pascal
 tests/webtbs/tw3628.pp svneol=native#text/plain
 tests/webtbs/tw3634.pp svneol=native#text/plain
+tests/webtbs/tw36381.pp svneol=native#text/plain
 tests/webtbs/tw36388.pp svneol=native#text/pascal
 tests/webtbs/tw36389.pp svneol=native#text/pascal
 tests/webtbs/tw36496a.pp svneol=native#text/pascal
@@ -18452,6 +18563,7 @@ tests/webtbs/tw37322.pp svneol=native#text/pascal
 tests/webtbs/tw37323.pp svneol=native#text/pascal
 tests/webtbs/tw37339.pp svneol=native#text/pascal
 tests/webtbs/tw37355.pp svneol=native#text/pascal
+tests/webtbs/tw37382.pp svneol=native#text/pascal
 tests/webtbs/tw37393.pp svneol=native#text/pascal
 tests/webtbs/tw37397.pp svneol=native#text/plain
 tests/webtbs/tw37398.pp svneol=native#text/pascal
@@ -18471,6 +18583,7 @@ tests/webtbs/tw37508.pp svneol=native#text/pascal
 tests/webtbs/tw3751.pp svneol=native#text/plain
 tests/webtbs/tw37554.pp svneol=native#text/pascal
 tests/webtbs/tw3758.pp svneol=native#text/plain
+tests/webtbs/tw37621.pp -text svneol=native#text/pascal
 tests/webtbs/tw3764.pp svneol=native#text/plain
 tests/webtbs/tw3765.pp svneol=native#text/plain
 tests/webtbs/tw37650.pp svneol=native#text/pascal
@@ -18485,11 +18598,44 @@ tests/webtbs/tw3780.pp svneol=native#text/plain
 tests/webtbs/tw37806.pp svneol=native#text/pascal
 tests/webtbs/tw3782.pp svneol=native#text/plain
 tests/webtbs/tw37823.pp svneol=native#text/pascal
+tests/webtbs/tw37844.pp svneol=native#text/pascal
+tests/webtbs/tw37878.pp svneol=native#text/plain
+tests/webtbs/tw37926.pp svneol=native#text/pascal
+tests/webtbs/tw37949.pp svneol=native#text/pascal
 tests/webtbs/tw3796.pp svneol=native#text/plain
+tests/webtbs/tw37969.pp svneol=native#text/pascal
+tests/webtbs/tw38012.pp svneol=native#text/pascal
+tests/webtbs/tw38022.pp svneol=native#text/pascal
 tests/webtbs/tw3805.pp svneol=native#text/plain
+tests/webtbs/tw38051.pp svneol=native#text/pascal
+tests/webtbs/tw38054.pp svneol=native#text/plain
+tests/webtbs/tw38058.pp svneol=native#text/pascal
+tests/webtbs/tw38069.pp svneol=native#text/pascal
+tests/webtbs/tw38074.pp svneol=native#text/pascal
+tests/webtbs/tw38083.pp svneol=native#text/pascal
+tests/webtbs/tw38122.pp svneol=native#text/pascal
+tests/webtbs/tw38122b.pp svneol=native#text/pascal
 tests/webtbs/tw3814.pp svneol=native#text/plain
+tests/webtbs/tw38145a.pp svneol=native#text/pascal
+tests/webtbs/tw38145b.pp svneol=native#text/pascal
+tests/webtbs/tw38151.pp svneol=native#text/pascal
+tests/webtbs/tw38164.pp svneol=native#text/pascal
+tests/webtbs/tw38201.pp svneol=native#text/pascal
+tests/webtbs/tw38202.pp svneol=native#text/pascal
+tests/webtbs/tw38225.pp svneol=native#text/pascal
+tests/webtbs/tw38238.pp svneol=native#text/pascal
+tests/webtbs/tw38249.pp svneol=native#text/pascal
+tests/webtbs/tw38259.pp svneol=native#text/pascal
+tests/webtbs/tw38267a.pp svneol=native#text/pascal
+tests/webtbs/tw38267b.pp svneol=native#text/pascal
 tests/webtbs/tw3827.pp svneol=native#text/plain
 tests/webtbs/tw3829.pp svneol=native#text/plain
+tests/webtbs/tw38295.pp svneol=native#text/pascal
+tests/webtbs/tw38299.pp svneol=native#text/pascal
+tests/webtbs/tw38309.pp svneol=native#text/pascal
+tests/webtbs/tw38310a.pp svneol=native#text/pascal
+tests/webtbs/tw38310b.pp svneol=native#text/pascal
+tests/webtbs/tw38310c.pp svneol=native#text/pascal
 tests/webtbs/tw3833.pp svneol=native#text/plain
 tests/webtbs/tw3840.pp svneol=native#text/plain
 tests/webtbs/tw3841.pp svneol=native#text/plain
@@ -19026,6 +19172,7 @@ tests/webtbs/uw35918a.pp svneol=native#text/pascal
 tests/webtbs/uw35918b.pp svneol=native#text/pascal
 tests/webtbs/uw35918c.pp svneol=native#text/pascal
 tests/webtbs/uw36544.pp svneol=native#text/pascal
+tests/webtbs/uw38069.pp svneol=native#text/pascal
 tests/webtbs/uw3968.pp svneol=native#text/plain
 tests/webtbs/uw4056.pp svneol=native#text/plain
 tests/webtbs/uw4140.pp svneol=native#text/plain
@@ -19155,14 +19302,17 @@ utils/fpdoc/Makefile.fpc.fpcmake svneol=native#text/plain
 utils/fpdoc/README.txt svneol=native#text/plain
 utils/fpdoc/css.inc svneol=native#text/plain
 utils/fpdoc/dglobals.pp svneol=native#text/plain
+utils/fpdoc/dw_basehtml.pp svneol=native#text/plain
+utils/fpdoc/dw_basemd.pp svneol=native#text/plain
+utils/fpdoc/dw_chm.pp svneol=native#text/plain
 utils/fpdoc/dw_dxml.pp svneol=native#text/plain
 utils/fpdoc/dw_html.pp svneol=native#text/plain
-utils/fpdoc/dw_htmlchm.inc svneol=native#text/plain
 utils/fpdoc/dw_ipflin.pas svneol=native#text/plain
 utils/fpdoc/dw_latex.pp svneol=native#text/plain
 utils/fpdoc/dw_linrtf.pp svneol=native#text/plain
 utils/fpdoc/dw_lintmpl.pp svneol=native#text/plain
 utils/fpdoc/dw_man.pp svneol=native#text/plain
+utils/fpdoc/dw_markdown.pp svneol=native#text/plain
 utils/fpdoc/dw_template.pp svneol=native#text/plain
 utils/fpdoc/dw_txt.pp svneol=native#text/plain
 utils/fpdoc/dw_xml.pp svneol=native#text/plain

.gitignore

@@ -3,6 +3,7 @@
 /*.o
 /*.ppu
 /*.s
+/bin
 /build-stamp.*
 compiler/*.bak
 compiler/*.exe

Makefile

@@ -2,7 +2,7 @@
 # Don't edit, this file is generated by FPCMake Version 2.0.0
 #
 default: help
-MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm-wasm sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos
+MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded m68k-sinclairql powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm-wasm sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos z80-amstradcpc
 BSDs = freebsd netbsd openbsd darwin dragonfly
 UNIXs = linux $(BSDs) solaris qnx haiku aix
 LIMIT83fs = go32v2 os2 emx watcom msdos win16 atari
@@ -601,6 +601,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 override TARGET_DIRS+=compiler rtl utils packages installer
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+override TARGET_DIRS+=compiler rtl utils packages installer
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 override TARGET_DIRS+=compiler rtl utils packages installer
 endif
@@ -817,6 +820,9 @@ endif
 ifeq ($(FULL_TARGET),z80-msxdos)
 override TARGET_DIRS+=compiler rtl utils packages installer
 endif
+ifeq ($(FULL_TARGET),z80-amstradcpc)
+override TARGET_DIRS+=compiler rtl utils packages installer
+endif
 override INSTALL_FPCPACKAGE=y
 ifdef REQUIRE_UNITSDIR
 override UNITSDIR+=$(REQUIRE_UNITSDIR)
@@ -1044,15 +1050,34 @@ ifneq ($(findstring sparc64,$(shell uname -a)),)
 ifeq ($(BINUTILSPREFIX),)
 GCCLIBDIR:=$(shell dirname `gcc -m32 -print-libgcc-file-name`)
 else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips mipsel),)
+CROSSGCCOPT=-mabi=32
+else
 CROSSGCCOPT=-m32
 endif
 endif
 endif
 endif
+endif
 ifdef FPCFPMAKE
 FPCFPMAKE_CPU_TARGET=$(shell $(FPCFPMAKE) -iTP)
 ifeq ($(CPU_TARGET),$(FPCFPMAKE_CPU_TARGET))
 FPCMAKEGCCLIBDIR:=$(GCCLIBDIR)
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_TARGET),aarch64 powerpc64 riscv64 sparc64 x86_64),)
+FPCMAKE_CROSSGCCOPT=-m64
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips64 mips64el),)
+FPCMAKE_CROSSGCCOPT=-mabi=64
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips mipsel),)
+FPCMAKE_CROSSGCCOPT=-mabi=32
+else
+FPCMAKE_CROSSGCCOPT=-m32
+endif
+endif
+endif
+FPCMAKEGCCLIBDIR:=$(shell dirname `gcc $(FPCMAKE_CROSSGCCOPT) -print-libgcc-file-name`)
 endif
 endif
 ifndef FPCMAKEGCCLIBDIR
@@ -1569,11 +1594,11 @@ endif
 ifndef CROSSBOOTSTRAP
 ifneq ($(BINUTILSPREFIX),)
 override FPCOPT+=-XP$(BINUTILSPREFIX)
-endif
-ifneq ($(BINUTILSPREFIX),)
+ifneq ($(RLINKPATH),)
 override FPCOPT+=-Xr$(RLINKPATH)
 endif
 endif
+endif
 ifndef CROSSCOMPILE
 ifneq ($(BINUTILSPREFIX),)
 override FPCMAKEOPT+=-XP$(BINUTILSPREFIX)
@@ -2285,6 +2310,13 @@ TARGET_DIRS_UTILS=1
 TARGET_DIRS_PACKAGES=1
 TARGET_DIRS_INSTALLER=1
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+TARGET_DIRS_COMPILER=1
+TARGET_DIRS_RTL=1
+TARGET_DIRS_UTILS=1
+TARGET_DIRS_PACKAGES=1
+TARGET_DIRS_INSTALLER=1
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 TARGET_DIRS_COMPILER=1
 TARGET_DIRS_RTL=1
@@ -2789,6 +2821,13 @@ TARGET_DIRS_UTILS=1
 TARGET_DIRS_PACKAGES=1
 TARGET_DIRS_INSTALLER=1
 endif
+ifeq ($(FULL_TARGET),z80-amstradcpc)
+TARGET_DIRS_COMPILER=1
+TARGET_DIRS_RTL=1
+TARGET_DIRS_UTILS=1
+TARGET_DIRS_PACKAGES=1
+TARGET_DIRS_INSTALLER=1
+endif
 ifdef TARGET_DIRS_COMPILER
 compiler_all:
 	$(MAKE) -C compiler all

compiler/Makefile

@@ -2,7 +2,7 @@
 # Don't edit, this file is generated by FPCMake Version 2.0.0
 #
 default: all
-MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm-wasm sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos z80-amstradcpc
+MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded m68k-sinclairql powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm-wasm sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos z80-amstradcpc
 BSDs = freebsd netbsd openbsd darwin dragonfly
 UNIXs = linux $(BSDs) solaris qnx haiku aix
 LIMIT83fs = go32v2 os2 emx watcom msdos win16 atari
@@ -352,6 +352,24 @@ override PACKAGE_VERSION=3.3.1
 unexport FPC_VERSION FPC_COMPILERINFO
 CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80
 ALLTARGETS=$(CYCLETARGETS)
+NO_NATIVE_COMPILER_OS_LIST=amstradcpc embedded freertos gba macosclassic msdos msxdos nds palmos symbian watcom wii win16 zxspectrum
+NO_NATIVE_COMPILER_CPU_LIST=avr i8086 jvm z80
+ifneq ($(CPU_SOURCE),$(CPU_TARGET))
+ifneq ($(findstring $(CPU_TARGET),$(NO_NATIVE_COMPILER_CPU_LIST)),)
+NoNativeBinaries=1
+endif
+endif
+ifneq ($(OS_SOURCE),$(OS_TARGET))
+ifneq ($(findstring $(OS_TARGET),$(NO_NATIVE_COMPILER_OS_LIST)),)
+NoNativeBinaries=1
+endif
+endif
+ifndef FORCE_NATIVE_BINARIES
+ifeq ($(NoNativeBinaries),1)
+override EXEEXT=$(SRCEXEEXT)
+CROSSINSTALL=1
+endif
+endif
 ifdef POWERPC
 PPC_TARGET=powerpc
 endif
@@ -433,6 +451,18 @@ endif
 ifndef RTLOPT
 RTLOPT:=$(OPT)
 endif
+DATE_FMT = +%Y/%m/%d
+ifdef SOURCE_DATE_EPOCH
+    COMPDATESTR ?= $(shell date -u -d "@$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u -r "$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u "$(DATE_FMT)")
+else
+   GIT_DIR = $(wildcard ../.git)
+   ifneq ($(GIT_DIR),)
+      COMPDATESTR:=$(shell git log -1 --pretty=%cd --date=format:'%Y/%m/%d')
+   endif
+endif
+ifdef COMPDATESTR
+override OPTNEW+=-DD$(COMPDATESTR)
+endif
 ifdef CYCLELEVEL
 ifeq ($(CYCLELEVEL),1)
 override LOCALOPT+=$(OPTLEVEL1)
@@ -613,37 +643,6 @@ OPTWPOPERFORM+=-Owsymbolliveness
 endif
 endif
 endif
-ifeq ($(CPU_TARGET),jvm)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),embedded)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),gba)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),msdos)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),nds)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),win16)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),macosclassic)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),freertos)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),zxspectrum)
-NoNativeBinaries=1
-endif
-ifeq ($(NoNativeBinaries),1)
-override EXEEXT=$(SRCEXEEXT)
-CROSSINSTALL=1
-endif
 ifeq ($(FULL_TARGET),i386-linux)
 override TARGET_DIRS+=utils
 endif
@@ -734,6 +733,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 override TARGET_DIRS+=utils
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+override TARGET_DIRS+=utils
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 override TARGET_DIRS+=utils
 endif
@@ -1043,6 +1045,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 override TARGET_PROGRAMS+=pp
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+override TARGET_PROGRAMS+=pp
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 override TARGET_PROGRAMS+=pp
 endif
@@ -1353,6 +1358,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
 endif
@@ -1662,6 +1670,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
 endif
@@ -1971,6 +1982,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
 endif
@@ -2280,6 +2294,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
 endif
@@ -2725,15 +2742,34 @@ ifneq ($(findstring sparc64,$(shell uname -a)),)
 ifeq ($(BINUTILSPREFIX),)
 GCCLIBDIR:=$(shell dirname `gcc -m32 -print-libgcc-file-name`)
 else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips mipsel),)
+CROSSGCCOPT=-mabi=32
+else
 CROSSGCCOPT=-m32
 endif
 endif
 endif
 endif
+endif
 ifdef FPCFPMAKE
 FPCFPMAKE_CPU_TARGET=$(shell $(FPCFPMAKE) -iTP)
 ifeq ($(CPU_TARGET),$(FPCFPMAKE_CPU_TARGET))
 FPCMAKEGCCLIBDIR:=$(GCCLIBDIR)
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_TARGET),aarch64 powerpc64 riscv64 sparc64 x86_64),)
+FPCMAKE_CROSSGCCOPT=-m64
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips64 mips64el),)
+FPCMAKE_CROSSGCCOPT=-mabi=64
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips mipsel),)
+FPCMAKE_CROSSGCCOPT=-mabi=32
+else
+FPCMAKE_CROSSGCCOPT=-m32
+endif
+endif
+endif
+FPCMAKEGCCLIBDIR:=$(shell dirname `gcc $(FPCMAKE_CROSSGCCOPT) -print-libgcc-file-name`)
 endif
 endif
 ifndef FPCMAKEGCCLIBDIR
@@ -3324,6 +3360,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 REQUIRE_PACKAGES_RTL=1
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+REQUIRE_PACKAGES_RTL=1
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 REQUIRE_PACKAGES_RTL=1
 endif
@@ -3598,11 +3637,11 @@ endif
 ifndef CROSSBOOTSTRAP
 ifneq ($(BINUTILSPREFIX),)
 override FPCOPT+=-XP$(BINUTILSPREFIX)
-endif
-ifneq ($(BINUTILSPREFIX),)
+ifneq ($(RLINKPATH),)
 override FPCOPT+=-Xr$(RLINKPATH)
 endif
 endif
+endif
 ifndef CROSSCOMPILE
 ifneq ($(BINUTILSPREFIX),)
 override FPCMAKEOPT+=-XP$(BINUTILSPREFIX)
@@ -4288,6 +4327,9 @@ endif
 ifeq ($(FULL_TARGET),m68k-embedded)
 TARGET_DIRS_UTILS=1
 endif
+ifeq ($(FULL_TARGET),m68k-sinclairql)
+TARGET_DIRS_UTILS=1
+endif
 ifeq ($(FULL_TARGET),powerpc-linux)
 TARGET_DIRS_UTILS=1
 endif
@@ -4778,9 +4820,9 @@ msgtxt.inc: $(MSGFILE)
 msg: msgtxt.inc
 insdatx86 : $(COMPILER_UNITTARGETDIR) x86/x86ins.dat
 	$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkx86ins.pp
-	cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) i8086 && mv -f *.inc ../i8086
-	cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) && mv -f *.inc ../i386
-	cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) x86_64 && mv -f *.inc ../x86_64
+	cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) i8086 && mv -f i8086tab.inc i8086op.inc i8086nop.inc i8086att.inc i8086atts.inc i8086int.inc i8086prop.inc ../i8086
+	cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) && mv -f i386tab.inc i386op.inc i386nop.inc i386att.inc i386atts.inc i386int.inc i386prop.inc ../i386
+	cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) x86_64 && mv -f x8664tab.inc x8664op.inc x8664nop.inc x8664att.inc x8664ats.inc x8664int.inc x8664pro.inc ../x86_64
 insdatarm : arm/armins.dat
 	    $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkarmins.pp
 	cd arm && ..$(PATHSEP)utils$(PATHSEP)mkarmins$(SRCEXEEXT)
@@ -4883,7 +4925,7 @@ wpocycle:
 	$(RM) $(EXENAME)
 	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(RTLOPT) $(OPTWPOPERFORM) $(OPTNEW))' rtlclean
 	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(RTLOPT) $(OPTWPOPERFORM) $(OPTNEW))' rtl
-	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(LOCALOPT) $(OPTNEW) $(OPTWPOPERFORM) $(subst pp1.wpo,pp2.wpo,$(OPTWPOCOLLECT)))' $(addsuffix _clean,$(ALLTARGETS)) 
+	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(LOCALOPT) $(OPTNEW) $(OPTWPOPERFORM) $(subst pp1.wpo,pp2.wpo,$(OPTWPOCOLLECT)))' $(addsuffix _clean,$(ALLTARGETS))
 	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(LOCALOPT) $(OPTNEW) $(OPTWPOPERFORM) $(subst pp1.wpo,pp2.wpo,$(OPTWPOCOLLECT)))' compiler
 	$(MOVE) $(EXENAME) $(TEMPWPONAME1)
 	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPWPONAME1PREFIX)$(TEMPWPONAME1)' 'OPT=$(strip $(RTLOPT) $(OPTNEW) $(subst pp1.wpo,pp2.wpo,$(OPTWPOPERFORM)))' rtlclean
@@ -4972,12 +5014,12 @@ ifdef NEED_G_COMPILERS
 endif
 	$(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 rtlclean
 	$(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 rtl
-	$(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 cycleclean 
-	$(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 compiler 
-	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtlclean 
-	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtl 
-	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 cycleclean 
-	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 compiler 
+	$(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 cycleclean
+	$(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 compiler
+	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtlclean
+	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtl
+	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 cycleclean
+	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 compiler
 ifndef CROSSINSTALL
 	$(MAKE) 'FPC=$(BASEDIR)/$(PPCROSSNAMEPREFIX)$(PPCROSSNAME)' 'OPT=$(RTLOPT) $(CROSSOPT)' CYCLELEVEL=3 rtlclean
 	$(MAKE) 'FPC=$(BASEDIR)/$(PPCROSSNAMEPREFIX)$(PPCROSSNAME)' 'OPT=$(RTLOPT) $(CROSSOPT)' CYCLELEVEL=3 rtl
@@ -5053,7 +5095,7 @@ endif
 	$(MKDIR) $(MSGINSTALLDIR)
 	$(INSTALL) $(MSGFILES) $(MSGINSTALLDIR)
 endif
-install: 
+install:
 ifndef FPC
 	$(MAKE) quickinstall auxfilesinstall FPC=$(BASEDIR)/$(INSTALLEXEFILE)
 else

compiler/Makefile.fpc

@@ -37,6 +37,33 @@ CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr
 # All supported targets used for clean
 ALLTARGETS=$(CYCLETARGETS)
 
+# All OS targets that do not support native compiler
+NO_NATIVE_COMPILER_OS_LIST=amstradcpc embedded freertos gba macosclassic msdos msxdos nds palmos symbian watcom wii win16 zxspectrum
+# All CPU targets that do not support native compiler
+NO_NATIVE_COMPILER_CPU_LIST=avr i8086 jvm z80
+
+# Don't compile a native compiler & utilities for targets
+# which do not support it
+ifneq ($(CPU_SOURCE),$(CPU_TARGET))
+ifneq ($(findstring $(CPU_TARGET),$(NO_NATIVE_COMPILER_CPU_LIST)),)
+NoNativeBinaries=1
+endif
+endif
+
+ifneq ($(OS_SOURCE),$(OS_TARGET))
+ifneq ($(findstring $(OS_TARGET),$(NO_NATIVE_COMPILER_OS_LIST)),)
+NoNativeBinaries=1
+endif
+endif
+
+ifndef FORCE_NATIVE_BINARIES
+ifeq ($(NoNativeBinaries),1)
+override EXEEXT=$(SRCEXEEXT)
+# In those cases, installation in a cross-installation
+CROSSINSTALL=1
+endif
+endif
+
 # Allow POWERPC, POWERPC64, M68K, I386, jvm defines for target cpu
 ifdef POWERPC
 PPC_TARGET=powerpc
@@ -141,6 +168,22 @@ ifndef RTLOPT
 RTLOPT:=$(OPT)
 endif
 
+DATE_FMT = +%Y/%m/%d
+ifdef SOURCE_DATE_EPOCH
+    COMPDATESTR ?= $(shell date -u -d "@$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u -r "$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u "$(DATE_FMT)")
+else
+   # does a git directory exist? ...
+   GIT_DIR = $(wildcard ../.git)
+   ifneq ($(GIT_DIR),)
+      # ... then take date from head
+      COMPDATESTR:=$(shell git log -1 --pretty=%cd --date=format:'%Y/%m/%d')
+   endif
+endif
+
+ifdef COMPDATESTR
+override OPTNEW+=-DD$(COMPDATESTR)
+endif
+
 ifdef CYCLELEVEL
 ifeq ($(CYCLELEVEL),1)
 override LOCALOPT+=$(OPTLEVEL1)
@@ -380,43 +423,6 @@ endif
 endif
 endif
 
-# Don't compile a native compiler & utilities for JVM and embedded
-# targets
-ifeq ($(CPU_TARGET),jvm)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),embedded)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),gba)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),msdos)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),nds)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),win16)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),macosclassic)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),freertos)
-NoNativeBinaries=1
-endif
-ifeq ($(OS_TARGET),zxspectrum)
-NoNativeBinaries=1
-endif
-
-# Allow install for jvm
-ifeq ($(NoNativeBinaries),1)
-override EXEEXT=$(SRCEXEEXT)
-# In those cases, installation in a cross-installation
-CROSSINSTALL=1
-endif
-
 [rules]
 #####################################################################
 # Setup Targets
@@ -699,9 +705,9 @@ msg: msgtxt.inc
 
 insdatx86 : $(COMPILER_UNITTARGETDIR) x86/x86ins.dat
 	$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkx86ins.pp
-        cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) i8086 && mv -f *.inc ../i8086
-        cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) && mv -f *.inc ../i386
-        cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) x86_64 && mv -f *.inc ../x86_64
+        cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) i8086 && mv -f i8086tab.inc i8086op.inc i8086nop.inc i8086att.inc i8086atts.inc i8086int.inc i8086prop.inc ../i8086
+        cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) && mv -f i386tab.inc i386op.inc i386nop.inc i386att.inc i386atts.inc i386int.inc i386prop.inc ../i386
+        cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86ins$(SRCEXEEXT) x86_64 && mv -f x8664tab.inc x8664op.inc x8664nop.inc x8664att.inc x8664ats.inc x8664int.inc x8664pro.inc ../x86_64
 
 insdatarm : arm/armins.dat
 	    $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkarmins.pp
@@ -739,7 +745,7 @@ regdatsp64 : sparcgen/spreg.dat
             $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkspreg.pp
         cd sparcgen && ..$(PATHSEP)utils$(PATHSEP)mkspreg$(SRCEXEEXT) sparc64
 		mv -f sparcgen/rsp*.inc sparc64
-		
+
 regdatavr : avr/avrreg.dat
             $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkavrreg.pp
         cd avr && ..$(PATHSEP)utils$(PATHSEP)mkavrreg$(SRCEXEEXT)
@@ -765,7 +771,7 @@ intrdatx86 : x86/x86intr.dat
 		cp -f x86/cpumminnr.inc ../rtl/x86_64
         cp -f x86/cpummprocs.inc ../rtl/i386
 		cp -f x86/cpumminnr.inc ../rtl/i386
-        
+
 intrdat : intrdatx86
 
 # revision.inc rule
@@ -854,7 +860,7 @@ wpocycle:
         $(RM) $(EXENAME)
         $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(RTLOPT) $(OPTWPOPERFORM) $(OPTNEW))' rtlclean
         $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(RTLOPT) $(OPTWPOPERFORM) $(OPTNEW))' rtl
-        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(LOCALOPT) $(OPTNEW) $(OPTWPOPERFORM) $(subst pp1.wpo,pp2.wpo,$(OPTWPOCOLLECT)))' $(addsuffix _clean,$(ALLTARGETS)) 
+        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(LOCALOPT) $(OPTNEW) $(OPTWPOPERFORM) $(subst pp1.wpo,pp2.wpo,$(OPTWPOCOLLECT)))' $(addsuffix _clean,$(ALLTARGETS))
 	$(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAME3PREFIX)$(TEMPNAME3)' 'OPT=$(strip $(LOCALOPT) $(OPTNEW) $(OPTWPOPERFORM) $(subst pp1.wpo,pp2.wpo,$(OPTWPOCOLLECT)))' compiler
         $(MOVE) $(EXENAME) $(TEMPWPONAME1)
         $(MAKE) 'FPC=$(BASEDIR)/$(TEMPWPONAME1PREFIX)$(TEMPWPONAME1)' 'OPT=$(strip $(RTLOPT) $(OPTNEW) $(subst pp1.wpo,pp2.wpo,$(OPTWPOPERFORM)))' rtlclean
@@ -972,13 +978,13 @@ endif
 # Clear detected compiler binary, because it can be existing crosscompiler binary, but we need native compiler here
         $(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 rtlclean
         $(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 rtl
-        $(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 cycleclean 
-        $(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 compiler 
+        $(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 cycleclean
+        $(MAKE) OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) EXENAME=$(TEMPNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=1 compiler
 # ppcross<ARCH> (source native)
-        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtlclean 
-        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtl 
-        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 cycleclean 
-        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 compiler 
+        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtlclean
+        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 rtl
+        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 cycleclean
+        $(MAKE) 'FPC=$(BASEDIR)/$(TEMPNAMEPREFIX)$(TEMPNAME)' OS_TARGET=$(OS_SOURCE) CPU_TARGET=$(CPU_SOURCE) PPC_TARGET=$(CPU_TARGET) EXENAME=$(PPCROSSNAME) CROSSBINDIR= BINUTILSPREFIX= CROSSCYCLEBOOTSTRAP=1 CYCLELEVEL=2 compiler
 # ppc<ARCH> (target native)
 ifndef CROSSINSTALL
         $(MAKE) 'FPC=$(BASEDIR)/$(PPCROSSNAMEPREFIX)$(PPCROSSNAME)' 'OPT=$(RTLOPT) $(CROSSOPT)' CYCLELEVEL=3 rtlclean
@@ -1091,7 +1097,7 @@ fullinstall:
 	$(MAKE) $(addsuffix _exe_install,$($(FULL_TARGETS)))
 	$(MAKE) $(addsuffix _all,$(TARGET_DIRS))
 	$(MAKE) $(addsuffix _install,$(TARGET_DIRS))
-        
+
 auxfilesinstall:
 ifndef CROSSINSTALL
 ifdef UNIXHier
@@ -1101,9 +1107,9 @@ endif
         $(MKDIR) $(MSGINSTALLDIR)
         $(INSTALL) $(MSGFILES) $(MSGINSTALLDIR)
 endif
-	
 
-install: 
+
+install:
 # if no FPC is passed, use that one we assume, we just build
 ifndef FPC
 	$(MAKE) quickinstall auxfilesinstall FPC=$(BASEDIR)/$(INSTALLEXEFILE)

compiler/aarch64/a64att.inc

@@ -47,18 +47,6 @@
 'ldaxr',
 'stlxr',
 'stlxp',
-'ld1',
-'ld2',
-'ld3',
-'ld4',
-'st1',
-'st2',
-'st3',
-'st4',
-'ld1r',
-'ld2r',
-'ld3r',
-'ld4r',
 'prfm',
 'prfum',
 'add',
@@ -111,35 +99,11 @@
 'csneg',
 'ccmn',
 'ccmp',
-'nop',
-'yield',
-'wfe',
-'wfi',
-'sev',
-'sevl',
-'mov',
-'bfi',
-'bfxil',
-'sbfiz',
-'sbfx',
-'ubfiz',
-'ubfx',
-'asr',
-'lsl',
-'lsr',
-'ror',
-'sxtb',
-'sxth',
-'sxtw',
-'uxtb',
-'uxth',
-'neg',
 'ngc',
 'mvn',
 'mneg',
 'mul',
 'smnegl',
-'smull',
 'umnegl',
 'umull',
 'cset',
@@ -147,20 +111,102 @@
 'cinc',
 'cinv',
 'cneg',
-'fmov',
+'sxtb',
+'sxth',
+'sxtw',
+'uxtb',
+'uxth',
+'bfi',
+'bfxil',
+'sbfiz',
+'sbfx',
+'ubfiz',
+'ubfx',
+'yield',
+'wfe',
+'wfi',
+'sev',
+'sevl',
+'mov',
+'addhn',
+'addhn2',
+'addp',
+'addv',
+'aesd',
+'aese',
+'aesimc',
+'easmc',
+'bif',
+'bit',
+'bsl',
+'cmeq',
+'cmge',
+'cmgt',
+'cmhi',
+'cmhs',
+'cmle',
+'cmlt',
+'cmtst',
+'cnt',
+'dup',
+'ext',
+'fabd',
+'bacge',
+'fabs',
+'facgt',
+'fadd',
+'fccmp',
+'fccmpe',
+'fcmeq',
+'fcmge',
+'fcmgt',
+'fcmle',
+'fcmlt',
+'fcmp',
+'fcmpe',
+'fcsel',
 'fcvt',
 'fcvtas',
 'fcvtau',
+'fcvtl',
+'fcvtl2',
 'fcvtms',
 'fcvtmu',
 'fcvtns',
 'fcvtnu',
 'fcvtps',
 'fcvtpu',
+'fcvtxn',
+'fcvtxn2',
 'fcvtzs',
 'fcvtzu',
-'scvtf',
-'ucvtf',
+'fdiv',
+'fmadd',
+'fmax',
+'fmaxnm',
+'fmaxnmp',
+'fmanmv',
+'fmaxp',
+'fmaxv',
+'fmin',
+'fminnm',
+'fminnmp',
+'fminnmv',
+'fminp',
+'fminv',
+'fmla',
+'fmls',
+'fmov',
+'fmsub',
+'fmul',
+'fmulx',
+'fneg',
+'fnmadd',
+'fnmsub',
+'fnmul',
+'frecpe',
+'frecps',
+'frecpx',
 'frinta',
 'frinti',
 'frintm',
@@ -168,28 +214,188 @@
 'frintp',
 'frintx',
 'frintz',
-'fabs',
-'fneg',
+'frsqrte',
+'frsqrts',
 'fsqrt',
-'fadd',
-'fdiv',
-'fmul',
-'fnmul',
 'fsub',
-'fmax',
-'fmin',
-'fminnm',
-'fmadd',
-'fmsub',
-'fnmadd',
-'fnmsub',
-'fcmp',
-'fcmpe',
-'fccmp',
-'fcmmpe',
-'fcsel',
-'umov',
-'ins',
+'ld1',
+'ld1r',
+'ld2',
+'ld2r',
+'ld3',
+'ld3r',
+'ld4',
+'ld4r',
+'mla',
+'mls',
 'movi',
-'veor'
+'mvni',
+'pmul',
+'pmull',
+'pmull2',
+'raddhn',
+'raddhn2',
+'rev64',
+'rshrn',
+'rshrn2',
+'srubhn',
+'rsubhn2',
+'saba',
+'sabal',
+'sabal2',
+'sadalp',
+'saddl',
+'saddl2',
+'saddlp',
+'saddlv',
+'saddw',
+'saddw2',
+'scvtf',
+'shac1c',
+'sha1h',
+'sha1m',
+'sha1p',
+'sha1su0',
+'sha1su1',
+'sha256h2',
+'sha256h',
+'sha256su0',
+'sha256su1',
+'shadd',
+'shl',
+'shll',
+'shll2',
+'shrn',
+'shrn2',
+'shsub',
+'sli',
+'smax',
+'smaxp',
+'smaxc',
+'smin',
+'sminp',
+'sminv',
+'smlal',
+'smlal2',
+'smlsl',
+'smlsl2',
+'smov',
+'smull',
+'smull2',
+'sqabs',
+'sqadd',
+'sqdmlal',
+'sqdmlal2',
+'sqdmlsl',
+'sqdmlsl2',
+'sqdmulh',
+'sqdmull',
+'sqdmull2',
+'sqneg',
+'sqrdmulh',
+'sqrshl',
+'sqrshrn',
+'sqrshrn2',
+'sqrshrun',
+'sqrshrun2',
+'sqshl',
+'sqshlu',
+'sqshrn',
+'sqsrhn2',
+'sqshrun',
+'sqshrun2',
+'sqsub',
+'sqxtn',
+'sqxtn2',
+'sqxtun',
+'sqxtun2',
+'srhqdd',
+'sri',
+'srshl',
+'srshr',
+'srsra',
+'sshl',
+'sshll',
+'sshll2',
+'sshr',
+'ssra',
+'ssubl',
+'ssubl2',
+'ssubw',
+'ssubw2',
+'st1',
+'st2',
+'st3',
+'st4',
+'subqadd',
+'sxtl',
+'tbl',
+'tbx',
+'trn1',
+'trn2',
+'uaba',
+'uabal',
+'uabal2',
+'uabd',
+'uabdl',
+'uabdl2',
+'uadalp',
+'uaddll',
+'uaddll2',
+'uaddlp',
+'uaddlv',
+'uaddw',
+'uaddw2',
+'ucvtf',
+'uhadd',
+'uhsub',
+'umax',
+'umaxp',
+'umaxv',
+'umin',
+'uminp',
+'uminv',
+'umlal',
+'umlal2',
+'umlsl',
+'umlsl2',
+'umov',
+'uqadd',
+'uqrshl',
+'uqrshrn',
+'uqrshrn2',
+'uqshl',
+'uqshrn',
+'uqsub',
+'uqxtn',
+'uqxtn2',
+'urecpe',
+'urhadd',
+'urshl',
+'urshr',
+'ursqrte',
+'ursra',
+'ushl',
+'ushll2',
+'ushr',
+'usqadd',
+'usra',
+'usubl',
+'usubl2',
+'usubw',
+'usubw2',
+'uxtl',
+'uzp1',
+'uzp2',
+'xtn1',
+'xtn2',
+'zip1',
+'zip2',
+'nop',
+'asr',
+'lsl',
+'lsr',
+'ror',
+'neg',
+'ins'
 );

compiler/aarch64/a64atts.inc

@@ -191,5 +191,211 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufNONE
 );

compiler/aarch64/a64ins.dat

@@ -93,30 +93,6 @@
 
 [STLXP]
 
-[LD1]
-
-[LD2]
-
-[LD3]
-
-[LD4]
-
-[ST1]
-
-[ST2]
-
-[ST3]
-
-[ST4]
-
-[LD1R]
-
-[LD2R]
-
-[LD3R]
-
-[LD4R]
-
 [PRFM]
 
 [PRFUM]
@@ -221,21 +197,39 @@
 
 [CCMP]
 
-; Aliases
-; they are not generated by the compiler, they are only used for inline assembler
-[NOP]
+[NGC]
 
-[YIELD]
+[MVN]
 
-[WFE]
+[MNEG]
 
-[WFI]
+[MUL]
 
-[SEV]
+[SMNEGL]
 
-[SEVL]
+[UMNEGL]
 
-[MOV]
+[UMULL]
+
+[CSET]
+
+[CSETM]
+
+[CINC]
+
+[CINV]
+
+[CNEG]
+
+[SXTB]
+
+[SXTH]
+
+[SXTW]
+
+[UXTB]
+
+[UXTH]
 
 [BFI]
 
@@ -249,53 +243,92 @@
 
 [UBFX]
 
-[ASR]
+[YIELD]
 
-[LSL]
+[WFE]
 
-[LSR]
+[WFI]
 
-[ROR]
+[SEV]
 
-[SXTB]
+[SEVL]
 
-[SXTH]
+[MOV]
 
-[SXTW]
+; Vector/float instructions
+[ADDHN]
 
-[UXTB]
+[ADDHN2]
 
-[UXTH]
+[ADDP]
 
-[NEG]
+[ADDV]
 
-[NGC]
+[AESD]
 
-[MVN]
+[AESE]
 
-[MNEG]
+[AESIMC]
 
-[MUL]
+[EASMC]
 
-[SMNEGL]
+[BIF]
 
-[SMULL]
+[BIT]
 
-[UMNEGL]
+[BSL]
 
-[UMULL]
+[CMEQ]
 
-[CSET]
+[CMGE]
 
-[CSETM]
+[CMGT]
 
-[CINC]
+[CMHI]
 
-[CINV]
+[CMHS]
 
-[CNEG]
+[CMLE]
 
-[FMOV]
+[CMLT]
+
+[CMTST]
+
+[CNT]
+
+[DUP]
+
+[EXT]
+
+[FABD]
+
+[BACGE]
+
+[FABS]
+
+[FACGT]
+
+[FADD]
+
+[FCCMP]
+
+[FCCMPE]
+
+[FCMEQ]
+
+[FCMGE]
+
+[FCMGT]
+
+[FCMLE]
+
+[FCMLT]
+
+[FCMP]
+
+[FCMPE]
+
+[FCSEL]
 
 [FCVT]
 
@@ -303,6 +336,10 @@
 
 [FCVTAU]
 
+[FCVTL]
+
+[FCVTL2]
+
 [FCVTMS]
 
 [FCVTMU]
@@ -315,13 +352,67 @@
 
 [FCVTPU]
 
+[FCVTXN]
+
+[FCVTXN2]
+
 [FCVTZS]
 
 [FCVTZU]
 
-[SCVTF]
+[FDIV]
 
-[UCVTF]
+[FMADD]
+
+[FMAX]
+
+[FMAXNM]
+
+[FMAXNMP]
+
+[FMANMV]
+
+[FMAXP]
+
+[FMAXV]
+
+[FMIN]
+
+[FMINNM]
+
+[FMINNMP]
+
+[FMINNMV]
+
+[FMINP]
+
+[FMINV]
+
+[FMLA]
+
+[FMLS]
+
+[FMOV]
+
+[FMSUB]
+
+[FMUL]
+
+[FMULX]
+
+[FNEG]
+
+[FNMADD]
+
+[FNMSUB]
+
+[FNMUL]
+
+[FRECPE]
+
+[FRECPS]
+
+[FRECPX]
 
 [FRINTA]
 
@@ -337,50 +428,373 @@
 
 [FRINTZ]
 
-[FABS]
+[FRSQRTE]
 
-[FNEG]
+[FRSQRTS]
 
 [FSQRT]
 
-[FADD]
+[FSUB]
 
-[FDIV]
+[LD1]
 
-[FMUL]
+[LD1R]
 
-[FNMUL]
+[LD2]
 
-[FSUB]
+[LD2R]
 
-[FMAX]
+[LD3]
 
-[FMIN]
+[LD3R]
 
-[FMINNM]
+[LD4]
 
-[FMADD]
+[LD4R]
 
-[FMSUB]
+[MLA]
 
-[FNMADD]
+[MLS]
 
-[FNMSUB]
+[MOVI]
 
-[FCMP]
+[MVNI]
 
-[FCMPE]
+[PMUL]
 
-[FCCMP]
+[PMULL]
 
-[FCMMPE]
+[PMULL2]
 
-[FCSEL]
+[RADDHN]
+
+[RADDHN2]
+
+[REV64]
+
+[RSHRN]
+
+[RSHRN2]
+
+[SRUBHN]
+
+[RSUBHN2]
+
+[SABA]
+
+[SABAL]
+
+[SABAL2]
+
+[SADALP]
+
+[SADDL]
+
+[SADDL2]
+
+[SADDLP]
+
+[SADDLV]
+
+[SADDW]
+
+[SADDW2]
+
+[SCVTF]
+
+[SHAC1C]
+
+[SHA1H]
+
+[SHA1M]
+
+[SHA1P]
+
+[SHA1SU0]
+
+[SHA1SU1]
+
+[SHA256H2]
+
+[SHA256H]
+
+[SHA256SU0]
+
+[SHA256SU1]
+
+[SHADD]
+
+[SHL]
+
+[SHLL]
+
+[SHLL2]
+
+[SHRN]
+
+[SHRN2]
+
+[SHSUB]
+
+[SLI]
+
+[SMAX]
+
+[SMAXP]
+
+[SMAXC]
+
+[SMIN]
+
+[SMINP]
+
+[SMINV]
+
+[SMLAL]
+
+[SMLAL2]
+
+[SMLSL]
+
+[SMLSL2]
+
+[SMOV]
+
+[SMULL]
+
+[SMULL2]
+
+[SQABS]
+
+[SQADD]
+
+[SQDMLAL]
+
+[SQDMLAL2]
+
+[SQDMLSL]
+
+[SQDMLSL2]
+
+[SQDMULH]
+
+[SQDMULL]
+
+[SQDMULL2]
+
+[SQNEG]
+
+[SQRDMULH]
+
+[SQRSHL]
+
+[SQRSHRN]
+
+[SQRSHRN2]
+
+[SQRSHRUN]
+
+[SQRSHRUN2]
+
+[SQSHL]
+
+[SQSHLU]
+
+[SQSHRN]
+
+[SQSRHN2]
+
+[SQSHRUN]
+
+[SQSHRUN2]
+
+[SQSUB]
+
+[SQXTN]
+
+[SQXTN2]
+
+[SQXTUN]
+
+[SQXTUN2]
+
+[SRHQDD]
+
+[SRI]
+
+[SRSHL]
+
+[SRSHR]
+
+[SRSRA]
+
+[SSHL]
+
+[SSHLL]
+
+[SSHLL2]
+
+[SSHR]
+
+[SSRA]
+
+[SSUBL]
+
+[SSUBL2]
+
+[SSUBW]
+
+[SSUBW2]
+
+[ST1]
+
+[ST2]
+
+[ST3]
+
+[ST4]
+
+[SUBQADD]
+
+[SXTL]
+
+[TBL]
+
+[TBX]
+
+[TRN1]
+
+[TRN2]
+
+[UABA]
+
+[UABAL]
+
+[UABAL2]
+
+[UABD]
+
+[UABDL]
+
+[UABDL2]
+
+[UADALP]
+
+[UADDLL]
+
+[UADDLL2]
+
+[UADDLP]
+
+[UADDLV]
+
+[UADDW]
+
+[UADDW2]
+
+[UCVTF]
+
+[UHADD]
+
+[UHSUB]
+
+[UMAX]
+
+[UMAXP]
+
+[UMAXV]
+
+[UMIN]
+
+[UMINP]
+
+[UMINV]
+
+[UMLAL]
+
+[UMLAL2]
+
+[UMLSL]
+
+[UMLSL2]
 
 [UMOV]
 
-[INS]
+[UQADD]
 
-[MOVI]
+[UQRSHL]
+
+[UQRSHRN]
+
+[UQRSHRN2]
+
+[UQSHL]
+
+[UQSHRN]
+
+[UQSUB]
+
+[UQXTN]
+
+[UQXTN2]
+
+[URECPE]
+
+[URHADD]
+
+[URSHL]
+
+[URSHR]
+
+[URSQRTE]
+
+[URSRA]
+
+[USHL]
+
+[USHLL2]
+
+[USHR]
+
+[USQADD]
+
+[USRA]
+
+[USUBL]
+
+[USUBL2]
+
+[USUBW]
+
+[USUBW2]
+
+[UXTL]
+
+[UZP1]
+
+[UZP2]
+
+[XTN1]
+
+[XTN2]
+
+[ZIP1]
+
+[ZIP2]
+
+; Aliases
+; they are not generated by the compiler, they are only used for inline assembler
+[NOP]
+
+[ASR]
+
+[LSL]
+
+[LSR]
+
+[ROR]
+
+[NEG]
+
+[INS]
 
-[VEOR]

compiler/aarch64/a64op.inc

@@ -47,18 +47,6 @@ A_STLR,
 A_LDAXR,
 A_STLXR,
 A_STLXP,
-A_LD1,
-A_LD2,
-A_LD3,
-A_LD4,
-A_ST1,
-A_ST2,
-A_ST3,
-A_ST4,
-A_LD1R,
-A_LD2R,
-A_LD3R,
-A_LD4R,
 A_PRFM,
 A_PRFUM,
 A_ADD,
@@ -111,35 +99,11 @@ A_CSINV,
 A_CSNEG,
 A_CCMN,
 A_CCMP,
-A_NOP,
-A_YIELD,
-A_WFE,
-A_WFI,
-A_SEV,
-A_SEVL,
-A_MOV,
-A_BFI,
-A_BFXIL,
-A_SBFIZ,
-A_SBFX,
-A_UBFIZ,
-A_UBFX,
-A_ASR,
-A_LSL,
-A_LSR,
-A_ROR,
-A_SXTB,
-A_SXTH,
-A_SXTW,
-A_UXTB,
-A_UXTH,
-A_NEG,
 A_NGC,
 A_MVN,
 A_MNEG,
 A_MUL,
 A_SMNEGL,
-A_SMULL,
 A_UMNEGL,
 A_UMULL,
 A_CSET,
@@ -147,20 +111,102 @@ A_CSETM,
 A_CINC,
 A_CINV,
 A_CNEG,
-A_FMOV,
+A_SXTB,
+A_SXTH,
+A_SXTW,
+A_UXTB,
+A_UXTH,
+A_BFI,
+A_BFXIL,
+A_SBFIZ,
+A_SBFX,
+A_UBFIZ,
+A_UBFX,
+A_YIELD,
+A_WFE,
+A_WFI,
+A_SEV,
+A_SEVL,
+A_MOV,
+A_ADDHN,
+A_ADDHN2,
+A_ADDP,
+A_ADDV,
+A_AESD,
+A_AESE,
+A_AESIMC,
+A_EASMC,
+A_BIF,
+A_BIT,
+A_BSL,
+A_CMEQ,
+A_CMGE,
+A_CMGT,
+A_CMHI,
+A_CMHS,
+A_CMLE,
+A_CMLT,
+A_CMTST,
+A_CNT,
+A_DUP,
+A_EXT,
+A_FABD,
+A_BACGE,
+A_FABS,
+A_FACGT,
+A_FADD,
+A_FCCMP,
+A_FCCMPE,
+A_FCMEQ,
+A_FCMGE,
+A_FCMGT,
+A_FCMLE,
+A_FCMLT,
+A_FCMP,
+A_FCMPE,
+A_FCSEL,
 A_FCVT,
 A_FCVTAS,
 A_FCVTAU,
+A_FCVTL,
+A_FCVTL2,
 A_FCVTMS,
 A_FCVTMU,
 A_FCVTNS,
 A_FCVTNU,
 A_FCVTPS,
 A_FCVTPU,
+A_FCVTXN,
+A_FCVTXN2,
 A_FCVTZS,
 A_FCVTZU,
-A_SCVTF,
-A_UCVTF,
+A_FDIV,
+A_FMADD,
+A_FMAX,
+A_FMAXNM,
+A_FMAXNMP,
+A_FMANMV,
+A_FMAXP,
+A_FMAXV,
+A_FMIN,
+A_FMINNM,
+A_FMINNMP,
+A_FMINNMV,
+A_FMINP,
+A_FMINV,
+A_FMLA,
+A_FMLS,
+A_FMOV,
+A_FMSUB,
+A_FMUL,
+A_FMULX,
+A_FNEG,
+A_FNMADD,
+A_FNMSUB,
+A_FNMUL,
+A_FRECPE,
+A_FRECPS,
+A_FRECPX,
 A_FRINTA,
 A_FRINTI,
 A_FRINTM,
@@ -168,28 +214,188 @@ A_FRINTN,
 A_FRINTP,
 A_FRINTX,
 A_FRINTZ,
-A_FABS,
-A_FNEG,
+A_FRSQRTE,
+A_FRSQRTS,
 A_FSQRT,
-A_FADD,
-A_FDIV,
-A_FMUL,
-A_FNMUL,
 A_FSUB,
-A_FMAX,
-A_FMIN,
-A_FMINNM,
-A_FMADD,
-A_FMSUB,
-A_FNMADD,
-A_FNMSUB,
-A_FCMP,
-A_FCMPE,
-A_FCCMP,
-A_FCMMPE,
-A_FCSEL,
-A_UMOV,
-A_INS,
+A_LD1,
+A_LD1R,
+A_LD2,
+A_LD2R,
+A_LD3,
+A_LD3R,
+A_LD4,
+A_LD4R,
+A_MLA,
+A_MLS,
 A_MOVI,
-A_VEOR
+A_MVNI,
+A_PMUL,
+A_PMULL,
+A_PMULL2,
+A_RADDHN,
+A_RADDHN2,
+A_REV64,
+A_RSHRN,
+A_RSHRN2,
+A_SRUBHN,
+A_RSUBHN2,
+A_SABA,
+A_SABAL,
+A_SABAL2,
+A_SADALP,
+A_SADDL,
+A_SADDL2,
+A_SADDLP,
+A_SADDLV,
+A_SADDW,
+A_SADDW2,
+A_SCVTF,
+A_SHAC1C,
+A_SHA1H,
+A_SHA1M,
+A_SHA1P,
+A_SHA1SU0,
+A_SHA1SU1,
+A_SHA256H2,
+A_SHA256H,
+A_SHA256SU0,
+A_SHA256SU1,
+A_SHADD,
+A_SHL,
+A_SHLL,
+A_SHLL2,
+A_SHRN,
+A_SHRN2,
+A_SHSUB,
+A_SLI,
+A_SMAX,
+A_SMAXP,
+A_SMAXC,
+A_SMIN,
+A_SMINP,
+A_SMINV,
+A_SMLAL,
+A_SMLAL2,
+A_SMLSL,
+A_SMLSL2,
+A_SMOV,
+A_SMULL,
+A_SMULL2,
+A_SQABS,
+A_SQADD,
+A_SQDMLAL,
+A_SQDMLAL2,
+A_SQDMLSL,
+A_SQDMLSL2,
+A_SQDMULH,
+A_SQDMULL,
+A_SQDMULL2,
+A_SQNEG,
+A_SQRDMULH,
+A_SQRSHL,
+A_SQRSHRN,
+A_SQRSHRN2,
+A_SQRSHRUN,
+A_SQRSHRUN2,
+A_SQSHL,
+A_SQSHLU,
+A_SQSHRN,
+A_SQSRHN2,
+A_SQSHRUN,
+A_SQSHRUN2,
+A_SQSUB,
+A_SQXTN,
+A_SQXTN2,
+A_SQXTUN,
+A_SQXTUN2,
+A_SRHQDD,
+A_SRI,
+A_SRSHL,
+A_SRSHR,
+A_SRSRA,
+A_SSHL,
+A_SSHLL,
+A_SSHLL2,
+A_SSHR,
+A_SSRA,
+A_SSUBL,
+A_SSUBL2,
+A_SSUBW,
+A_SSUBW2,
+A_ST1,
+A_ST2,
+A_ST3,
+A_ST4,
+A_SUBQADD,
+A_SXTL,
+A_TBL,
+A_TBX,
+A_TRN1,
+A_TRN2,
+A_UABA,
+A_UABAL,
+A_UABAL2,
+A_UABD,
+A_UABDL,
+A_UABDL2,
+A_UADALP,
+A_UADDLL,
+A_UADDLL2,
+A_UADDLP,
+A_UADDLV,
+A_UADDW,
+A_UADDW2,
+A_UCVTF,
+A_UHADD,
+A_UHSUB,
+A_UMAX,
+A_UMAXP,
+A_UMAXV,
+A_UMIN,
+A_UMINP,
+A_UMINV,
+A_UMLAL,
+A_UMLAL2,
+A_UMLSL,
+A_UMLSL2,
+A_UMOV,
+A_UQADD,
+A_UQRSHL,
+A_UQRSHRN,
+A_UQRSHRN2,
+A_UQSHL,
+A_UQSHRN,
+A_UQSUB,
+A_UQXTN,
+A_UQXTN2,
+A_URECPE,
+A_URHADD,
+A_URSHL,
+A_URSHR,
+A_URSQRTE,
+A_URSRA,
+A_USHL,
+A_USHLL2,
+A_USHR,
+A_USQADD,
+A_USRA,
+A_USUBL,
+A_USUBL2,
+A_USUBW,
+A_USUBW2,
+A_UXTL,
+A_UZP1,
+A_UZP2,
+A_XTN1,
+A_XTN2,
+A_ZIP1,
+A_ZIP2,
+A_NOP,
+A_ASR,
+A_LSL,
+A_LSR,
+A_ROR,
+A_NEG,
+A_INS
 );

compiler/aarch64/a64reg.dat

@@ -76,235 +76,586 @@ XZR,$01,$05,$1F,xzr,31,31
 WSP,$01,$04,$20,wsp,31,31
 SP,$01,$05,$20,sp,31,31
 
+NZCV,$05,$00,$00,nzcv,0,0
+FPCR,$05,$00,$01,fpcr,0,0
+FPSR,$05,$00,$02,fpsr,0,0
+TPIDR_EL0,$05,$00,$03,tpidr_el0,0,0
+
 ; vfp registers
 ; generated by fpc/compiler/utils/gena64vfp.pp to avoid tedious typing
 B0,$04,$01,$00,b0,64,64
 H0,$04,$03,$00,h0,64,64
 S0,$04,$09,$00,s0,64,64
 D0,$04,$0a,$00,d0,64,64
-Q0,$04,$05,$00,q0,64,64
-V08B,$04,$17,$00,v0.8b,64,64
-V016B,$04,$18,$00,v0.16b,64,64
+Q0,$04,$0b,$00,q0,64,64
+V0,$04,$00,$00,v0,64,64
+V0_B,$04,$20,$00,v0.b,64,64
+V0_H,$04,$21,$00,v0.h,64,64
+V0_S,$04,$22,$00,v0.s,64,64
+V0_D,$04,$23,$00,v0.d,64,64
+V0_8B,$04,$18,$00,v0.8b,64,64
+V0_16B,$04,$19,$00,v0.16b,64,64
+V0_4H,$04,$1a,$00,v0.4h,64,64
+V0_8H,$04,$1b,$00,v0.8h,64,64
+V0_2S,$04,$1c,$00,v0.2s,64,64
+V0_4S,$04,$1d,$00,v0.4s,64,64
+V0_1D,$04,$1e,$00,v0.1d,64,64
+V0_2D,$04,$1f,$00,v0.2d,64,64
 B1,$04,$01,$01,b1,65,65
 H1,$04,$03,$01,h1,65,65
 S1,$04,$09,$01,s1,65,65
 D1,$04,$0a,$01,d1,65,65
-Q1,$04,$05,$01,q1,65,65
-V18B,$04,$17,$01,v1.8b,65,65
-V116B,$04,$18,$01,v1.16b,65,65
+Q1,$04,$0b,$01,q1,65,65
+V1,$04,$00,$01,v1,65,65
+V1_B,$04,$20,$01,v1.b,65,65
+V1_H,$04,$21,$01,v1.h,65,65
+V1_S,$04,$22,$01,v1.s,65,65
+V1_D,$04,$23,$01,v1.d,65,65
+V1_8B,$04,$18,$01,v1.8b,65,65
+V1_16B,$04,$19,$01,v1.16b,65,65
+V1_4H,$04,$1a,$01,v1.4h,65,65
+V1_8H,$04,$1b,$01,v1.8h,65,65
+V1_2S,$04,$1c,$01,v1.2s,65,65
+V1_4S,$04,$1d,$01,v1.4s,65,65
+V1_1D,$04,$1e,$01,v1.1d,65,65
+V1_2D,$04,$1f,$01,v1.2d,65,65
 B2,$04,$01,$02,b2,66,66
 H2,$04,$03,$02,h2,66,66
 S2,$04,$09,$02,s2,66,66
 D2,$04,$0a,$02,d2,66,66
-Q2,$04,$05,$02,q2,66,66
-V28B,$04,$17,$02,v2.8b,66,66
-V216B,$04,$18,$02,v2.16b,66,66
+Q2,$04,$0b,$02,q2,66,66
+V2,$04,$00,$02,v2,66,66
+V2_B,$04,$20,$02,v2.b,66,66
+V2_H,$04,$21,$02,v2.h,66,66
+V2_S,$04,$22,$02,v2.s,66,66
+V2_D,$04,$23,$02,v2.d,66,66
+V2_8B,$04,$18,$02,v2.8b,66,66
+V2_16B,$04,$19,$02,v2.16b,66,66
+V2_4H,$04,$1a,$02,v2.4h,66,66
+V2_8H,$04,$1b,$02,v2.8h,66,66
+V2_2S,$04,$1c,$02,v2.2s,66,66
+V2_4S,$04,$1d,$02,v2.4s,66,66
+V2_1D,$04,$1e,$02,v2.1d,66,66
+V2_2D,$04,$1f,$02,v2.2d,66,66
 B3,$04,$01,$03,b3,67,67
 H3,$04,$03,$03,h3,67,67
 S3,$04,$09,$03,s3,67,67
 D3,$04,$0a,$03,d3,67,67
-Q3,$04,$05,$03,q3,67,67
-V38B,$04,$17,$03,v3.8b,67,67
-V316B,$04,$18,$03,v3.16b,67,67
+Q3,$04,$0b,$03,q3,67,67
+V3,$04,$00,$03,v3,67,67
+V3_B,$04,$20,$03,v3.b,67,67
+V3_H,$04,$21,$03,v3.h,67,67
+V3_S,$04,$22,$03,v3.s,67,67
+V3_D,$04,$23,$03,v3.d,67,67
+V3_8B,$04,$18,$03,v3.8b,67,67
+V3_16B,$04,$19,$03,v3.16b,67,67
+V3_4H,$04,$1a,$03,v3.4h,67,67
+V3_8H,$04,$1b,$03,v3.8h,67,67
+V3_2S,$04,$1c,$03,v3.2s,67,67
+V3_4S,$04,$1d,$03,v3.4s,67,67
+V3_1D,$04,$1e,$03,v3.1d,67,67
+V3_2D,$04,$1f,$03,v3.2d,67,67
 B4,$04,$01,$04,b4,68,68
 H4,$04,$03,$04,h4,68,68
 S4,$04,$09,$04,s4,68,68
 D4,$04,$0a,$04,d4,68,68
-Q4,$04,$05,$04,q4,68,68
-V48B,$04,$17,$04,v4.8b,68,68
-V416B,$04,$18,$04,v4.16b,68,68
+Q4,$04,$0b,$04,q4,68,68
+V4,$04,$00,$04,v4,68,68
+V4_B,$04,$20,$04,v4.b,68,68
+V4_H,$04,$21,$04,v4.h,68,68
+V4_S,$04,$22,$04,v4.s,68,68
+V4_D,$04,$23,$04,v4.d,68,68
+V4_8B,$04,$18,$04,v4.8b,68,68
+V4_16B,$04,$19,$04,v4.16b,68,68
+V4_4H,$04,$1a,$04,v4.4h,68,68
+V4_8H,$04,$1b,$04,v4.8h,68,68
+V4_2S,$04,$1c,$04,v4.2s,68,68
+V4_4S,$04,$1d,$04,v4.4s,68,68
+V4_1D,$04,$1e,$04,v4.1d,68,68
+V4_2D,$04,$1f,$04,v4.2d,68,68
 B5,$04,$01,$05,b5,69,69
 H5,$04,$03,$05,h5,69,69
 S5,$04,$09,$05,s5,69,69
 D5,$04,$0a,$05,d5,69,69
-Q5,$04,$05,$05,q5,69,69
-V58B,$04,$17,$05,v5.8b,69,69
-V516B,$04,$18,$05,v5.16b,69,69
+Q5,$04,$0b,$05,q5,69,69
+V5,$04,$00,$05,v5,69,69
+V5_B,$04,$20,$05,v5.b,69,69
+V5_H,$04,$21,$05,v5.h,69,69
+V5_S,$04,$22,$05,v5.s,69,69
+V5_D,$04,$23,$05,v5.d,69,69
+V5_8B,$04,$18,$05,v5.8b,69,69
+V5_16B,$04,$19,$05,v5.16b,69,69
+V5_4H,$04,$1a,$05,v5.4h,69,69
+V5_8H,$04,$1b,$05,v5.8h,69,69
+V5_2S,$04,$1c,$05,v5.2s,69,69
+V5_4S,$04,$1d,$05,v5.4s,69,69
+V5_1D,$04,$1e,$05,v5.1d,69,69
+V5_2D,$04,$1f,$05,v5.2d,69,69
 B6,$04,$01,$06,b6,70,70
 H6,$04,$03,$06,h6,70,70
-S6,$04,$09,$06,s6,70,70                                                                     gena64vfp.pp
+S6,$04,$09,$06,s6,70,70
 D6,$04,$0a,$06,d6,70,70
-Q6,$04,$05,$06,q6,70,70
-V68B,$04,$17,$06,v6.8b,70,70
-V616B,$04,$18,$06,v6.16b,70,70
+Q6,$04,$0b,$06,q6,70,70
+V6,$04,$00,$06,v6,70,70
+V6_B,$04,$20,$06,v6.b,70,70
+V6_H,$04,$21,$06,v6.h,70,70
+V6_S,$04,$22,$06,v6.s,70,70
+V6_D,$04,$23,$06,v6.d,70,70
+V6_8B,$04,$18,$06,v6.8b,70,70
+V6_16B,$04,$19,$06,v6.16b,70,70
+V6_4H,$04,$1a,$06,v6.4h,70,70
+V6_8H,$04,$1b,$06,v6.8h,70,70
+V6_2S,$04,$1c,$06,v6.2s,70,70
+V6_4S,$04,$1d,$06,v6.4s,70,70
+V6_1D,$04,$1e,$06,v6.1d,70,70
+V6_2D,$04,$1f,$06,v6.2d,70,70
 B7,$04,$01,$07,b7,71,71
 H7,$04,$03,$07,h7,71,71
 S7,$04,$09,$07,s7,71,71
 D7,$04,$0a,$07,d7,71,71
-Q7,$04,$05,$07,q7,71,71
-V78B,$04,$17,$07,v7.8b,71,71
-V716B,$04,$18,$07,v7.16b,71,71
+Q7,$04,$0b,$07,q7,71,71
+V7,$04,$00,$07,v7,71,71
+V7_B,$04,$20,$07,v7.b,71,71
+V7_H,$04,$21,$07,v7.h,71,71
+V7_S,$04,$22,$07,v7.s,71,71
+V7_D,$04,$23,$07,v7.d,71,71
+V7_8B,$04,$18,$07,v7.8b,71,71
+V7_16B,$04,$19,$07,v7.16b,71,71
+V7_4H,$04,$1a,$07,v7.4h,71,71
+V7_8H,$04,$1b,$07,v7.8h,71,71
+V7_2S,$04,$1c,$07,v7.2s,71,71
+V7_4S,$04,$1d,$07,v7.4s,71,71
+V7_1D,$04,$1e,$07,v7.1d,71,71
+V7_2D,$04,$1f,$07,v7.2d,71,71
 B8,$04,$01,$08,b8,72,72
 H8,$04,$03,$08,h8,72,72
 S8,$04,$09,$08,s8,72,72
 D8,$04,$0a,$08,d8,72,72
-Q8,$04,$05,$08,q8,72,72
-V88B,$04,$17,$08,v8.8b,72,72
-V816B,$04,$18,$08,v8.16b,72,72
+Q8,$04,$0b,$08,q8,72,72
+V8,$04,$00,$08,v8,72,72
+V8_B,$04,$20,$08,v8.b,72,72
+V8_H,$04,$21,$08,v8.h,72,72
+V8_S,$04,$22,$08,v8.s,72,72
+V8_D,$04,$23,$08,v8.d,72,72
+V8_8B,$04,$18,$08,v8.8b,72,72
+V8_16B,$04,$19,$08,v8.16b,72,72
+V8_4H,$04,$1a,$08,v8.4h,72,72
+V8_8H,$04,$1b,$08,v8.8h,72,72
+V8_2S,$04,$1c,$08,v8.2s,72,72
+V8_4S,$04,$1d,$08,v8.4s,72,72
+V8_1D,$04,$1e,$08,v8.1d,72,72
+V8_2D,$04,$1f,$08,v8.2d,72,72
 B9,$04,$01,$09,b9,73,73
 H9,$04,$03,$09,h9,73,73
 S9,$04,$09,$09,s9,73,73
 D9,$04,$0a,$09,d9,73,73
-Q9,$04,$05,$09,q9,73,73
-V98B,$04,$17,$09,v9.8b,73,73
-V916B,$04,$18,$09,v9.16b,73,73
+Q9,$04,$0b,$09,q9,73,73
+V9,$04,$00,$09,v9,73,73
+V9_B,$04,$20,$09,v9.b,73,73
+V9_H,$04,$21,$09,v9.h,73,73
+V9_S,$04,$22,$09,v9.s,73,73
+V9_D,$04,$23,$09,v9.d,73,73
+V9_8B,$04,$18,$09,v9.8b,73,73
+V9_16B,$04,$19,$09,v9.16b,73,73
+V9_4H,$04,$1a,$09,v9.4h,73,73
+V9_8H,$04,$1b,$09,v9.8h,73,73
+V9_2S,$04,$1c,$09,v9.2s,73,73
+V9_4S,$04,$1d,$09,v9.4s,73,73
+V9_1D,$04,$1e,$09,v9.1d,73,73
+V9_2D,$04,$1f,$09,v9.2d,73,73
 B10,$04,$01,$0A,b10,74,74
 H10,$04,$03,$0A,h10,74,74
 S10,$04,$09,$0A,s10,74,74
 D10,$04,$0a,$0A,d10,74,74
-Q10,$04,$05,$0A,q10,74,74
-V108B,$04,$17,$0A,v10.8b,74,74
-V1016B,$04,$18,$0A,v10.16b,74,74
+Q10,$04,$0b,$0A,q10,74,74
+V10,$04,$00,$0A,v10,74,74
+V10_B,$04,$20,$0A,v10.b,74,74
+V10_H,$04,$21,$0A,v10.h,74,74
+V10_S,$04,$22,$0A,v10.s,74,74
+V10_D,$04,$23,$0A,v10.d,74,74
+V10_8B,$04,$18,$0A,v10.8b,74,74
+V10_16B,$04,$19,$0A,v10.16b,74,74
+V10_4H,$04,$1a,$0A,v10.4h,74,74
+V10_8H,$04,$1b,$0A,v10.8h,74,74
+V10_2S,$04,$1c,$0A,v10.2s,74,74
+V10_4S,$04,$1d,$0A,v10.4s,74,74
+V10_1D,$04,$1e,$0A,v10.1d,74,74
+V10_2D,$04,$1f,$0A,v10.2d,74,74
 B11,$04,$01,$0B,b11,75,75
 H11,$04,$03,$0B,h11,75,75
 S11,$04,$09,$0B,s11,75,75
 D11,$04,$0a,$0B,d11,75,75
-Q11,$04,$05,$0B,q11,75,75
-V118B,$04,$17,$0B,v11.8b,75,75
-V1116B,$04,$18,$0B,v11.16b,75,75
+Q11,$04,$0b,$0B,q11,75,75
+V11,$04,$00,$0B,v11,75,75
+V11_B,$04,$20,$0B,v11.b,75,75
+V11_H,$04,$21,$0B,v11.h,75,75
+V11_S,$04,$22,$0B,v11.s,75,75
+V11_D,$04,$23,$0B,v11.d,75,75
+V11_8B,$04,$18,$0B,v11.8b,75,75
+V11_16B,$04,$19,$0B,v11.16b,75,75
+V11_4H,$04,$1a,$0B,v11.4h,75,75
+V11_8H,$04,$1b,$0B,v11.8h,75,75
+V11_2S,$04,$1c,$0B,v11.2s,75,75
+V11_4S,$04,$1d,$0B,v11.4s,75,75
+V11_1D,$04,$1e,$0B,v11.1d,75,75
+V11_2D,$04,$1f,$0B,v11.2d,75,75
 B12,$04,$01,$0C,b12,76,76
 H12,$04,$03,$0C,h12,76,76
 S12,$04,$09,$0C,s12,76,76
 D12,$04,$0a,$0C,d12,76,76
-Q12,$04,$05,$0C,q12,76,76
-V128B,$04,$17,$0C,v12.8b,76,76
-V1216B,$04,$18,$0C,v12.16b,76,76
+Q12,$04,$0b,$0C,q12,76,76
+V12,$04,$00,$0C,v12,76,76
+V12_B,$04,$20,$0C,v12.b,76,76
+V12_H,$04,$21,$0C,v12.h,76,76
+V12_S,$04,$22,$0C,v12.s,76,76
+V12_D,$04,$23,$0C,v12.d,76,76
+V12_8B,$04,$18,$0C,v12.8b,76,76
+V12_16B,$04,$19,$0C,v12.16b,76,76
+V12_4H,$04,$1a,$0C,v12.4h,76,76
+V12_8H,$04,$1b,$0C,v12.8h,76,76
+V12_2S,$04,$1c,$0C,v12.2s,76,76
+V12_4S,$04,$1d,$0C,v12.4s,76,76
+V12_1D,$04,$1e,$0C,v12.1d,76,76
+V12_2D,$04,$1f,$0C,v12.2d,76,76
 B13,$04,$01,$0D,b13,77,77
 H13,$04,$03,$0D,h13,77,77
 S13,$04,$09,$0D,s13,77,77
 D13,$04,$0a,$0D,d13,77,77
-Q13,$04,$05,$0D,q13,77,77
-V138B,$04,$17,$0D,v13.8b,77,77
-V1316B,$04,$18,$0D,v13.16b,77,77
+Q13,$04,$0b,$0D,q13,77,77
+V13,$04,$00,$0D,v13,77,77
+V13_B,$04,$20,$0D,v13.b,77,77
+V13_H,$04,$21,$0D,v13.h,77,77
+V13_S,$04,$22,$0D,v13.s,77,77
+V13_D,$04,$23,$0D,v13.d,77,77
+V13_8B,$04,$18,$0D,v13.8b,77,77
+V13_16B,$04,$19,$0D,v13.16b,77,77
+V13_4H,$04,$1a,$0D,v13.4h,77,77
+V13_8H,$04,$1b,$0D,v13.8h,77,77
+V13_2S,$04,$1c,$0D,v13.2s,77,77
+V13_4S,$04,$1d,$0D,v13.4s,77,77
+V13_1D,$04,$1e,$0D,v13.1d,77,77
+V13_2D,$04,$1f,$0D,v13.2d,77,77
 B14,$04,$01,$0E,b14,78,78
 H14,$04,$03,$0E,h14,78,78
 S14,$04,$09,$0E,s14,78,78
 D14,$04,$0a,$0E,d14,78,78
-Q14,$04,$05,$0E,q14,78,78
-V148B,$04,$17,$0E,v14.8b,78,78
-V1416B,$04,$18,$0E,v14.16b,78,78
+Q14,$04,$0b,$0E,q14,78,78
+V14,$04,$00,$0E,v14,78,78
+V14_B,$04,$20,$0E,v14.b,78,78
+V14_H,$04,$21,$0E,v14.h,78,78
+V14_S,$04,$22,$0E,v14.s,78,78
+V14_D,$04,$23,$0E,v14.d,78,78
+V14_8B,$04,$18,$0E,v14.8b,78,78
+V14_16B,$04,$19,$0E,v14.16b,78,78
+V14_4H,$04,$1a,$0E,v14.4h,78,78
+V14_8H,$04,$1b,$0E,v14.8h,78,78
+V14_2S,$04,$1c,$0E,v14.2s,78,78
+V14_4S,$04,$1d,$0E,v14.4s,78,78
+V14_1D,$04,$1e,$0E,v14.1d,78,78
+V14_2D,$04,$1f,$0E,v14.2d,78,78
 B15,$04,$01,$0F,b15,79,79
 H15,$04,$03,$0F,h15,79,79
 S15,$04,$09,$0F,s15,79,79
 D15,$04,$0a,$0F,d15,79,79
-Q15,$04,$05,$0F,q15,79,79
-V158B,$04,$17,$0F,v15.8b,79,79
-V1516B,$04,$18,$0F,v15.16b,79,79
+Q15,$04,$0b,$0F,q15,79,79
+V15,$04,$00,$0F,v15,79,79
+V15_B,$04,$20,$0F,v15.b,79,79
+V15_H,$04,$21,$0F,v15.h,79,79
+V15_S,$04,$22,$0F,v15.s,79,79
+V15_D,$04,$23,$0F,v15.d,79,79
+V15_8B,$04,$18,$0F,v15.8b,79,79
+V15_16B,$04,$19,$0F,v15.16b,79,79
+V15_4H,$04,$1a,$0F,v15.4h,79,79
+V15_8H,$04,$1b,$0F,v15.8h,79,79
+V15_2S,$04,$1c,$0F,v15.2s,79,79
+V15_4S,$04,$1d,$0F,v15.4s,79,79
+V15_1D,$04,$1e,$0F,v15.1d,79,79
+V15_2D,$04,$1f,$0F,v15.2d,79,79
 B16,$04,$01,$10,b16,80,80
 H16,$04,$03,$10,h16,80,80
 S16,$04,$09,$10,s16,80,80
 D16,$04,$0a,$10,d16,80,80
-Q16,$04,$05,$10,q16,80,80
-V168B,$04,$17,$10,v16.8b,80,80
-V1616B,$04,$18,$10,v16.16b,80,80
+Q16,$04,$0b,$10,q16,80,80
+V16,$04,$00,$10,v16,80,80
+V16_B,$04,$20,$10,v16.b,80,80
+V16_H,$04,$21,$10,v16.h,80,80
+V16_S,$04,$22,$10,v16.s,80,80
+V16_D,$04,$23,$10,v16.d,80,80
+V16_8B,$04,$18,$10,v16.8b,80,80
+V16_16B,$04,$19,$10,v16.16b,80,80
+V16_4H,$04,$1a,$10,v16.4h,80,80
+V16_8H,$04,$1b,$10,v16.8h,80,80
+V16_2S,$04,$1c,$10,v16.2s,80,80
+V16_4S,$04,$1d,$10,v16.4s,80,80
+V16_1D,$04,$1e,$10,v16.1d,80,80
+V16_2D,$04,$1f,$10,v16.2d,80,80
 B17,$04,$01,$11,b17,81,81
 H17,$04,$03,$11,h17,81,81
 S17,$04,$09,$11,s17,81,81
 D17,$04,$0a,$11,d17,81,81
-Q17,$04,$05,$11,q17,81,81
-V178B,$04,$17,$11,v17.8b,81,81
-V1716B,$04,$18,$11,v17.16b,81,81
+Q17,$04,$0b,$11,q17,81,81
+V17,$04,$00,$11,v17,81,81
+V17_B,$04,$20,$11,v17.b,81,81
+V17_H,$04,$21,$11,v17.h,81,81
+V17_S,$04,$22,$11,v17.s,81,81
+V17_D,$04,$23,$11,v17.d,81,81
+V17_8B,$04,$18,$11,v17.8b,81,81
+V17_16B,$04,$19,$11,v17.16b,81,81
+V17_4H,$04,$1a,$11,v17.4h,81,81
+V17_8H,$04,$1b,$11,v17.8h,81,81
+V17_2S,$04,$1c,$11,v17.2s,81,81
+V17_4S,$04,$1d,$11,v17.4s,81,81
+V17_1D,$04,$1e,$11,v17.1d,81,81
+V17_2D,$04,$1f,$11,v17.2d,81,81
 B18,$04,$01,$12,b18,82,82
 H18,$04,$03,$12,h18,82,82
 S18,$04,$09,$12,s18,82,82
 D18,$04,$0a,$12,d18,82,82
-Q18,$04,$05,$12,q18,82,82
-V188B,$04,$17,$12,v18.8b,82,82
-V1816B,$04,$18,$12,v18.16b,82,82
+Q18,$04,$0b,$12,q18,82,82
+V18,$04,$00,$12,v18,82,82
+V18_B,$04,$20,$12,v18.b,82,82
+V18_H,$04,$21,$12,v18.h,82,82
+V18_S,$04,$22,$12,v18.s,82,82
+V18_D,$04,$23,$12,v18.d,82,82
+V18_8B,$04,$18,$12,v18.8b,82,82
+V18_16B,$04,$19,$12,v18.16b,82,82
+V18_4H,$04,$1a,$12,v18.4h,82,82
+V18_8H,$04,$1b,$12,v18.8h,82,82
+V18_2S,$04,$1c,$12,v18.2s,82,82
+V18_4S,$04,$1d,$12,v18.4s,82,82
+V18_1D,$04,$1e,$12,v18.1d,82,82
+V18_2D,$04,$1f,$12,v18.2d,82,82
 B19,$04,$01,$13,b19,83,83
 H19,$04,$03,$13,h19,83,83
 S19,$04,$09,$13,s19,83,83
 D19,$04,$0a,$13,d19,83,83
-Q19,$04,$05,$13,q19,83,83
-V198B,$04,$17,$13,v19.8b,83,83
-V1916B,$04,$18,$13,v19.16b,83,83
+Q19,$04,$0b,$13,q19,83,83
+V19,$04,$00,$13,v19,83,83
+V19_B,$04,$20,$13,v19.b,83,83
+V19_H,$04,$21,$13,v19.h,83,83
+V19_S,$04,$22,$13,v19.s,83,83
+V19_D,$04,$23,$13,v19.d,83,83
+V19_8B,$04,$18,$13,v19.8b,83,83
+V19_16B,$04,$19,$13,v19.16b,83,83
+V19_4H,$04,$1a,$13,v19.4h,83,83
+V19_8H,$04,$1b,$13,v19.8h,83,83
+V19_2S,$04,$1c,$13,v19.2s,83,83
+V19_4S,$04,$1d,$13,v19.4s,83,83
+V19_1D,$04,$1e,$13,v19.1d,83,83
+V19_2D,$04,$1f,$13,v19.2d,83,83
 B20,$04,$01,$14,b20,84,84
 H20,$04,$03,$14,h20,84,84
 S20,$04,$09,$14,s20,84,84
 D20,$04,$0a,$14,d20,84,84
-Q20,$04,$05,$14,q20,84,84
-V208B,$04,$17,$14,v20.8b,84,84
-V2016B,$04,$18,$14,v20.16b,84,84
+Q20,$04,$0b,$14,q20,84,84
+V20,$04,$00,$14,v20,84,84
+V20_B,$04,$20,$14,v20.b,84,84
+V20_H,$04,$21,$14,v20.h,84,84
+V20_S,$04,$22,$14,v20.s,84,84
+V20_D,$04,$23,$14,v20.d,84,84
+V20_8B,$04,$18,$14,v20.8b,84,84
+V20_16B,$04,$19,$14,v20.16b,84,84
+V20_4H,$04,$1a,$14,v20.4h,84,84
+V20_8H,$04,$1b,$14,v20.8h,84,84
+V20_2S,$04,$1c,$14,v20.2s,84,84
+V20_4S,$04,$1d,$14,v20.4s,84,84
+V20_1D,$04,$1e,$14,v20.1d,84,84
+V20_2D,$04,$1f,$14,v20.2d,84,84
 B21,$04,$01,$15,b21,85,85
 H21,$04,$03,$15,h21,85,85
 S21,$04,$09,$15,s21,85,85
 D21,$04,$0a,$15,d21,85,85
-Q21,$04,$05,$15,q21,85,85
-V218B,$04,$17,$15,v21.8b,85,85
-V2116B,$04,$18,$15,v21.16b,85,85
+Q21,$04,$0b,$15,q21,85,85
+V21,$04,$00,$15,v21,85,85
+V21_B,$04,$20,$15,v21.b,85,85
+V21_H,$04,$21,$15,v21.h,85,85
+V21_S,$04,$22,$15,v21.s,85,85
+V21_D,$04,$23,$15,v21.d,85,85
+V21_8B,$04,$18,$15,v21.8b,85,85
+V21_16B,$04,$19,$15,v21.16b,85,85
+V21_4H,$04,$1a,$15,v21.4h,85,85
+V21_8H,$04,$1b,$15,v21.8h,85,85
+V21_2S,$04,$1c,$15,v21.2s,85,85
+V21_4S,$04,$1d,$15,v21.4s,85,85
+V21_1D,$04,$1e,$15,v21.1d,85,85
+V21_2D,$04,$1f,$15,v21.2d,85,85
 B22,$04,$01,$16,b22,86,86
 H22,$04,$03,$16,h22,86,86
 S22,$04,$09,$16,s22,86,86
 D22,$04,$0a,$16,d22,86,86
-Q22,$04,$05,$16,q22,86,86
-V228B,$04,$17,$16,v22.8b,86,86
-V2216B,$04,$18,$16,v22.16b,86,86
+Q22,$04,$0b,$16,q22,86,86
+V22,$04,$00,$16,v22,86,86
+V22_B,$04,$20,$16,v22.b,86,86
+V22_H,$04,$21,$16,v22.h,86,86
+V22_S,$04,$22,$16,v22.s,86,86
+V22_D,$04,$23,$16,v22.d,86,86
+V22_8B,$04,$18,$16,v22.8b,86,86
+V22_16B,$04,$19,$16,v22.16b,86,86
+V22_4H,$04,$1a,$16,v22.4h,86,86
+V22_8H,$04,$1b,$16,v22.8h,86,86
+V22_2S,$04,$1c,$16,v22.2s,86,86
+V22_4S,$04,$1d,$16,v22.4s,86,86
+V22_1D,$04,$1e,$16,v22.1d,86,86
+V22_2D,$04,$1f,$16,v22.2d,86,86
 B23,$04,$01,$17,b23,87,87
 H23,$04,$03,$17,h23,87,87
 S23,$04,$09,$17,s23,87,87
 D23,$04,$0a,$17,d23,87,87
-Q23,$04,$05,$17,q23,87,87
-V238B,$04,$17,$17,v23.8b,87,87
-V2316B,$04,$18,$17,v23.16b,87,87
+Q23,$04,$0b,$17,q23,87,87
+V23,$04,$00,$17,v23,87,87
+V23_B,$04,$20,$17,v23.b,87,87
+V23_H,$04,$21,$17,v23.h,87,87
+V23_S,$04,$22,$17,v23.s,87,87
+V23_D,$04,$23,$17,v23.d,87,87
+V23_8B,$04,$18,$17,v23.8b,87,87
+V23_16B,$04,$19,$17,v23.16b,87,87
+V23_4H,$04,$1a,$17,v23.4h,87,87
+V23_8H,$04,$1b,$17,v23.8h,87,87
+V23_2S,$04,$1c,$17,v23.2s,87,87
+V23_4S,$04,$1d,$17,v23.4s,87,87
+V23_1D,$04,$1e,$17,v23.1d,87,87
+V23_2D,$04,$1f,$17,v23.2d,87,87
 B24,$04,$01,$18,b24,88,88
 H24,$04,$03,$18,h24,88,88
 S24,$04,$09,$18,s24,88,88
 D24,$04,$0a,$18,d24,88,88
-Q24,$04,$05,$18,q24,88,88
-V248B,$04,$17,$18,v24.8b,88,88
-V2416B,$04,$18,$18,v24.16b,88,88
+Q24,$04,$0b,$18,q24,88,88
+V24,$04,$00,$18,v24,88,88
+V24_B,$04,$20,$18,v24.b,88,88
+V24_H,$04,$21,$18,v24.h,88,88
+V24_S,$04,$22,$18,v24.s,88,88
+V24_D,$04,$23,$18,v24.d,88,88
+V24_8B,$04,$18,$18,v24.8b,88,88
+V24_16B,$04,$19,$18,v24.16b,88,88
+V24_4H,$04,$1a,$18,v24.4h,88,88
+V24_8H,$04,$1b,$18,v24.8h,88,88
+V24_2S,$04,$1c,$18,v24.2s,88,88
+V24_4S,$04,$1d,$18,v24.4s,88,88
+V24_1D,$04,$1e,$18,v24.1d,88,88
+V24_2D,$04,$1f,$18,v24.2d,88,88
 B25,$04,$01,$19,b25,89,89
 H25,$04,$03,$19,h25,89,89
 S25,$04,$09,$19,s25,89,89
 D25,$04,$0a,$19,d25,89,89
-Q25,$04,$05,$19,q25,89,89
-V258B,$04,$17,$19,v25.8b,89,89
-V2516B,$04,$18,$19,v25.16b,89,89
+Q25,$04,$0b,$19,q25,89,89
+V25,$04,$00,$19,v25,89,89
+V25_B,$04,$20,$19,v25.b,89,89
+V25_H,$04,$21,$19,v25.h,89,89
+V25_S,$04,$22,$19,v25.s,89,89
+V25_D,$04,$23,$19,v25.d,89,89
+V25_8B,$04,$18,$19,v25.8b,89,89
+V25_16B,$04,$19,$19,v25.16b,89,89
+V25_4H,$04,$1a,$19,v25.4h,89,89
+V25_8H,$04,$1b,$19,v25.8h,89,89
+V25_2S,$04,$1c,$19,v25.2s,89,89
+V25_4S,$04,$1d,$19,v25.4s,89,89
+V25_1D,$04,$1e,$19,v25.1d,89,89
+V25_2D,$04,$1f,$19,v25.2d,89,89
 B26,$04,$01,$1A,b26,90,90
 H26,$04,$03,$1A,h26,90,90
 S26,$04,$09,$1A,s26,90,90
 D26,$04,$0a,$1A,d26,90,90
-Q26,$04,$05,$1A,q26,90,90
-V268B,$04,$17,$1A,v26.8b,90,90
-V2616B,$04,$18,$1A,v26.16b,90,90
+Q26,$04,$0b,$1A,q26,90,90
+V26,$04,$00,$1A,v26,90,90
+V26_B,$04,$20,$1A,v26.b,90,90
+V26_H,$04,$21,$1A,v26.h,90,90
+V26_S,$04,$22,$1A,v26.s,90,90
+V26_D,$04,$23,$1A,v26.d,90,90
+V26_8B,$04,$18,$1A,v26.8b,90,90
+V26_16B,$04,$19,$1A,v26.16b,90,90
+V26_4H,$04,$1a,$1A,v26.4h,90,90
+V26_8H,$04,$1b,$1A,v26.8h,90,90
+V26_2S,$04,$1c,$1A,v26.2s,90,90
+V26_4S,$04,$1d,$1A,v26.4s,90,90
+V26_1D,$04,$1e,$1A,v26.1d,90,90
+V26_2D,$04,$1f,$1A,v26.2d,90,90
 B27,$04,$01,$1B,b27,91,91
 H27,$04,$03,$1B,h27,91,91
 S27,$04,$09,$1B,s27,91,91
 D27,$04,$0a,$1B,d27,91,91
-Q27,$04,$05,$1B,q27,91,91
-V278B,$04,$17,$1B,v27.8b,91,91
-V2716B,$04,$18,$1B,v27.16b,91,91
+Q27,$04,$0b,$1B,q27,91,91
+V27,$04,$00,$1B,v27,91,91
+V27_B,$04,$20,$1B,v27.b,91,91
+V27_H,$04,$21,$1B,v27.h,91,91
+V27_S,$04,$22,$1B,v27.s,91,91
+V27_D,$04,$23,$1B,v27.d,91,91
+V27_8B,$04,$18,$1B,v27.8b,91,91
+V27_16B,$04,$19,$1B,v27.16b,91,91
+V27_4H,$04,$1a,$1B,v27.4h,91,91
+V27_8H,$04,$1b,$1B,v27.8h,91,91
+V27_2S,$04,$1c,$1B,v27.2s,91,91
+V27_4S,$04,$1d,$1B,v27.4s,91,91
+V27_1D,$04,$1e,$1B,v27.1d,91,91
+V27_2D,$04,$1f,$1B,v27.2d,91,91
 B28,$04,$01,$1C,b28,92,92
 H28,$04,$03,$1C,h28,92,92
 S28,$04,$09,$1C,s28,92,92
 D28,$04,$0a,$1C,d28,92,92
-Q28,$04,$05,$1C,q28,92,92
-V288B,$04,$17,$1C,v28.8b,92,92
-V2816B,$04,$18,$1C,v28.16b,92,92
+Q28,$04,$0b,$1C,q28,92,92
+V28,$04,$00,$1C,v28,92,92
+V28_B,$04,$20,$1C,v28.b,92,92
+V28_H,$04,$21,$1C,v28.h,92,92
+V28_S,$04,$22,$1C,v28.s,92,92
+V28_D,$04,$23,$1C,v28.d,92,92
+V28_8B,$04,$18,$1C,v28.8b,92,92
+V28_16B,$04,$19,$1C,v28.16b,92,92
+V28_4H,$04,$1a,$1C,v28.4h,92,92
+V28_8H,$04,$1b,$1C,v28.8h,92,92
+V28_2S,$04,$1c,$1C,v28.2s,92,92
+V28_4S,$04,$1d,$1C,v28.4s,92,92
+V28_1D,$04,$1e,$1C,v28.1d,92,92
+V28_2D,$04,$1f,$1C,v28.2d,92,92
 B29,$04,$01,$1D,b29,93,93
 H29,$04,$03,$1D,h29,93,93
 S29,$04,$09,$1D,s29,93,93
 D29,$04,$0a,$1D,d29,93,93
-Q29,$04,$05,$1D,q29,93,93
-V298B,$04,$17,$1D,v29.8b,93,93
-V2916B,$04,$18,$1D,v29.16b,93,93
+Q29,$04,$0b,$1D,q29,93,93
+V29,$04,$00,$1D,v29,93,93
+V29_B,$04,$20,$1D,v29.b,93,93
+V29_H,$04,$21,$1D,v29.h,93,93
+V29_S,$04,$22,$1D,v29.s,93,93
+V29_D,$04,$23,$1D,v29.d,93,93
+V29_8B,$04,$18,$1D,v29.8b,93,93
+V29_16B,$04,$19,$1D,v29.16b,93,93
+V29_4H,$04,$1a,$1D,v29.4h,93,93
+V29_8H,$04,$1b,$1D,v29.8h,93,93
+V29_2S,$04,$1c,$1D,v29.2s,93,93
+V29_4S,$04,$1d,$1D,v29.4s,93,93
+V29_1D,$04,$1e,$1D,v29.1d,93,93
+V29_2D,$04,$1f,$1D,v29.2d,93,93
 B30,$04,$01,$1E,b30,94,94
 H30,$04,$03,$1E,h30,94,94
 S30,$04,$09,$1E,s30,94,94
 D30,$04,$0a,$1E,d30,94,94
-Q30,$04,$05,$1E,q30,94,94
-V308B,$04,$17,$1E,v30.8b,94,94
-V3016B,$04,$18,$1E,v30.16b,94,94
+Q30,$04,$0b,$1E,q30,94,94
+V30,$04,$00,$1E,v30,94,94
+V30_B,$04,$20,$1E,v30.b,94,94
+V30_H,$04,$21,$1E,v30.h,94,94
+V30_S,$04,$22,$1E,v30.s,94,94
+V30_D,$04,$23,$1E,v30.d,94,94
+V30_8B,$04,$18,$1E,v30.8b,94,94
+V30_16B,$04,$19,$1E,v30.16b,94,94
+V30_4H,$04,$1a,$1E,v30.4h,94,94
+V30_8H,$04,$1b,$1E,v30.8h,94,94
+V30_2S,$04,$1c,$1E,v30.2s,94,94
+V30_4S,$04,$1d,$1E,v30.4s,94,94
+V30_1D,$04,$1e,$1E,v30.1d,94,94
+V30_2D,$04,$1f,$1E,v30.2d,94,94
 B31,$04,$01,$1F,b31,95,95
 H31,$04,$03,$1F,h31,95,95
 S31,$04,$09,$1F,s31,95,95
 D31,$04,$0a,$1F,d31,95,95
-Q31,$04,$05,$1F,q31,95,95
-V318B,$04,$17,$1F,v31.8b,95,95
-V3116B,$04,$18,$1F,v31.16b,95,95
-
-NZCV,$05,$00,$00,nzcv,0,0
-FPCR,$05,$00,$01,fpcr,0,0
-FPSR,$05,$00,$02,fpsr,0,0
-TPIDR_EL0,$05,$00,$03,tpidr_el0,0,0
-
+Q31,$04,$0b,$1F,q31,95,95
+V31,$04,$00,$1F,v31,95,95
+V31_B,$04,$20,$1F,v31.b,95,95
+V31_H,$04,$21,$1F,v31.h,95,95
+V31_S,$04,$22,$1F,v31.s,95,95
+V31_D,$04,$23,$1F,v31.d,95,95
+V31_8B,$04,$18,$1F,v31.8b,95,95
+V31_16B,$04,$19,$1F,v31.16b,95,95
+V31_4H,$04,$1a,$1F,v31.4h,95,95
+V31_8H,$04,$1b,$1F,v31.8h,95,95
+V31_2S,$04,$1c,$1F,v31.2s,95,95
+V31_4S,$04,$1d,$1F,v31.4s,95,95
+V31_1D,$04,$1e,$1F,v31.1d,95,95
+V31_2D,$04,$1f,$1F,v31.2d,95,95

compiler/aarch64/aasmcpu.pas

@@ -158,6 +158,8 @@ uses
          procedure loadshifterop(opidx:longint;const so:tshifterop);
          procedure loadconditioncode(opidx: longint; const c: tasmcond);
          procedure loadrealconst(opidx: longint; const _value: bestreal);
+         procedure loadregset(opidx: longint; _basereg: tregister; _nregs: byte; _regsetindex: byte = 255);
+         procedure loadindexedreg(opidx: longint; _indexedreg: tregister; _regindex: byte);
 
          constructor op_none(op : tasmop);
 
@@ -172,6 +174,9 @@ uses
          constructor op_reg_const_shifterop(op : tasmop;_op1: tregister; _op2: aint;_op3 : tshifterop);
          constructor op_reg_realconst(op: tasmop; _op1: tregister; _op2: bestreal);
 
+         constructor op_indexedreg_reg(op : tasmop;_op1: tregister; _op1index: byte; _op2 : tregister);
+         constructor op_reg_indexedreg(op : tasmop;_op1: tregister; _op2 : tregister; _op2index: byte);
+
          constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
          constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
          constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
@@ -183,9 +188,14 @@ uses
          constructor op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister; const _op4 : tshifterop);
          constructor op_reg_reg_reg_cond(op : tasmop;_op1,_op2,_op3 : tregister; const _op4: tasmcond);
 
+         constructor op_const_ref(op:tasmop; _op1: aint; _op2: treference);
+
          { this is for Jmp instructions }
          constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
 
+         { ldN(r)/stN }
+         constructor op_regset_reg_ref(op: tasmop; basereg: tregister; nregs: byte; const ref: treference);
+
          constructor op_sym(op : tasmop;_op1 : tasmsymbol);
          constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
          constructor op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
@@ -295,6 +305,35 @@ implementation
       end;
 
 
+    procedure taicpu.loadregset(opidx: longint; _basereg: tregister; _nregs: byte; _regsetindex: byte = 255);
+      begin
+        allocate_oper(opidx+1);
+        with oper[opidx]^ do
+          begin
+            if typ<>top_regset then
+              clearop(opidx);
+            basereg:=_basereg;
+            nregs:=_nregs;
+            regsetindex:=_regsetindex;
+            typ:=top_regset;
+          end;
+      end;
+
+
+    procedure taicpu.loadindexedreg(opidx: longint; _indexedreg: tregister; _regindex: byte);
+      begin
+        allocate_oper(opidx+1);
+        with oper[opidx]^ do
+          begin
+            if typ<>top_indexedreg then
+              clearop(opidx);
+            indexedreg:=_indexedreg;
+            regindex:=_regindex;
+            typ:=top_indexedreg;
+          end;
+      end;
+
+
 {*****************************************************************************
                                  taicpu Constructors
 *****************************************************************************}
@@ -406,6 +445,24 @@ implementation
       end;
 
 
+    constructor taicpu.op_indexedreg_reg(op: tasmop; _op1: tregister; _op1index: byte; _op2: tregister);
+      begin
+        inherited create(op);
+        ops:=2;
+        loadindexedreg(0,_op1,_op1index);
+        loadreg(1,_op2);
+      end;
+
+
+    constructor taicpu.op_reg_indexedreg(op: tasmop; _op1: tregister; _op2: tregister; _op2index: byte);
+      begin
+        inherited create(op);
+        ops:=2;
+        loadreg(0,_op1);
+        loadindexedreg(1,_op2,_op2index);
+      end;
+
+
      constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
        begin
          inherited create(op);
@@ -489,6 +546,15 @@ implementation
        end;
 
 
+     constructor taicpu.op_const_ref(op : tasmop; _op1 : aint; _op2 : treference);
+      begin
+         inherited create(op);
+         ops:=2;
+         loadconst(0,_op1);
+         loadref(1,_op2);
+      end;
+
+
     constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
       begin
          inherited create(op);
@@ -498,6 +564,15 @@ implementation
       end;
 
 
+    constructor taicpu.op_regset_reg_ref(op: tasmop; basereg: tregister; nregs: byte; const ref: treference);
+      begin
+        inherited create(op);
+        ops:=2;
+        loadregset(0,basereg,nregs);
+        loadref(1, ref);
+      end;
+
+
     constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
       begin
          inherited create(op);
@@ -552,7 +627,7 @@ implementation
       const
         { invalid sizes for aarch64 are 0 }
         subreg2bytesize: array[TSubRegister] of byte =
-          (0,0,0,0,4,8,0,0,0,4,8,0,0,0,0,0,0,0,0,0,0,0,0,8,16,0);
+          (0,0,0,0,4,8,0,0,0,4,8,0,0,0,0,0,0,0,0,0,0,0,0,8,16,0,16,16,16,16,16,16,16,16,16,16);
       var
         scalefactor: byte;
       begin
@@ -569,7 +644,7 @@ implementation
           R_MMREGISTER:
             result:=taicpu.op_reg_ref(op,r,ref);
           else
-            internalerror(200401041);
+            internalerror(2004010407);
         end;
       end;
 
@@ -639,7 +714,9 @@ implementation
         result:=sr_internal_illegal;
         { post-indexed is only allowed for vector and immediate loads/stores }
         if (ref.addressmode=AM_POSTINDEXED) and
-           not(op in [A_LD1,A_LD2,A_LD3,A_LD4,A_ST1,A_ST2,A_ST3,A_ST4]) and
+           not((op = A_LD1) or (op = A_LD2) or (op = A_LD3) or (op = A_LD4) or
+               (op = A_LD1R) or (op = A_LD2R) or (op = A_LD3R) or (op = A_LD4R) or
+               (op = A_ST1) or (op = A_ST2) or (op = A_ST3) or (op = A_ST4)) and
            (not(op in [A_LDR,A_STR,A_LDP,A_STP]) or
             (ref.base=NR_NO) or
             (ref.index<>NR_NO)) then
@@ -682,32 +759,46 @@ implementation
             * can scale with the size of the access
             * can zero/sign extend 32 bit index register, and/or multiple by
               access size
-            * no pre/post-indexing
+            * no pre/post-indexing except for ldN(r)/stN
         }
         if (ref.base<>NR_NO) and
            (ref.index<>NR_NO) then
           begin
-            if ref.addressmode in [AM_PREINDEXED,AM_POSTINDEXED] then
-              exit;
             case op of
               { this holds for both integer and fpu/vector loads }
               A_LDR,A_STR:
-                if (ref.offset=0) and
-                   (((ref.shiftmode=SM_None) and
-                     (ref.shiftimm=0)) or
-                    ((ref.shiftmode in [SM_LSL,SM_UXTW,SM_SXTW]) and
-                     (ref.shiftimm=tcgsizep2size[size]))) then
-                  result:=sr_simple
-                else
-                  result:=sr_complex;
-              { todo }
+                begin
+                  if ref.addressmode in [AM_PREINDEXED,AM_POSTINDEXED] then
+                    exit;
+                  if (ref.offset=0) and
+                     (((ref.shiftmode=SM_None) and
+                       (ref.shiftimm=0)) or
+                      ((ref.shiftmode in [SM_LSL,SM_UXTW,SM_SXTW]) and
+                       (ref.shiftimm=tcgsizep2size[size]))) then
+                    result:=sr_simple
+                  else
+                    result:=sr_complex;
+                end;
               A_LD1,A_LD2,A_LD3,A_LD4,
+              A_LD1R,A_LD2R,A_LD3R,A_LD4R,
               A_ST1,A_ST2,A_ST3,A_ST4:
-                internalerror(2014110704);
+                begin
+                  if ref.addressmode in [AM_PREINDEXED] then
+                    exit;
+                  if (ref.offset=0) and
+                     (ref.addressmode=AM_POSTINDEXED) then
+                    result:=sr_simple
+                  else
+                   result:=sr_complex;
+                end;
               { these don't support base+index }
               A_LDUR,A_STUR,
               A_LDP,A_STP:
-                result:=sr_complex;
+                begin
+                  if ref.addressmode in [AM_PREINDEXED,AM_POSTINDEXED] then
+                    exit;
+                  result:=sr_complex;
+                end
               else
                 { nothing: result is already sr_internal_illegal };
             end;
@@ -724,6 +815,8 @@ implementation
               - regular with signed 9 bit immediate
             * LDUR*/STUR*:
               - regular with signed 9 bit immediate
+            * ldN(r)/stN
+              - 0 or with postindex
         }
         if ref.base<>NR_NO then
           begin
@@ -767,17 +860,28 @@ implementation
                 end;
               A_LDUR,A_STUR:
                 begin
-                  if (ref.addressmode=AM_OFFSET) and
-                     (ref.offset>=-256) and
+                  if ref.addressmode in [AM_PREINDEXED,AM_POSTINDEXED] then
+                    exit;
+                  if (ref.offset>=-256) and
                      (ref.offset<=255) then
                     result:=sr_simple
                   else
                     result:=sr_complex;
                 end;
-              { todo }
               A_LD1,A_LD2,A_LD3,A_LD4,
+              A_LD1R,A_LD2R,A_LD3R,A_LD4R,
               A_ST1,A_ST2,A_ST3,A_ST4:
-                internalerror(2014110907);
+                begin
+                  if ref.addressmode in [AM_PREINDEXED] then
+                    exit;
+                  if (ref.offset=0) or
+                     ((ref.addressmode=AM_POSTINDEXED) and
+                      { to check the validity of the offset, we'd have to analyse the regset argument }
+                      (ref.offset>0)) then
+                    result:=sr_simple
+                  else
+                    result:=sr_complex;
+                end;
               A_LDAR,
               A_LDAXR,
               A_LDXR,

compiler/aarch64/agcpugas.pas

@@ -229,7 +229,7 @@ unit agcpugas;
                   begin
                     check_offset(seh.data.offset,512);
                     check_reg(seh.data.reg,R_MMREGISTER,min_mm_reg);
-                    writeword($DA00 or ((getsupreg(seh.data.reg)-min_int_reg) shl 6) or ((seh.data.offset shr 3)-1));
+                    writeword($DA00 or ((getsupreg(seh.data.reg)-min_mm_reg) shl 6) or ((seh.data.offset shr 3)-1));
                   end;
                 else
                   internalerror(2020041503);
@@ -305,7 +305,11 @@ unit agcpugas;
                         internalerror(2020041214);
                     end
                   else
-                    lastsec:=tai_section(hp);
+                    begin
+                      lastsec:=tai_section(hp);
+                      { also reset the last encountered symbol }
+                      lastsym:=nil;
+                    end;
 
                   if assigned(tmplist) then
                     begin
@@ -313,10 +317,11 @@ unit agcpugas;
                       tmplist.free;
                       tmplist:=nil;
                     end;
+
                 end;
               ait_symbol:
                 begin
-                  if tai_symbol(hp).is_global then
+                  if tai_symbol(hp).sym.typ=AT_FUNCTION then
                     lastsym:=tai_symbol(hp);
                 end;
               ait_instruction:
@@ -365,7 +370,7 @@ unit agcpugas;
                         { note: we can pass Nil here, because in case of a LLVM
                                 backend this whole code shouldn't be required
                                 anyway }
-                        xdatasym:=current_asmdata.DefineAsmSymbol('xdata_'+lastsec.name^,AB_LOCAL,AT_DATA,nil);
+                        xdatasym:=current_asmdata.DefineAsmSymbol('xdata_'+lastsym.sym.name,AB_LOCAL,AT_DATA,nil);
 
                         tmplist:=tasmlist.create;
                         new_section(tmplist,sec_pdata,lastsec.name^,0);
@@ -408,7 +413,7 @@ unit agcpugas;
                           unwindrec:=unwindrec or ((unwinddata.size div 4) shl 27);
 
                         { exception record headers }
-                        tmplist.concat(tai_const.Create_32bit(unwindrec));
+                        tmplist.concat(tai_const.Create_32bit(longint(unwindrec)));
                         if cs_asm_source in init_settings.globalswitches then
                           tmplist.concat(tai_comment.create(strpnew(hexstr(unwindrec,8))));
 
@@ -419,7 +424,7 @@ unit agcpugas;
                             if unwinddata.size div 4>255 then
                               comment(V_Error,'Too many unwind codes for SEH');
                             unwindrec:=(unwinddata.size div 4) shl 16;
-                            tmplist.concat(tai_const.create_32bit(unwindrec));
+                            tmplist.concat(tai_const.create_32bit(longint(unwindrec)));
                             if cs_asm_source in init_settings.globalswitches then
                               tmplist.concat(tai_comment.create(strpnew(hexstr(unwindrec,8))));
                           end;
@@ -429,7 +434,7 @@ unit agcpugas;
                         while unwinddata.pos<unwinddata.size do
                           begin
                             unwinddata.read(unwindrec,sizeof(longword));
-                            tmplist.concat(tai_const.Create_32bit(unwindrec));
+                            tmplist.concat(tai_const.Create_32bit(longint(unwindrec)));
                             if cs_asm_source in init_settings.globalswitches then
                               tmplist.concat(tai_comment.create(strpnew(hexstr(unwindrec,8))));
                           end;
@@ -650,7 +655,7 @@ unit agcpugas;
                 else
                   begin
                     if ref.refaddr<>addr_no then
-                      internalerror(2014121506);
+                      internalerror(2014121502);
                     if (ref.offset<>0) then
                       result:=result+', #'+tostr(ref.offset);
                   end;
@@ -668,26 +673,13 @@ unit agcpugas;
 
 
     function getopstr(asminfo: pasminfo; hp: taicpu; opnr: longint; const o: toper): string;
+      var
+        i: longint;
+        reg: tregister;
       begin
         case o.typ of
           top_reg:
-            { we cannot yet represent "umov w0, v4.s[0]" or "ins v4.d[0], x1",
-              so for now we use "s4" or "d4" instead -> translate here }
-            if ((hp.opcode=A_INS) or
-                (hp.opcode=A_UMOV)) and
-               (getregtype(hp.oper[opnr]^.reg)=R_MMREGISTER) then
-              begin
-                case getsubreg(hp.oper[opnr]^.reg) of
-                  R_SUBMMS:
-                    getopstr:='v'+tostr(getsupreg(hp.oper[opnr]^.reg))+'.S[0]';
-                  R_SUBMMD:
-                    getopstr:='v'+tostr(getsupreg(hp.oper[opnr]^.reg))+'.D[0]';
-                  else
-                    internalerror(2014122907);
-                end;
-              end
-            else
-              getopstr:=gas_regname(o.reg);
+            getopstr:=gas_regname(o.reg);
           top_shifterop:
             begin
               getopstr:=gas_shiftmode2str[o.shifterop^.shiftmode];
@@ -720,7 +712,24 @@ unit agcpugas;
             begin
               str(o.val_real,Result);
               Result:='#'+Result;
-            end
+            end;
+          top_regset:
+            begin
+              reg:=o.basereg;
+              result:='{'+gas_regname(reg);
+              for i:=1 to o.nregs-1 do
+                begin
+                  setsupreg(reg,succ(getsupreg(reg)) mod 32);
+                  result:=result+', '+gas_regname(reg);
+                end;
+              result:=result+'}';
+              if o.regsetindex<>255 then
+                result:=result+'['+tostr(o.regsetindex)+']'
+            end;
+          top_indexedreg:
+            begin
+              result:=gas_regname(o.indexedreg)+'['+tostr(o.regindex)+']';
+            end;
           else
             internalerror(2014121507);
         end;

compiler/aarch64/aoptcpu.pas

@@ -85,11 +85,11 @@ Implementation
     var
       p: taicpu;
     begin
-      p := taicpu(hp);
       Result := false;
       if not ((assigned(hp)) and (hp.typ = ait_instruction)) then
         exit;
 
+      p := taicpu(hp);
       case p.opcode of
         { These operands do not write into a register at all }
         A_CMP, A_CMN, A_TST, A_B, A_BL, A_MSR, A_FCMP:
@@ -538,6 +538,27 @@ Implementation
           DebugMsg(SPeepholeOptimization + 'FMovFMov2FMov done', p);
           Result:=true;
         end;
+      { not enabled as apparently not happening
+      if MatchOpType(taicpu(p),top_reg,top_reg) and
+        GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
+        MatchInstruction(hp1, [A_FSUB,A_FADD,A_FNEG,A_FMUL,A_FSQRT,A_FDIV,A_FABS], [PF_None]) and
+        (MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^) or
+         ((taicpu(hp1).ops=3) and MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[2]^))
+        ) and
+        RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
+        not(RegUsedBetween(taicpu(p).oper[0]^.reg,p,hp1)) then
+        begin
+          DebugMsg(SPeepholeOptimization + 'FMovFOp2FOp done', hp1);
+          AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,UsedRegs);
+          if MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^) then
+            taicpu(hp1).oper[1]^.reg:=taicpu(p).oper[1]^.reg;
+          if (taicpu(hp1).ops=3) and MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[2]^) then
+            taicpu(hp1).oper[2]^.reg:=taicpu(p).oper[1]^.reg;
+          RemoveCurrentP(p);
+          Result:=true;
+          exit;
+        end;
+      }
     end;
 
 
@@ -772,6 +793,11 @@ Implementation
             A_SXTH:
               Result:=OptPass1SXTH(p);
 //            A_VLDR,
+            A_FMADD,
+            A_FMSUB,
+            A_FNMADD,
+            A_FNMSUB,
+            A_FNMUL,
             A_FADD,
             A_FMUL,
             A_FDIV,

compiler/aarch64/cgcpu.pas

@@ -274,7 +274,7 @@ implementation
               { todo }
               A_LD1,A_LD2,A_LD3,A_LD4,
               A_ST1,A_ST2,A_ST3,A_ST4:
-                internalerror(2014110704);
+                internalerror(2014110702);
               { these don't support base+index }
               A_LDUR,A_STUR,
               A_LDP,A_STP:
@@ -301,7 +301,7 @@ implementation
                     offset may still be too big }
                 end;
               else
-                internalerror(2014110901);
+                internalerror(2014110903);
             end;
           end;
 
@@ -1162,10 +1162,17 @@ implementation
        begin
          if not shufflescalar(shuffle) then
            internalerror(2014122801);
-         if not(tcgsize2size[fromsize] in [4,8]) or
-            (tcgsize2size[fromsize]<>tcgsize2size[tosize]) then
+         if tcgsize2size[fromsize]<>tcgsize2size[tosize] then
            internalerror(2014122803);
-         list.concat(taicpu.op_reg_reg(A_INS,mmreg,intreg));
+         case tcgsize2size[tosize] of
+           4:
+             setsubreg(mmreg,R_SUBMMS);
+           8:
+             setsubreg(mmreg,R_SUBMMD);
+           else
+             internalerror(2020101310);
+         end;
+         list.concat(taicpu.op_indexedreg_reg(A_INS,mmreg,0,intreg));
        end;
 
 
@@ -1175,14 +1182,21 @@ implementation
        begin
          if not shufflescalar(shuffle) then
            internalerror(2014122802);
-         if not(tcgsize2size[fromsize] in [4,8]) or
-            (tcgsize2size[fromsize]>tcgsize2size[tosize]) then
+         if tcgsize2size[fromsize]>tcgsize2size[tosize] then
            internalerror(2014122804);
+         case tcgsize2size[fromsize] of
+           4:
+             setsubreg(mmreg,R_SUBMMS);
+           8:
+             setsubreg(mmreg,R_SUBMMD);
+           else
+             internalerror(2020101311);
+           end;
          if tcgsize2size[fromsize]<tcgsize2size[tosize] then
            r:=makeregsize(intreg,fromsize)
          else
            r:=intreg;
-         list.concat(taicpu.op_reg_reg(A_UMOV,r,mmreg));
+         list.concat(taicpu.op_reg_indexedreg(A_UMOV,r,mmreg,0));
        end;
 
 

compiler/aarch64/cpubase.pas

@@ -48,10 +48,6 @@ unit cpubase;
     type
       TAsmOp= {$i a64op.inc}
 
-      TAsmOps = set of TAsmOp;
-      { AArch64 has less than 256 opcodes so far }
-      TCommonAsmOps = Set of TAsmOp;
-
       { This should define the array of instructions as string }
       op2strtable=array[tasmop] of string[11];
 
@@ -60,6 +56,13 @@ unit cpubase;
       firstop = low(tasmop);
       { Last value of opcode enumeration  }
       lastop  = high(tasmop);
+      { Last value of opcode for TCommonAsmOps set below  }
+      LastCommonAsmOp = A_MOV;
+
+    type
+      { See comment for this type in arm/cpubase.pas }
+      TCommonAsmOps = Set of A_None .. LastCommonAsmOp;
+
 
 {*****************************************************************************
                                   Registers
@@ -75,6 +78,7 @@ unit cpubase;
 
       RS_IP0 = RS_X16;
       RS_IP1 = RS_X17;
+      RS_XR = RS_X8;
 
       R_SUBWHOLE = R_SUBQ;
 
@@ -83,6 +87,7 @@ unit cpubase;
 
       NR_IP0 = NR_X16;
       NR_IP1 = NR_X17;
+      NR_XR = NR_X8;
 
       { Integer Super registers first and last }
       first_int_supreg = RS_X0;
@@ -108,7 +113,7 @@ unit cpubase;
       std_param_align = 8;
 
       { TODO: Calculate bsstart}
-      regnumber_count_bsstart = 256;
+      regnumber_count_bsstart = 512;
 
       regnumber_table : array[tregisterindex] of tregister = (
         {$i ra64num.inc}
@@ -406,6 +411,23 @@ unit cpubase;
                   result:=OS_F64;
                 R_SUBMMS:
                   result:=OS_F32;
+                { always use OS_M128, because these could be the top or bottom bytes (or middle in some cases) }
+                R_SUBMM8B:
+                  result:=OS_M128;
+                R_SUBMM16B:
+                  result:=OS_M128;
+                R_SUBMM4H:
+                  result:=OS_M128;
+                R_SUBMM8H:
+                  result:=OS_M128;
+                R_SUBMM2S:
+                  result:=OS_M128;
+                R_SUBMM4S:
+                  result:=OS_M128;
+                R_SUBMM1D:
+                  result:=OS_M128;
+                R_SUBMM2D:
+                  result:=OS_M128;
                 R_SUBMMWHOLE:
                   result:=OS_M128;
                 else

compiler/aarch64/cpupara.pas

@@ -266,7 +266,7 @@ unit cpupara;
                     size:=OS_ADDR;
                     def:=hp.paraloc[side].def;
                     loc:=LOC_REGISTER;
-                    register:=NR_X8;
+                    register:=NR_XR;
                   end
               end
             else
@@ -349,7 +349,7 @@ unit cpupara;
         paracgsize, locsize: tcgsize;
         firstparaloc: boolean;
       begin
-        result.reset;
+        result.init;
 
         { currently only support C-style array of const,
           there should be no location assigned to the vararg array itself }
@@ -682,7 +682,7 @@ unit cpupara;
             result:=curstackoffset;
           end
         else
-          internalerror(200410231);
+          internalerror(2004102303);
 
         create_funcretloc_info(p,side);
       end;

compiler/aarch64/hlcgcpu.pas

@@ -184,7 +184,7 @@ implementation
           not is_objectpascal_helper(procdef.struct) then
         begin
           if (procdef.extnumber=$ffff) then
-            Internalerror(200006139);
+            Internalerror(2000061302);
           { mov  0(%rdi),%rax ; load vmt}
           reference_reset_base(href,voidpointertype,paraloc^.register,0,ctempposinvalid,sizeof(pint),[]);
           getcpuregister(list,NR_IP0);

compiler/aarch64/ncpuflw.pas

@@ -355,7 +355,7 @@ function taarch64tryfinallynode.dogetcopy: tnode;
     if (target_info.system=system_aarch64_win64) then
       begin
         if df_generic in current_procinfo.procdef.defoptions then
-          InternalError(2020033101);
+          InternalError(2020033104);
 
         p.finalizepi:=tcgprocinfo(current_procinfo.create_for_outlining('$fin$',current_procinfo.procdef.struct,potype_exceptfilter,voidtype,p.right));
         if pi_do_call in finalizepi.flags then

compiler/aarch64/ncpuinl.pas

@@ -44,6 +44,7 @@ interface
         procedure second_trunc_real; override;
         procedure second_get_frame; override;
         procedure second_fma; override;
+        procedure second_prefetch; override;
       private
         procedure load_fpu_location;
       end;
@@ -55,7 +56,7 @@ implementation
       globtype,verbose,globals,
       cpuinfo, defutil,symdef,aasmdata,aasmcpu,
       cgbase,cgutils,pass_1,pass_2,
-      ncal,
+      ncal,nutils,
       cpubase,ncgutil,cgobj,cgcpu, hlcgobj;
 
 {*****************************************************************************
@@ -272,6 +273,34 @@ implementation
       end;
 
 
+    procedure taarch64inlinenode.second_prefetch;
+      var
+        ref : treference;
+        r : tregister;
+        checkpointer_used : boolean;
+      begin
+        { do not call Checkpointer for left node }
+        checkpointer_used:=(cs_checkpointer in current_settings.localswitches);
+        if checkpointer_used then
+          node_change_local_switch(left,cs_checkpointer,false);
+        secondpass(left);
+        if checkpointer_used then
+          node_change_local_switch(left,cs_checkpointer,false);
+       case left.location.loc of
+         LOC_CREFERENCE,
+         LOC_REFERENCE:
+           begin
+             r:=cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
+             cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,left.location.reference,r);
+             reference_reset_base(ref,r,0,location.reference.temppos,left.location.reference.alignment,location.reference.volatility);
+             current_asmdata.CurrAsmList.concat(taicpu.op_const_ref(A_PRFM,0,ref));
+           end;
+         else
+           { nothing to prefetch };
+       end;
+      end;
+
+
 begin
   cinlinenode:=taarch64inlinenode;
 end.

compiler/aarch64/ncpumat.pas

@@ -82,11 +82,13 @@ implementation
          var
            helper1, helper2: TRegister;
            so: tshifterop;
+           opsize: TCgSize;
          begin
+           opsize:=def_cgsize(resultdef);
            if tordconstnode(right).value=0 then
              internalerror(2020021601)
            else if tordconstnode(right).value=1 then
-             cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, numerator, resultreg)
+             cg.a_load_reg_reg(current_asmdata.CurrAsmList, opsize, opsize, numerator, resultreg)
            else if (tordconstnode(right).value = int64(-1)) then
              begin
                // note: only in the signed case possible..., may overflow
@@ -100,26 +102,26 @@ implementation
              begin
                if (is_signed(right.resultdef)) then
                  begin
-                    helper2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
+                    helper2:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
                     if power = 1 then
                       helper1:=numerator
                     else
                       begin
-                        helper1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
-                        cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,63,numerator,helper1);
+                        helper1:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                        cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,opsize,resultdef.size*8-1,numerator,helper1);
                       end;
                     shifterop_reset(so);
                     so.shiftmode:=SM_LSR;
-                    so.shiftimm:=64-power;
+                    so.shiftimm:=resultdef.size*8-power;
                     current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,helper2,numerator,helper1,so));
-                    cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,power,helper2,resultreg);
+                    cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,def_cgsize(resultdef),power,helper2,resultreg);
                   end
                else
-                 cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_INT,power,numerator,resultreg)
+                 cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,opsize,power,numerator,resultreg)
              end
            else
              { Everything else is handled in the generic code }
-             cg.g_div_const_reg_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),
+             cg.g_div_const_reg_reg(current_asmdata.CurrAsmList,opsize,
                tordconstnode(right).value.svalue,numerator,resultreg);
          end;
 

compiler/aarch64/ra64con.inc

@@ -66,231 +66,583 @@ NR_WZR = tregister($0104001F);
 NR_XZR = tregister($0105001F);
 NR_WSP = tregister($01040020);
 NR_SP = tregister($01050020);
+NR_NZCV = tregister($05000000);
+NR_FPCR = tregister($05000001);
+NR_FPSR = tregister($05000002);
+NR_TPIDR_EL0 = tregister($05000003);
 NR_B0 = tregister($04010000);
 NR_H0 = tregister($04030000);
 NR_S0 = tregister($04090000);
 NR_D0 = tregister($040a0000);
-NR_Q0 = tregister($04050000);
-NR_V08B = tregister($04170000);
-NR_V016B = tregister($04180000);
+NR_Q0 = tregister($040b0000);
+NR_V0 = tregister($04000000);
+NR_V0_B = tregister($04200000);
+NR_V0_H = tregister($04210000);
+NR_V0_S = tregister($04220000);
+NR_V0_D = tregister($04230000);
+NR_V0_8B = tregister($04180000);
+NR_V0_16B = tregister($04190000);
+NR_V0_4H = tregister($041a0000);
+NR_V0_8H = tregister($041b0000);
+NR_V0_2S = tregister($041c0000);
+NR_V0_4S = tregister($041d0000);
+NR_V0_1D = tregister($041e0000);
+NR_V0_2D = tregister($041f0000);
 NR_B1 = tregister($04010001);
 NR_H1 = tregister($04030001);
 NR_S1 = tregister($04090001);
 NR_D1 = tregister($040a0001);
-NR_Q1 = tregister($04050001);
-NR_V18B = tregister($04170001);
-NR_V116B = tregister($04180001);
+NR_Q1 = tregister($040b0001);
+NR_V1 = tregister($04000001);
+NR_V1_B = tregister($04200001);
+NR_V1_H = tregister($04210001);
+NR_V1_S = tregister($04220001);
+NR_V1_D = tregister($04230001);
+NR_V1_8B = tregister($04180001);
+NR_V1_16B = tregister($04190001);
+NR_V1_4H = tregister($041a0001);
+NR_V1_8H = tregister($041b0001);
+NR_V1_2S = tregister($041c0001);
+NR_V1_4S = tregister($041d0001);
+NR_V1_1D = tregister($041e0001);
+NR_V1_2D = tregister($041f0001);
 NR_B2 = tregister($04010002);
 NR_H2 = tregister($04030002);
 NR_S2 = tregister($04090002);
 NR_D2 = tregister($040a0002);
-NR_Q2 = tregister($04050002);
-NR_V28B = tregister($04170002);
-NR_V216B = tregister($04180002);
+NR_Q2 = tregister($040b0002);
+NR_V2 = tregister($04000002);
+NR_V2_B = tregister($04200002);
+NR_V2_H = tregister($04210002);
+NR_V2_S = tregister($04220002);
+NR_V2_D = tregister($04230002);
+NR_V2_8B = tregister($04180002);
+NR_V2_16B = tregister($04190002);
+NR_V2_4H = tregister($041a0002);
+NR_V2_8H = tregister($041b0002);
+NR_V2_2S = tregister($041c0002);
+NR_V2_4S = tregister($041d0002);
+NR_V2_1D = tregister($041e0002);
+NR_V2_2D = tregister($041f0002);
 NR_B3 = tregister($04010003);
 NR_H3 = tregister($04030003);
 NR_S3 = tregister($04090003);
 NR_D3 = tregister($040a0003);
-NR_Q3 = tregister($04050003);
-NR_V38B = tregister($04170003);
-NR_V316B = tregister($04180003);
+NR_Q3 = tregister($040b0003);
+NR_V3 = tregister($04000003);
+NR_V3_B = tregister($04200003);
+NR_V3_H = tregister($04210003);
+NR_V3_S = tregister($04220003);
+NR_V3_D = tregister($04230003);
+NR_V3_8B = tregister($04180003);
+NR_V3_16B = tregister($04190003);
+NR_V3_4H = tregister($041a0003);
+NR_V3_8H = tregister($041b0003);
+NR_V3_2S = tregister($041c0003);
+NR_V3_4S = tregister($041d0003);
+NR_V3_1D = tregister($041e0003);
+NR_V3_2D = tregister($041f0003);
 NR_B4 = tregister($04010004);
 NR_H4 = tregister($04030004);
 NR_S4 = tregister($04090004);
 NR_D4 = tregister($040a0004);
-NR_Q4 = tregister($04050004);
-NR_V48B = tregister($04170004);
-NR_V416B = tregister($04180004);
+NR_Q4 = tregister($040b0004);
+NR_V4 = tregister($04000004);
+NR_V4_B = tregister($04200004);
+NR_V4_H = tregister($04210004);
+NR_V4_S = tregister($04220004);
+NR_V4_D = tregister($04230004);
+NR_V4_8B = tregister($04180004);
+NR_V4_16B = tregister($04190004);
+NR_V4_4H = tregister($041a0004);
+NR_V4_8H = tregister($041b0004);
+NR_V4_2S = tregister($041c0004);
+NR_V4_4S = tregister($041d0004);
+NR_V4_1D = tregister($041e0004);
+NR_V4_2D = tregister($041f0004);
 NR_B5 = tregister($04010005);
 NR_H5 = tregister($04030005);
 NR_S5 = tregister($04090005);
 NR_D5 = tregister($040a0005);
-NR_Q5 = tregister($04050005);
-NR_V58B = tregister($04170005);
-NR_V516B = tregister($04180005);
+NR_Q5 = tregister($040b0005);
+NR_V5 = tregister($04000005);
+NR_V5_B = tregister($04200005);
+NR_V5_H = tregister($04210005);
+NR_V5_S = tregister($04220005);
+NR_V5_D = tregister($04230005);
+NR_V5_8B = tregister($04180005);
+NR_V5_16B = tregister($04190005);
+NR_V5_4H = tregister($041a0005);
+NR_V5_8H = tregister($041b0005);
+NR_V5_2S = tregister($041c0005);
+NR_V5_4S = tregister($041d0005);
+NR_V5_1D = tregister($041e0005);
+NR_V5_2D = tregister($041f0005);
 NR_B6 = tregister($04010006);
 NR_H6 = tregister($04030006);
 NR_S6 = tregister($04090006);
 NR_D6 = tregister($040a0006);
-NR_Q6 = tregister($04050006);
-NR_V68B = tregister($04170006);
-NR_V616B = tregister($04180006);
+NR_Q6 = tregister($040b0006);
+NR_V6 = tregister($04000006);
+NR_V6_B = tregister($04200006);
+NR_V6_H = tregister($04210006);
+NR_V6_S = tregister($04220006);
+NR_V6_D = tregister($04230006);
+NR_V6_8B = tregister($04180006);
+NR_V6_16B = tregister($04190006);
+NR_V6_4H = tregister($041a0006);
+NR_V6_8H = tregister($041b0006);
+NR_V6_2S = tregister($041c0006);
+NR_V6_4S = tregister($041d0006);
+NR_V6_1D = tregister($041e0006);
+NR_V6_2D = tregister($041f0006);
 NR_B7 = tregister($04010007);
 NR_H7 = tregister($04030007);
 NR_S7 = tregister($04090007);
 NR_D7 = tregister($040a0007);
-NR_Q7 = tregister($04050007);
-NR_V78B = tregister($04170007);
-NR_V716B = tregister($04180007);
+NR_Q7 = tregister($040b0007);
+NR_V7 = tregister($04000007);
+NR_V7_B = tregister($04200007);
+NR_V7_H = tregister($04210007);
+NR_V7_S = tregister($04220007);
+NR_V7_D = tregister($04230007);
+NR_V7_8B = tregister($04180007);
+NR_V7_16B = tregister($04190007);
+NR_V7_4H = tregister($041a0007);
+NR_V7_8H = tregister($041b0007);
+NR_V7_2S = tregister($041c0007);
+NR_V7_4S = tregister($041d0007);
+NR_V7_1D = tregister($041e0007);
+NR_V7_2D = tregister($041f0007);
 NR_B8 = tregister($04010008);
 NR_H8 = tregister($04030008);
 NR_S8 = tregister($04090008);
 NR_D8 = tregister($040a0008);
-NR_Q8 = tregister($04050008);
-NR_V88B = tregister($04170008);
-NR_V816B = tregister($04180008);
+NR_Q8 = tregister($040b0008);
+NR_V8 = tregister($04000008);
+NR_V8_B = tregister($04200008);
+NR_V8_H = tregister($04210008);
+NR_V8_S = tregister($04220008);
+NR_V8_D = tregister($04230008);
+NR_V8_8B = tregister($04180008);
+NR_V8_16B = tregister($04190008);
+NR_V8_4H = tregister($041a0008);
+NR_V8_8H = tregister($041b0008);
+NR_V8_2S = tregister($041c0008);
+NR_V8_4S = tregister($041d0008);
+NR_V8_1D = tregister($041e0008);
+NR_V8_2D = tregister($041f0008);
 NR_B9 = tregister($04010009);
 NR_H9 = tregister($04030009);
 NR_S9 = tregister($04090009);
 NR_D9 = tregister($040a0009);
-NR_Q9 = tregister($04050009);
-NR_V98B = tregister($04170009);
-NR_V916B = tregister($04180009);
+NR_Q9 = tregister($040b0009);
+NR_V9 = tregister($04000009);
+NR_V9_B = tregister($04200009);
+NR_V9_H = tregister($04210009);
+NR_V9_S = tregister($04220009);
+NR_V9_D = tregister($04230009);
+NR_V9_8B = tregister($04180009);
+NR_V9_16B = tregister($04190009);
+NR_V9_4H = tregister($041a0009);
+NR_V9_8H = tregister($041b0009);
+NR_V9_2S = tregister($041c0009);
+NR_V9_4S = tregister($041d0009);
+NR_V9_1D = tregister($041e0009);
+NR_V9_2D = tregister($041f0009);
 NR_B10 = tregister($0401000A);
 NR_H10 = tregister($0403000A);
 NR_S10 = tregister($0409000A);
 NR_D10 = tregister($040a000A);
-NR_Q10 = tregister($0405000A);
-NR_V108B = tregister($0417000A);
-NR_V1016B = tregister($0418000A);
+NR_Q10 = tregister($040b000A);
+NR_V10 = tregister($0400000A);
+NR_V10_B = tregister($0420000A);
+NR_V10_H = tregister($0421000A);
+NR_V10_S = tregister($0422000A);
+NR_V10_D = tregister($0423000A);
+NR_V10_8B = tregister($0418000A);
+NR_V10_16B = tregister($0419000A);
+NR_V10_4H = tregister($041a000A);
+NR_V10_8H = tregister($041b000A);
+NR_V10_2S = tregister($041c000A);
+NR_V10_4S = tregister($041d000A);
+NR_V10_1D = tregister($041e000A);
+NR_V10_2D = tregister($041f000A);
 NR_B11 = tregister($0401000B);
 NR_H11 = tregister($0403000B);
 NR_S11 = tregister($0409000B);
 NR_D11 = tregister($040a000B);
-NR_Q11 = tregister($0405000B);
-NR_V118B = tregister($0417000B);
-NR_V1116B = tregister($0418000B);
+NR_Q11 = tregister($040b000B);
+NR_V11 = tregister($0400000B);
+NR_V11_B = tregister($0420000B);
+NR_V11_H = tregister($0421000B);
+NR_V11_S = tregister($0422000B);
+NR_V11_D = tregister($0423000B);
+NR_V11_8B = tregister($0418000B);
+NR_V11_16B = tregister($0419000B);
+NR_V11_4H = tregister($041a000B);
+NR_V11_8H = tregister($041b000B);
+NR_V11_2S = tregister($041c000B);
+NR_V11_4S = tregister($041d000B);
+NR_V11_1D = tregister($041e000B);
+NR_V11_2D = tregister($041f000B);
 NR_B12 = tregister($0401000C);
 NR_H12 = tregister($0403000C);
 NR_S12 = tregister($0409000C);
 NR_D12 = tregister($040a000C);
-NR_Q12 = tregister($0405000C);
-NR_V128B = tregister($0417000C);
-NR_V1216B = tregister($0418000C);
+NR_Q12 = tregister($040b000C);
+NR_V12 = tregister($0400000C);
+NR_V12_B = tregister($0420000C);
+NR_V12_H = tregister($0421000C);
+NR_V12_S = tregister($0422000C);
+NR_V12_D = tregister($0423000C);
+NR_V12_8B = tregister($0418000C);
+NR_V12_16B = tregister($0419000C);
+NR_V12_4H = tregister($041a000C);
+NR_V12_8H = tregister($041b000C);
+NR_V12_2S = tregister($041c000C);
+NR_V12_4S = tregister($041d000C);
+NR_V12_1D = tregister($041e000C);
+NR_V12_2D = tregister($041f000C);
 NR_B13 = tregister($0401000D);
 NR_H13 = tregister($0403000D);
 NR_S13 = tregister($0409000D);
 NR_D13 = tregister($040a000D);
-NR_Q13 = tregister($0405000D);
-NR_V138B = tregister($0417000D);
-NR_V1316B = tregister($0418000D);
+NR_Q13 = tregister($040b000D);
+NR_V13 = tregister($0400000D);
+NR_V13_B = tregister($0420000D);
+NR_V13_H = tregister($0421000D);
+NR_V13_S = tregister($0422000D);
+NR_V13_D = tregister($0423000D);
+NR_V13_8B = tregister($0418000D);
+NR_V13_16B = tregister($0419000D);
+NR_V13_4H = tregister($041a000D);
+NR_V13_8H = tregister($041b000D);
+NR_V13_2S = tregister($041c000D);
+NR_V13_4S = tregister($041d000D);
+NR_V13_1D = tregister($041e000D);
+NR_V13_2D = tregister($041f000D);
 NR_B14 = tregister($0401000E);
 NR_H14 = tregister($0403000E);
 NR_S14 = tregister($0409000E);
 NR_D14 = tregister($040a000E);
-NR_Q14 = tregister($0405000E);
-NR_V148B = tregister($0417000E);
-NR_V1416B = tregister($0418000E);
+NR_Q14 = tregister($040b000E);
+NR_V14 = tregister($0400000E);
+NR_V14_B = tregister($0420000E);
+NR_V14_H = tregister($0421000E);
+NR_V14_S = tregister($0422000E);
+NR_V14_D = tregister($0423000E);
+NR_V14_8B = tregister($0418000E);
+NR_V14_16B = tregister($0419000E);
+NR_V14_4H = tregister($041a000E);
+NR_V14_8H = tregister($041b000E);
+NR_V14_2S = tregister($041c000E);
+NR_V14_4S = tregister($041d000E);
+NR_V14_1D = tregister($041e000E);
+NR_V14_2D = tregister($041f000E);
 NR_B15 = tregister($0401000F);
 NR_H15 = tregister($0403000F);
 NR_S15 = tregister($0409000F);
 NR_D15 = tregister($040a000F);
-NR_Q15 = tregister($0405000F);
-NR_V158B = tregister($0417000F);
-NR_V1516B = tregister($0418000F);
+NR_Q15 = tregister($040b000F);
+NR_V15 = tregister($0400000F);
+NR_V15_B = tregister($0420000F);
+NR_V15_H = tregister($0421000F);
+NR_V15_S = tregister($0422000F);
+NR_V15_D = tregister($0423000F);
+NR_V15_8B = tregister($0418000F);
+NR_V15_16B = tregister($0419000F);
+NR_V15_4H = tregister($041a000F);
+NR_V15_8H = tregister($041b000F);
+NR_V15_2S = tregister($041c000F);
+NR_V15_4S = tregister($041d000F);
+NR_V15_1D = tregister($041e000F);
+NR_V15_2D = tregister($041f000F);
 NR_B16 = tregister($04010010);
 NR_H16 = tregister($04030010);
 NR_S16 = tregister($04090010);
 NR_D16 = tregister($040a0010);
-NR_Q16 = tregister($04050010);
-NR_V168B = tregister($04170010);
-NR_V1616B = tregister($04180010);
+NR_Q16 = tregister($040b0010);
+NR_V16 = tregister($04000010);
+NR_V16_B = tregister($04200010);
+NR_V16_H = tregister($04210010);
+NR_V16_S = tregister($04220010);
+NR_V16_D = tregister($04230010);
+NR_V16_8B = tregister($04180010);
+NR_V16_16B = tregister($04190010);
+NR_V16_4H = tregister($041a0010);
+NR_V16_8H = tregister($041b0010);
+NR_V16_2S = tregister($041c0010);
+NR_V16_4S = tregister($041d0010);
+NR_V16_1D = tregister($041e0010);
+NR_V16_2D = tregister($041f0010);
 NR_B17 = tregister($04010011);
 NR_H17 = tregister($04030011);
 NR_S17 = tregister($04090011);
 NR_D17 = tregister($040a0011);
-NR_Q17 = tregister($04050011);
-NR_V178B = tregister($04170011);
-NR_V1716B = tregister($04180011);
+NR_Q17 = tregister($040b0011);
+NR_V17 = tregister($04000011);
+NR_V17_B = tregister($04200011);
+NR_V17_H = tregister($04210011);
+NR_V17_S = tregister($04220011);
+NR_V17_D = tregister($04230011);
+NR_V17_8B = tregister($04180011);
+NR_V17_16B = tregister($04190011);
+NR_V17_4H = tregister($041a0011);
+NR_V17_8H = tregister($041b0011);
+NR_V17_2S = tregister($041c0011);
+NR_V17_4S = tregister($041d0011);
+NR_V17_1D = tregister($041e0011);
+NR_V17_2D = tregister($041f0011);
 NR_B18 = tregister($04010012);
 NR_H18 = tregister($04030012);
 NR_S18 = tregister($04090012);
 NR_D18 = tregister($040a0012);
-NR_Q18 = tregister($04050012);
-NR_V188B = tregister($04170012);
-NR_V1816B = tregister($04180012);
+NR_Q18 = tregister($040b0012);
+NR_V18 = tregister($04000012);
+NR_V18_B = tregister($04200012);
+NR_V18_H = tregister($04210012);
+NR_V18_S = tregister($04220012);
+NR_V18_D = tregister($04230012);
+NR_V18_8B = tregister($04180012);
+NR_V18_16B = tregister($04190012);
+NR_V18_4H = tregister($041a0012);
+NR_V18_8H = tregister($041b0012);
+NR_V18_2S = tregister($041c0012);
+NR_V18_4S = tregister($041d0012);
+NR_V18_1D = tregister($041e0012);
+NR_V18_2D = tregister($041f0012);
 NR_B19 = tregister($04010013);
 NR_H19 = tregister($04030013);
 NR_S19 = tregister($04090013);
 NR_D19 = tregister($040a0013);
-NR_Q19 = tregister($04050013);
-NR_V198B = tregister($04170013);
-NR_V1916B = tregister($04180013);
+NR_Q19 = tregister($040b0013);
+NR_V19 = tregister($04000013);
+NR_V19_B = tregister($04200013);
+NR_V19_H = tregister($04210013);
+NR_V19_S = tregister($04220013);
+NR_V19_D = tregister($04230013);
+NR_V19_8B = tregister($04180013);
+NR_V19_16B = tregister($04190013);
+NR_V19_4H = tregister($041a0013);
+NR_V19_8H = tregister($041b0013);
+NR_V19_2S = tregister($041c0013);
+NR_V19_4S = tregister($041d0013);
+NR_V19_1D = tregister($041e0013);
+NR_V19_2D = tregister($041f0013);
 NR_B20 = tregister($04010014);
 NR_H20 = tregister($04030014);
 NR_S20 = tregister($04090014);
 NR_D20 = tregister($040a0014);
-NR_Q20 = tregister($04050014);
-NR_V208B = tregister($04170014);
-NR_V2016B = tregister($04180014);
+NR_Q20 = tregister($040b0014);
+NR_V20 = tregister($04000014);
+NR_V20_B = tregister($04200014);
+NR_V20_H = tregister($04210014);
+NR_V20_S = tregister($04220014);
+NR_V20_D = tregister($04230014);
+NR_V20_8B = tregister($04180014);
+NR_V20_16B = tregister($04190014);
+NR_V20_4H = tregister($041a0014);
+NR_V20_8H = tregister($041b0014);
+NR_V20_2S = tregister($041c0014);
+NR_V20_4S = tregister($041d0014);
+NR_V20_1D = tregister($041e0014);
+NR_V20_2D = tregister($041f0014);
 NR_B21 = tregister($04010015);
 NR_H21 = tregister($04030015);
 NR_S21 = tregister($04090015);
 NR_D21 = tregister($040a0015);
-NR_Q21 = tregister($04050015);
-NR_V218B = tregister($04170015);
-NR_V2116B = tregister($04180015);
+NR_Q21 = tregister($040b0015);
+NR_V21 = tregister($04000015);
+NR_V21_B = tregister($04200015);
+NR_V21_H = tregister($04210015);
+NR_V21_S = tregister($04220015);
+NR_V21_D = tregister($04230015);
+NR_V21_8B = tregister($04180015);
+NR_V21_16B = tregister($04190015);
+NR_V21_4H = tregister($041a0015);
+NR_V21_8H = tregister($041b0015);
+NR_V21_2S = tregister($041c0015);
+NR_V21_4S = tregister($041d0015);
+NR_V21_1D = tregister($041e0015);
+NR_V21_2D = tregister($041f0015);
 NR_B22 = tregister($04010016);
 NR_H22 = tregister($04030016);
 NR_S22 = tregister($04090016);
 NR_D22 = tregister($040a0016);
-NR_Q22 = tregister($04050016);
-NR_V228B = tregister($04170016);
-NR_V2216B = tregister($04180016);
+NR_Q22 = tregister($040b0016);
+NR_V22 = tregister($04000016);
+NR_V22_B = tregister($04200016);
+NR_V22_H = tregister($04210016);
+NR_V22_S = tregister($04220016);
+NR_V22_D = tregister($04230016);
+NR_V22_8B = tregister($04180016);
+NR_V22_16B = tregister($04190016);
+NR_V22_4H = tregister($041a0016);
+NR_V22_8H = tregister($041b0016);
+NR_V22_2S = tregister($041c0016);
+NR_V22_4S = tregister($041d0016);
+NR_V22_1D = tregister($041e0016);
+NR_V22_2D = tregister($041f0016);
 NR_B23 = tregister($04010017);
 NR_H23 = tregister($04030017);
 NR_S23 = tregister($04090017);
 NR_D23 = tregister($040a0017);
-NR_Q23 = tregister($04050017);
-NR_V238B = tregister($04170017);
-NR_V2316B = tregister($04180017);
+NR_Q23 = tregister($040b0017);
+NR_V23 = tregister($04000017);
+NR_V23_B = tregister($04200017);
+NR_V23_H = tregister($04210017);
+NR_V23_S = tregister($04220017);
+NR_V23_D = tregister($04230017);
+NR_V23_8B = tregister($04180017);
+NR_V23_16B = tregister($04190017);
+NR_V23_4H = tregister($041a0017);
+NR_V23_8H = tregister($041b0017);
+NR_V23_2S = tregister($041c0017);
+NR_V23_4S = tregister($041d0017);
+NR_V23_1D = tregister($041e0017);
+NR_V23_2D = tregister($041f0017);
 NR_B24 = tregister($04010018);
 NR_H24 = tregister($04030018);
 NR_S24 = tregister($04090018);
 NR_D24 = tregister($040a0018);
-NR_Q24 = tregister($04050018);
-NR_V248B = tregister($04170018);
-NR_V2416B = tregister($04180018);
+NR_Q24 = tregister($040b0018);
+NR_V24 = tregister($04000018);
+NR_V24_B = tregister($04200018);
+NR_V24_H = tregister($04210018);
+NR_V24_S = tregister($04220018);
+NR_V24_D = tregister($04230018);
+NR_V24_8B = tregister($04180018);
+NR_V24_16B = tregister($04190018);
+NR_V24_4H = tregister($041a0018);
+NR_V24_8H = tregister($041b0018);
+NR_V24_2S = tregister($041c0018);
+NR_V24_4S = tregister($041d0018);
+NR_V24_1D = tregister($041e0018);
+NR_V24_2D = tregister($041f0018);
 NR_B25 = tregister($04010019);
 NR_H25 = tregister($04030019);
 NR_S25 = tregister($04090019);
 NR_D25 = tregister($040a0019);
-NR_Q25 = tregister($04050019);
-NR_V258B = tregister($04170019);
-NR_V2516B = tregister($04180019);
+NR_Q25 = tregister($040b0019);
+NR_V25 = tregister($04000019);
+NR_V25_B = tregister($04200019);
+NR_V25_H = tregister($04210019);
+NR_V25_S = tregister($04220019);
+NR_V25_D = tregister($04230019);
+NR_V25_8B = tregister($04180019);
+NR_V25_16B = tregister($04190019);
+NR_V25_4H = tregister($041a0019);
+NR_V25_8H = tregister($041b0019);
+NR_V25_2S = tregister($041c0019);
+NR_V25_4S = tregister($041d0019);
+NR_V25_1D = tregister($041e0019);
+NR_V25_2D = tregister($041f0019);
 NR_B26 = tregister($0401001A);
 NR_H26 = tregister($0403001A);
 NR_S26 = tregister($0409001A);
 NR_D26 = tregister($040a001A);
-NR_Q26 = tregister($0405001A);
-NR_V268B = tregister($0417001A);
-NR_V2616B = tregister($0418001A);
+NR_Q26 = tregister($040b001A);
+NR_V26 = tregister($0400001A);
+NR_V26_B = tregister($0420001A);
+NR_V26_H = tregister($0421001A);
+NR_V26_S = tregister($0422001A);
+NR_V26_D = tregister($0423001A);
+NR_V26_8B = tregister($0418001A);
+NR_V26_16B = tregister($0419001A);
+NR_V26_4H = tregister($041a001A);
+NR_V26_8H = tregister($041b001A);
+NR_V26_2S = tregister($041c001A);
+NR_V26_4S = tregister($041d001A);
+NR_V26_1D = tregister($041e001A);
+NR_V26_2D = tregister($041f001A);
 NR_B27 = tregister($0401001B);
 NR_H27 = tregister($0403001B);
 NR_S27 = tregister($0409001B);
 NR_D27 = tregister($040a001B);
-NR_Q27 = tregister($0405001B);
-NR_V278B = tregister($0417001B);
-NR_V2716B = tregister($0418001B);
+NR_Q27 = tregister($040b001B);
+NR_V27 = tregister($0400001B);
+NR_V27_B = tregister($0420001B);
+NR_V27_H = tregister($0421001B);
+NR_V27_S = tregister($0422001B);
+NR_V27_D = tregister($0423001B);
+NR_V27_8B = tregister($0418001B);
+NR_V27_16B = tregister($0419001B);
+NR_V27_4H = tregister($041a001B);
+NR_V27_8H = tregister($041b001B);
+NR_V27_2S = tregister($041c001B);
+NR_V27_4S = tregister($041d001B);
+NR_V27_1D = tregister($041e001B);
+NR_V27_2D = tregister($041f001B);
 NR_B28 = tregister($0401001C);
 NR_H28 = tregister($0403001C);
 NR_S28 = tregister($0409001C);
 NR_D28 = tregister($040a001C);
-NR_Q28 = tregister($0405001C);
-NR_V288B = tregister($0417001C);
-NR_V2816B = tregister($0418001C);
+NR_Q28 = tregister($040b001C);
+NR_V28 = tregister($0400001C);
+NR_V28_B = tregister($0420001C);
+NR_V28_H = tregister($0421001C);
+NR_V28_S = tregister($0422001C);
+NR_V28_D = tregister($0423001C);
+NR_V28_8B = tregister($0418001C);
+NR_V28_16B = tregister($0419001C);
+NR_V28_4H = tregister($041a001C);
+NR_V28_8H = tregister($041b001C);
+NR_V28_2S = tregister($041c001C);
+NR_V28_4S = tregister($041d001C);
+NR_V28_1D = tregister($041e001C);
+NR_V28_2D = tregister($041f001C);
 NR_B29 = tregister($0401001D);
 NR_H29 = tregister($0403001D);
 NR_S29 = tregister($0409001D);
 NR_D29 = tregister($040a001D);
-NR_Q29 = tregister($0405001D);
-NR_V298B = tregister($0417001D);
-NR_V2916B = tregister($0418001D);
+NR_Q29 = tregister($040b001D);
+NR_V29 = tregister($0400001D);
+NR_V29_B = tregister($0420001D);
+NR_V29_H = tregister($0421001D);
+NR_V29_S = tregister($0422001D);
+NR_V29_D = tregister($0423001D);
+NR_V29_8B = tregister($0418001D);
+NR_V29_16B = tregister($0419001D);
+NR_V29_4H = tregister($041a001D);
+NR_V29_8H = tregister($041b001D);
+NR_V29_2S = tregister($041c001D);
+NR_V29_4S = tregister($041d001D);
+NR_V29_1D = tregister($041e001D);
+NR_V29_2D = tregister($041f001D);
 NR_B30 = tregister($0401001E);
 NR_H30 = tregister($0403001E);
 NR_S30 = tregister($0409001E);
 NR_D30 = tregister($040a001E);
-NR_Q30 = tregister($0405001E);
-NR_V308B = tregister($0417001E);
-NR_V3016B = tregister($0418001E);
+NR_Q30 = tregister($040b001E);
+NR_V30 = tregister($0400001E);
+NR_V30_B = tregister($0420001E);
+NR_V30_H = tregister($0421001E);
+NR_V30_S = tregister($0422001E);
+NR_V30_D = tregister($0423001E);
+NR_V30_8B = tregister($0418001E);
+NR_V30_16B = tregister($0419001E);
+NR_V30_4H = tregister($041a001E);
+NR_V30_8H = tregister($041b001E);
+NR_V30_2S = tregister($041c001E);
+NR_V30_4S = tregister($041d001E);
+NR_V30_1D = tregister($041e001E);
+NR_V30_2D = tregister($041f001E);
 NR_B31 = tregister($0401001F);
 NR_H31 = tregister($0403001F);
 NR_S31 = tregister($0409001F);
 NR_D31 = tregister($040a001F);
-NR_Q31 = tregister($0405001F);
-NR_V318B = tregister($0417001F);
-NR_V3116B = tregister($0418001F);
-NR_NZCV = tregister($05000000);
-NR_FPCR = tregister($05000001);
-NR_FPSR = tregister($05000002);
-NR_TPIDR_EL0 = tregister($05000003);
+NR_Q31 = tregister($040b001F);
+NR_V31 = tregister($0400001F);
+NR_V31_B = tregister($0420001F);
+NR_V31_H = tregister($0421001F);
+NR_V31_S = tregister($0422001F);
+NR_V31_D = tregister($0423001F);
+NR_V31_8B = tregister($0418001F);
+NR_V31_16B = tregister($0419001F);
+NR_V31_4H = tregister($041a001F);
+NR_V31_8H = tregister($041b001F);
+NR_V31_2S = tregister($041c001F);
+NR_V31_4S = tregister($041d001F);
+NR_V31_1D = tregister($041e001F);
+NR_V31_2D = tregister($041f001F);

compiler/aarch64/ra64dwa.inc

@@ -66,6 +66,18 @@
 31,
 31,
 31,
+0,
+0,
+0,
+0,
+64,
+64,
+64,
+64,
+64,
+64,
+64,
+64,
 64,
 64,
 64,
@@ -73,6 +85,17 @@
 64,
 64,
 64,
+64,
+64,
+64,
+65,
+65,
+65,
+65,
+65,
+65,
+65,
+65,
 65,
 65,
 65,
@@ -80,6 +103,17 @@
 65,
 65,
 65,
+65,
+65,
+65,
+66,
+66,
+66,
+66,
+66,
+66,
+66,
+66,
 66,
 66,
 66,
@@ -87,6 +121,17 @@
 66,
 66,
 66,
+66,
+66,
+66,
+67,
+67,
+67,
+67,
+67,
+67,
+67,
+67,
 67,
 67,
 67,
@@ -94,6 +139,18 @@
 67,
 67,
 67,
+67,
+67,
+67,
+68,
+68,
+68,
+68,
+68,
+68,
+68,
+68,
+68,
 68,
 68,
 68,
@@ -101,6 +158,17 @@
 68,
 68,
 68,
+68,
+68,
+69,
+69,
+69,
+69,
+69,
+69,
+69,
+69,
+69,
 69,
 69,
 69,
@@ -108,13 +176,34 @@
 69,
 69,
 69,
+69,
+69,
+70,
+70,
+70,
+70,
+70,
+70,
+70,
+70,
+70,
 70,
 70,
-70                                                             ,
 70,
 70,
 70,
 70,
+70,
+70,
+70,
+71,
+71,
+71,
+71,
+71,
+71,
+71,
+71,
 71,
 71,
 71,
@@ -122,6 +211,18 @@
 71,
 71,
 71,
+71,
+71,
+71,
+72,
+72,
+72,
+72,
+72,
+72,
+72,
+72,
+72,
 72,
 72,
 72,
@@ -129,6 +230,17 @@
 72,
 72,
 72,
+72,
+72,
+73,
+73,
+73,
+73,
+73,
+73,
+73,
+73,
+73,
 73,
 73,
 73,
@@ -136,6 +248,17 @@
 73,
 73,
 73,
+73,
+73,
+74,
+74,
+74,
+74,
+74,
+74,
+74,
+74,
+74,
 74,
 74,
 74,
@@ -143,6 +266,17 @@
 74,
 74,
 74,
+74,
+74,
+75,
+75,
+75,
+75,
+75,
+75,
+75,
+75,
+75,
 75,
 75,
 75,
@@ -150,6 +284,18 @@
 75,
 75,
 75,
+75,
+75,
+76,
+76,
+76,
+76,
+76,
+76,
+76,
+76,
+76,
+76,
 76,
 76,
 76,
@@ -157,6 +303,17 @@
 76,
 76,
 76,
+76,
+77,
+77,
+77,
+77,
+77,
+77,
+77,
+77,
+77,
+77,
 77,
 77,
 77,
@@ -164,6 +321,17 @@
 77,
 77,
 77,
+77,
+78,
+78,
+78,
+78,
+78,
+78,
+78,
+78,
+78,
+78,
 78,
 78,
 78,
@@ -171,6 +339,17 @@
 78,
 78,
 78,
+78,
+79,
+79,
+79,
+79,
+79,
+79,
+79,
+79,
+79,
+79,
 79,
 79,
 79,
@@ -178,6 +357,18 @@
 79,
 79,
 79,
+79,
+80,
+80,
+80,
+80,
+80,
+80,
+80,
+80,
+80,
+80,
+80,
 80,
 80,
 80,
@@ -192,6 +383,17 @@
 81,
 81,
 81,
+81,
+81,
+81,
+81,
+81,
+81,
+81,
+81,
+81,
+81,
+81,
 82,
 82,
 82,
@@ -199,6 +401,28 @@
 82,
 82,
 82,
+82,
+82,
+82,
+82,
+82,
+82,
+82,
+82,
+82,
+82,
+82,
+83,
+83,
+83,
+83,
+83,
+83,
+83,
+83,
+83,
+83,
+83,
 83,
 83,
 83,
@@ -213,6 +437,18 @@
 84,
 84,
 84,
+84,
+84,
+84,
+84,
+84,
+84,
+84,
+84,
+84,
+84,
+84,
+85,
 85,
 85,
 85,
@@ -220,6 +456,17 @@
 85,
 85,
 85,
+85,
+85,
+85,
+85,
+85,
+85,
+85,
+85,
+85,
+85,
+86,
 86,
 86,
 86,
@@ -227,6 +474,17 @@
 86,
 86,
 86,
+86,
+86,
+86,
+86,
+86,
+86,
+86,
+86,
+86,
+86,
+87,
 87,
 87,
 87,
@@ -234,6 +492,17 @@
 87,
 87,
 87,
+87,
+87,
+87,
+87,
+87,
+87,
+87,
+87,
+87,
+87,
+88,
 88,
 88,
 88,
@@ -241,6 +510,18 @@
 88,
 88,
 88,
+88,
+88,
+88,
+88,
+88,
+88,
+88,
+88,
+88,
+88,
+89,
+89,
 89,
 89,
 89,
@@ -248,6 +529,17 @@
 89,
 89,
 89,
+89,
+89,
+89,
+89,
+89,
+89,
+89,
+89,
+89,
+90,
+90,
 90,
 90,
 90,
@@ -255,6 +547,17 @@
 90,
 90,
 90,
+90,
+90,
+90,
+90,
+90,
+90,
+90,
+90,
+90,
+91,
+91,
 91,
 91,
 91,
@@ -262,6 +565,17 @@
 91,
 91,
 91,
+91,
+91,
+91,
+91,
+91,
+91,
+91,
+91,
+91,
+92,
+92,
 92,
 92,
 92,
@@ -269,6 +583,17 @@
 92,
 92,
 92,
+92,
+92,
+92,
+92,
+92,
+92,
+92,
+92,
+92,
+93,
+93,
 93,
 93,
 93,
@@ -276,6 +601,26 @@
 93,
 93,
 93,
+93,
+93,
+93,
+93,
+93,
+93,
+93,
+93,
+93,
+94,
+94,
+94,
+94,
+94,
+94,
+94,
+94,
+94,
+94,
+94,
 94,
 94,
 94,
@@ -290,7 +635,14 @@
 95,
 95,
 95,
-0,
-0,
-0,
-0
+95,
+95,
+95,
+95,
+95,
+95,
+95,
+95,
+95,
+95,
+95

compiler/aarch64/ra64nor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from a64reg.dat }
-295
+647

compiler/aarch64/ra64num.inc

@@ -66,231 +66,583 @@ tregister($0104001F),
 tregister($0105001F),
 tregister($01040020),
 tregister($01050020),
+tregister($05000000),
+tregister($05000001),
+tregister($05000002),
+tregister($05000003),
 tregister($04010000),
 tregister($04030000),
 tregister($04090000),
 tregister($040a0000),
-tregister($04050000),
-tregister($04170000),
+tregister($040b0000),
+tregister($04000000),
+tregister($04200000),
+tregister($04210000),
+tregister($04220000),
+tregister($04230000),
 tregister($04180000),
+tregister($04190000),
+tregister($041a0000),
+tregister($041b0000),
+tregister($041c0000),
+tregister($041d0000),
+tregister($041e0000),
+tregister($041f0000),
 tregister($04010001),
 tregister($04030001),
 tregister($04090001),
 tregister($040a0001),
-tregister($04050001),
-tregister($04170001),
+tregister($040b0001),
+tregister($04000001),
+tregister($04200001),
+tregister($04210001),
+tregister($04220001),
+tregister($04230001),
 tregister($04180001),
+tregister($04190001),
+tregister($041a0001),
+tregister($041b0001),
+tregister($041c0001),
+tregister($041d0001),
+tregister($041e0001),
+tregister($041f0001),
 tregister($04010002),
 tregister($04030002),
 tregister($04090002),
 tregister($040a0002),
-tregister($04050002),
-tregister($04170002),
+tregister($040b0002),
+tregister($04000002),
+tregister($04200002),
+tregister($04210002),
+tregister($04220002),
+tregister($04230002),
 tregister($04180002),
+tregister($04190002),
+tregister($041a0002),
+tregister($041b0002),
+tregister($041c0002),
+tregister($041d0002),
+tregister($041e0002),
+tregister($041f0002),
 tregister($04010003),
 tregister($04030003),
 tregister($04090003),
 tregister($040a0003),
-tregister($04050003),
-tregister($04170003),
+tregister($040b0003),
+tregister($04000003),
+tregister($04200003),
+tregister($04210003),
+tregister($04220003),
+tregister($04230003),
 tregister($04180003),
+tregister($04190003),
+tregister($041a0003),
+tregister($041b0003),
+tregister($041c0003),
+tregister($041d0003),
+tregister($041e0003),
+tregister($041f0003),
 tregister($04010004),
 tregister($04030004),
 tregister($04090004),
 tregister($040a0004),
-tregister($04050004),
-tregister($04170004),
+tregister($040b0004),
+tregister($04000004),
+tregister($04200004),
+tregister($04210004),
+tregister($04220004),
+tregister($04230004),
 tregister($04180004),
+tregister($04190004),
+tregister($041a0004),
+tregister($041b0004),
+tregister($041c0004),
+tregister($041d0004),
+tregister($041e0004),
+tregister($041f0004),
 tregister($04010005),
 tregister($04030005),
 tregister($04090005),
 tregister($040a0005),
-tregister($04050005),
-tregister($04170005),
+tregister($040b0005),
+tregister($04000005),
+tregister($04200005),
+tregister($04210005),
+tregister($04220005),
+tregister($04230005),
 tregister($04180005),
+tregister($04190005),
+tregister($041a0005),
+tregister($041b0005),
+tregister($041c0005),
+tregister($041d0005),
+tregister($041e0005),
+tregister($041f0005),
 tregister($04010006),
 tregister($04030006),
 tregister($04090006),
 tregister($040a0006),
-tregister($04050006),
-tregister($04170006),
+tregister($040b0006),
+tregister($04000006),
+tregister($04200006),
+tregister($04210006),
+tregister($04220006),
+tregister($04230006),
 tregister($04180006),
+tregister($04190006),
+tregister($041a0006),
+tregister($041b0006),
+tregister($041c0006),
+tregister($041d0006),
+tregister($041e0006),
+tregister($041f0006),
 tregister($04010007),
 tregister($04030007),
 tregister($04090007),
 tregister($040a0007),
-tregister($04050007),
-tregister($04170007),
+tregister($040b0007),
+tregister($04000007),
+tregister($04200007),
+tregister($04210007),
+tregister($04220007),
+tregister($04230007),
 tregister($04180007),
+tregister($04190007),
+tregister($041a0007),
+tregister($041b0007),
+tregister($041c0007),
+tregister($041d0007),
+tregister($041e0007),
+tregister($041f0007),
 tregister($04010008),
 tregister($04030008),
 tregister($04090008),
 tregister($040a0008),
-tregister($04050008),
-tregister($04170008),
+tregister($040b0008),
+tregister($04000008),
+tregister($04200008),
+tregister($04210008),
+tregister($04220008),
+tregister($04230008),
 tregister($04180008),
+tregister($04190008),
+tregister($041a0008),
+tregister($041b0008),
+tregister($041c0008),
+tregister($041d0008),
+tregister($041e0008),
+tregister($041f0008),
 tregister($04010009),
 tregister($04030009),
 tregister($04090009),
 tregister($040a0009),
-tregister($04050009),
-tregister($04170009),
+tregister($040b0009),
+tregister($04000009),
+tregister($04200009),
+tregister($04210009),
+tregister($04220009),
+tregister($04230009),
 tregister($04180009),
+tregister($04190009),
+tregister($041a0009),
+tregister($041b0009),
+tregister($041c0009),
+tregister($041d0009),
+tregister($041e0009),
+tregister($041f0009),
 tregister($0401000A),
 tregister($0403000A),
 tregister($0409000A),
 tregister($040a000A),
-tregister($0405000A),
-tregister($0417000A),
+tregister($040b000A),
+tregister($0400000A),
+tregister($0420000A),
+tregister($0421000A),
+tregister($0422000A),
+tregister($0423000A),
 tregister($0418000A),
+tregister($0419000A),
+tregister($041a000A),
+tregister($041b000A),
+tregister($041c000A),
+tregister($041d000A),
+tregister($041e000A),
+tregister($041f000A),
 tregister($0401000B),
 tregister($0403000B),
 tregister($0409000B),
 tregister($040a000B),
-tregister($0405000B),
-tregister($0417000B),
+tregister($040b000B),
+tregister($0400000B),
+tregister($0420000B),
+tregister($0421000B),
+tregister($0422000B),
+tregister($0423000B),
 tregister($0418000B),
+tregister($0419000B),
+tregister($041a000B),
+tregister($041b000B),
+tregister($041c000B),
+tregister($041d000B),
+tregister($041e000B),
+tregister($041f000B),
 tregister($0401000C),
 tregister($0403000C),
 tregister($0409000C),
 tregister($040a000C),
-tregister($0405000C),
-tregister($0417000C),
+tregister($040b000C),
+tregister($0400000C),
+tregister($0420000C),
+tregister($0421000C),
+tregister($0422000C),
+tregister($0423000C),
 tregister($0418000C),
+tregister($0419000C),
+tregister($041a000C),
+tregister($041b000C),
+tregister($041c000C),
+tregister($041d000C),
+tregister($041e000C),
+tregister($041f000C),
 tregister($0401000D),
 tregister($0403000D),
 tregister($0409000D),
 tregister($040a000D),
-tregister($0405000D),
-tregister($0417000D),
+tregister($040b000D),
+tregister($0400000D),
+tregister($0420000D),
+tregister($0421000D),
+tregister($0422000D),
+tregister($0423000D),
 tregister($0418000D),
+tregister($0419000D),
+tregister($041a000D),
+tregister($041b000D),
+tregister($041c000D),
+tregister($041d000D),
+tregister($041e000D),
+tregister($041f000D),
 tregister($0401000E),
 tregister($0403000E),
 tregister($0409000E),
 tregister($040a000E),
-tregister($0405000E),
-tregister($0417000E),
+tregister($040b000E),
+tregister($0400000E),
+tregister($0420000E),
+tregister($0421000E),
+tregister($0422000E),
+tregister($0423000E),
 tregister($0418000E),
+tregister($0419000E),
+tregister($041a000E),
+tregister($041b000E),
+tregister($041c000E),
+tregister($041d000E),
+tregister($041e000E),
+tregister($041f000E),
 tregister($0401000F),
 tregister($0403000F),
 tregister($0409000F),
 tregister($040a000F),
-tregister($0405000F),
-tregister($0417000F),
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 tregister($0418000F),
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 tregister($04030010),
 tregister($04090010),
 tregister($040a0010),
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 tregister($04180010),
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+tregister($041c0010),
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+tregister($041e0010),
+tregister($041f0010),
 tregister($04010011),
 tregister($04030011),
 tregister($04090011),
 tregister($040a0011),
-tregister($04050011),
-tregister($04170011),
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 tregister($04180011),
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+tregister($041a0011),
+tregister($041b0011),
+tregister($041c0011),
+tregister($041d0011),
+tregister($041e0011),
+tregister($041f0011),
 tregister($04010012),
 tregister($04030012),
 tregister($04090012),
 tregister($040a0012),
-tregister($04050012),
-tregister($04170012),
+tregister($040b0012),
+tregister($04000012),
+tregister($04200012),
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+tregister($04220012),
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 tregister($04180012),
+tregister($04190012),
+tregister($041a0012),
+tregister($041b0012),
+tregister($041c0012),
+tregister($041d0012),
+tregister($041e0012),
+tregister($041f0012),
 tregister($04010013),
 tregister($04030013),
 tregister($04090013),
 tregister($040a0013),
-tregister($04050013),
-tregister($04170013),
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 tregister($04180013),
+tregister($04190013),
+tregister($041a0013),
+tregister($041b0013),
+tregister($041c0013),
+tregister($041d0013),
+tregister($041e0013),
+tregister($041f0013),
 tregister($04010014),
 tregister($04030014),
 tregister($04090014),
 tregister($040a0014),
-tregister($04050014),
-tregister($04170014),
+tregister($040b0014),
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 tregister($04180014),
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+tregister($041b0014),
+tregister($041c0014),
+tregister($041d0014),
+tregister($041e0014),
+tregister($041f0014),
 tregister($04010015),
 tregister($04030015),
 tregister($04090015),
 tregister($040a0015),
-tregister($04050015),
-tregister($04170015),
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 tregister($04180015),
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+tregister($041a0015),
+tregister($041b0015),
+tregister($041c0015),
+tregister($041d0015),
+tregister($041e0015),
+tregister($041f0015),
 tregister($04010016),
 tregister($04030016),
 tregister($04090016),
 tregister($040a0016),
-tregister($04050016),
-tregister($04170016),
+tregister($040b0016),
+tregister($04000016),
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 tregister($04180016),
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+tregister($041a0016),
+tregister($041b0016),
+tregister($041c0016),
+tregister($041d0016),
+tregister($041e0016),
+tregister($041f0016),
 tregister($04010017),
 tregister($04030017),
 tregister($04090017),
 tregister($040a0017),
-tregister($04050017),
-tregister($04170017),
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 tregister($04180017),
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+tregister($041a0017),
+tregister($041b0017),
+tregister($041c0017),
+tregister($041d0017),
+tregister($041e0017),
+tregister($041f0017),
 tregister($04010018),
 tregister($04030018),
 tregister($04090018),
 tregister($040a0018),
-tregister($04050018),
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 tregister($04180018),
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 tregister($0418001B),
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+tregister($041b001B),
+tregister($041c001B),
+tregister($041d001B),
+tregister($041e001B),
+tregister($041f001B),
 tregister($0401001C),
 tregister($0403001C),
 tregister($0409001C),
 tregister($040a001C),
-tregister($0405001C),
-tregister($0417001C),
+tregister($040b001C),
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+tregister($041b001C),
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+tregister($041d001C),
+tregister($041e001C),
+tregister($041f001C),
 tregister($0401001D),
 tregister($0403001D),
 tregister($0409001D),
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-tregister($0405001D),
-tregister($0417001D),
+tregister($040b001D),
+tregister($0400001D),
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 tregister($0418001D),
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+tregister($041b001D),
+tregister($041c001D),
+tregister($041d001D),
+tregister($041e001D),
+tregister($041f001D),
 tregister($0401001E),
 tregister($0403001E),
 tregister($0409001E),
 tregister($040a001E),
-tregister($0405001E),
-tregister($0417001E),
+tregister($040b001E),
+tregister($0400001E),
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 tregister($0418001E),
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+tregister($041d001E),
+tregister($041e001E),
+tregister($041f001E),
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-tregister($0405001F),
-tregister($0417001F),
+tregister($040b001F),
+tregister($0400001F),
+tregister($0420001F),
+tregister($0421001F),
+tregister($0422001F),
+tregister($0423001F),
 tregister($0418001F),
-tregister($05000000),
-tregister($05000001),
-tregister($05000002),
-tregister($05000003)
+tregister($0419001F),
+tregister($041a001F),
+tregister($041b001F),
+tregister($041c001F),
+tregister($041d001F),
+tregister($041e001F),
+tregister($041f001F)

compiler/aarch64/ra64rni.inc

@@ -66,231 +66,583 @@
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compiler/aarch64/ra64sri.inc

@@ -1,234 +1,586 @@
 { don't edit, this file is generated from a64reg.dat }
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compiler/aarch64/ra64sta.inc

@@ -66,6 +66,18 @@
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compiler/aarch64/ra64std.inc

@@ -66,231 +66,583 @@
 'xzr',
 'wsp',
 'sp',
+'nzcv',
+'fpcr',
+'fpsr',
+'tpidr_el0',
 'b0',
 'h0',
 's0',
 'd0',
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+'v0',
+'v0.b',
+'v0.h',
+'v0.s',
+'v0.d',
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+'v0.4h',
+'v0.8h',
+'v0.2s',
+'v0.4s',
+'v0.1d',
+'v0.2d',
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+'v1',
+'v1.b',
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+'v1.d',
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+'v1.4h',
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+'v1.2s',
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+'v1.1d',
+'v1.2d',
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+'v2',
+'v2.b',
+'v2.h',
+'v2.s',
+'v2.d',
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+'v2.4h',
+'v2.8h',
+'v2.2s',
+'v2.4s',
+'v2.1d',
+'v2.2d',
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+'v3',
+'v3.b',
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+'v3.s',
+'v3.d',
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+'v3.4h',
+'v3.8h',
+'v3.2s',
+'v3.4s',
+'v3.1d',
+'v3.2d',
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 'h4',
 's4',
 'd4',
 'q4',
+'v4',
+'v4.b',
+'v4.h',
+'v4.s',
+'v4.d',
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+'v4.4h',
+'v4.8h',
+'v4.2s',
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+'v4.1d',
+'v4.2d',
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+'v5',
+'v5.b',
+'v5.h',
+'v5.s',
+'v5.d',
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+'v5.4h',
+'v5.8h',
+'v5.2s',
+'v5.4s',
+'v5.1d',
+'v5.2d',
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+'v6',
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+'v6.1d',
+'v6.2d',
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+'v7.s',
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+'v7.4h',
+'v7.8h',
+'v7.2s',
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+'v7.1d',
+'v7.2d',
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+'v8',
+'v8.b',
+'v8.h',
+'v8.s',
+'v8.d',
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+'v8.4h',
+'v8.8h',
+'v8.2s',
+'v8.4s',
+'v8.1d',
+'v8.2d',
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 'd9',
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+'v9',
+'v9.b',
+'v9.h',
+'v9.s',
+'v9.d',
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+'v9.4h',
+'v9.8h',
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+'v9.1d',
+'v9.2d',
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+'v10',
+'v10.b',
+'v10.h',
+'v10.s',
+'v10.d',
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+'v10.4h',
+'v10.8h',
+'v10.2s',
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+'v10.1d',
+'v10.2d',
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 'h11',
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 'd11',
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+'v11',
+'v11.b',
+'v11.h',
+'v11.s',
+'v11.d',
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+'v11.4h',
+'v11.8h',
+'v11.2s',
+'v11.4s',
+'v11.1d',
+'v11.2d',
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 'd12',
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+'v12',
+'v12.b',
+'v12.h',
+'v12.s',
+'v12.d',
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+'v12.4h',
+'v12.8h',
+'v12.2s',
+'v12.4s',
+'v12.1d',
+'v12.2d',
 'b13',
 'h13',
 's13',
 'd13',
 'q13',
+'v13',
+'v13.b',
+'v13.h',
+'v13.s',
+'v13.d',
 'v13.8b',
 'v13.16b',
+'v13.4h',
+'v13.8h',
+'v13.2s',
+'v13.4s',
+'v13.1d',
+'v13.2d',
 'b14',
 'h14',
 's14',
 'd14',
 'q14',
+'v14',
+'v14.b',
+'v14.h',
+'v14.s',
+'v14.d',
 'v14.8b',
 'v14.16b',
+'v14.4h',
+'v14.8h',
+'v14.2s',
+'v14.4s',
+'v14.1d',
+'v14.2d',
 'b15',
 'h15',
 's15',
 'd15',
 'q15',
+'v15',
+'v15.b',
+'v15.h',
+'v15.s',
+'v15.d',
 'v15.8b',
 'v15.16b',
+'v15.4h',
+'v15.8h',
+'v15.2s',
+'v15.4s',
+'v15.1d',
+'v15.2d',
 'b16',
 'h16',
 's16',
 'd16',
 'q16',
+'v16',
+'v16.b',
+'v16.h',
+'v16.s',
+'v16.d',
 'v16.8b',
 'v16.16b',
+'v16.4h',
+'v16.8h',
+'v16.2s',
+'v16.4s',
+'v16.1d',
+'v16.2d',
 'b17',
 'h17',
 's17',
 'd17',
 'q17',
+'v17',
+'v17.b',
+'v17.h',
+'v17.s',
+'v17.d',
 'v17.8b',
 'v17.16b',
+'v17.4h',
+'v17.8h',
+'v17.2s',
+'v17.4s',
+'v17.1d',
+'v17.2d',
 'b18',
 'h18',
 's18',
 'd18',
 'q18',
+'v18',
+'v18.b',
+'v18.h',
+'v18.s',
+'v18.d',
 'v18.8b',
 'v18.16b',
+'v18.4h',
+'v18.8h',
+'v18.2s',
+'v18.4s',
+'v18.1d',
+'v18.2d',
 'b19',
 'h19',
 's19',
 'd19',
 'q19',
+'v19',
+'v19.b',
+'v19.h',
+'v19.s',
+'v19.d',
 'v19.8b',
 'v19.16b',
+'v19.4h',
+'v19.8h',
+'v19.2s',
+'v19.4s',
+'v19.1d',
+'v19.2d',
 'b20',
 'h20',
 's20',
 'd20',
 'q20',
+'v20',
+'v20.b',
+'v20.h',
+'v20.s',
+'v20.d',
 'v20.8b',
 'v20.16b',
+'v20.4h',
+'v20.8h',
+'v20.2s',
+'v20.4s',
+'v20.1d',
+'v20.2d',
 'b21',
 'h21',
 's21',
 'd21',
 'q21',
+'v21',
+'v21.b',
+'v21.h',
+'v21.s',
+'v21.d',
 'v21.8b',
 'v21.16b',
+'v21.4h',
+'v21.8h',
+'v21.2s',
+'v21.4s',
+'v21.1d',
+'v21.2d',
 'b22',
 'h22',
 's22',
 'd22',
 'q22',
+'v22',
+'v22.b',
+'v22.h',
+'v22.s',
+'v22.d',
 'v22.8b',
 'v22.16b',
+'v22.4h',
+'v22.8h',
+'v22.2s',
+'v22.4s',
+'v22.1d',
+'v22.2d',
 'b23',
 'h23',
 's23',
 'd23',
 'q23',
+'v23',
+'v23.b',
+'v23.h',
+'v23.s',
+'v23.d',
 'v23.8b',
 'v23.16b',
+'v23.4h',
+'v23.8h',
+'v23.2s',
+'v23.4s',
+'v23.1d',
+'v23.2d',
 'b24',
 'h24',
 's24',
 'd24',
 'q24',
+'v24',
+'v24.b',
+'v24.h',
+'v24.s',
+'v24.d',
 'v24.8b',
 'v24.16b',
+'v24.4h',
+'v24.8h',
+'v24.2s',
+'v24.4s',
+'v24.1d',
+'v24.2d',
 'b25',
 'h25',
 's25',
 'd25',
 'q25',
+'v25',
+'v25.b',
+'v25.h',
+'v25.s',
+'v25.d',
 'v25.8b',
 'v25.16b',
+'v25.4h',
+'v25.8h',
+'v25.2s',
+'v25.4s',
+'v25.1d',
+'v25.2d',
 'b26',
 'h26',
 's26',
 'd26',
 'q26',
+'v26',
+'v26.b',
+'v26.h',
+'v26.s',
+'v26.d',
 'v26.8b',
 'v26.16b',
+'v26.4h',
+'v26.8h',
+'v26.2s',
+'v26.4s',
+'v26.1d',
+'v26.2d',
 'b27',
 'h27',
 's27',
 'd27',
 'q27',
+'v27',
+'v27.b',
+'v27.h',
+'v27.s',
+'v27.d',
 'v27.8b',
 'v27.16b',
+'v27.4h',
+'v27.8h',
+'v27.2s',
+'v27.4s',
+'v27.1d',
+'v27.2d',
 'b28',
 'h28',
 's28',
 'd28',
 'q28',
+'v28',
+'v28.b',
+'v28.h',
+'v28.s',
+'v28.d',
 'v28.8b',
 'v28.16b',
+'v28.4h',
+'v28.8h',
+'v28.2s',
+'v28.4s',
+'v28.1d',
+'v28.2d',
 'b29',
 'h29',
 's29',
 'd29',
 'q29',
+'v29',
+'v29.b',
+'v29.h',
+'v29.s',
+'v29.d',
 'v29.8b',
 'v29.16b',
+'v29.4h',
+'v29.8h',
+'v29.2s',
+'v29.4s',
+'v29.1d',
+'v29.2d',
 'b30',
 'h30',
 's30',
 'd30',
 'q30',
+'v30',
+'v30.b',
+'v30.h',
+'v30.s',
+'v30.d',
 'v30.8b',
 'v30.16b',
+'v30.4h',
+'v30.8h',
+'v30.2s',
+'v30.4s',
+'v30.1d',
+'v30.2d',
 'b31',
 'h31',
 's31',
 'd31',
 'q31',
+'v31',
+'v31.b',
+'v31.h',
+'v31.s',
+'v31.d',
 'v31.8b',
 'v31.16b',
-'nzcv',
-'fpcr',
-'fpsr',
-'tpidr_el0'
+'v31.4h',
+'v31.8h',
+'v31.2s',
+'v31.4s',
+'v31.1d',
+'v31.2d'

compiler/aarch64/ra64sup.inc

@@ -66,231 +66,583 @@ RS_WZR = $1F;
 RS_XZR = $1F;
 RS_WSP = $20;
 RS_SP = $20;
+RS_NZCV = $00;
+RS_FPCR = $01;
+RS_FPSR = $02;
+RS_TPIDR_EL0 = $03;
 RS_B0 = $00;
 RS_H0 = $00;
 RS_S0 = $00;
 RS_D0 = $00;
 RS_Q0 = $00;
-RS_V08B = $00;
-RS_V016B = $00;
+RS_V0 = $00;
+RS_V0_B = $00;
+RS_V0_H = $00;
+RS_V0_S = $00;
+RS_V0_D = $00;
+RS_V0_8B = $00;
+RS_V0_16B = $00;
+RS_V0_4H = $00;
+RS_V0_8H = $00;
+RS_V0_2S = $00;
+RS_V0_4S = $00;
+RS_V0_1D = $00;
+RS_V0_2D = $00;
 RS_B1 = $01;
 RS_H1 = $01;
 RS_S1 = $01;
 RS_D1 = $01;
 RS_Q1 = $01;
-RS_V18B = $01;
-RS_V116B = $01;
+RS_V1 = $01;
+RS_V1_B = $01;
+RS_V1_H = $01;
+RS_V1_S = $01;
+RS_V1_D = $01;
+RS_V1_8B = $01;
+RS_V1_16B = $01;
+RS_V1_4H = $01;
+RS_V1_8H = $01;
+RS_V1_2S = $01;
+RS_V1_4S = $01;
+RS_V1_1D = $01;
+RS_V1_2D = $01;
 RS_B2 = $02;
 RS_H2 = $02;
 RS_S2 = $02;
 RS_D2 = $02;
 RS_Q2 = $02;
-RS_V28B = $02;
-RS_V216B = $02;
+RS_V2 = $02;
+RS_V2_B = $02;
+RS_V2_H = $02;
+RS_V2_S = $02;
+RS_V2_D = $02;
+RS_V2_8B = $02;
+RS_V2_16B = $02;
+RS_V2_4H = $02;
+RS_V2_8H = $02;
+RS_V2_2S = $02;
+RS_V2_4S = $02;
+RS_V2_1D = $02;
+RS_V2_2D = $02;
 RS_B3 = $03;
 RS_H3 = $03;
 RS_S3 = $03;
 RS_D3 = $03;
 RS_Q3 = $03;
-RS_V38B = $03;
-RS_V316B = $03;
+RS_V3 = $03;
+RS_V3_B = $03;
+RS_V3_H = $03;
+RS_V3_S = $03;
+RS_V3_D = $03;
+RS_V3_8B = $03;
+RS_V3_16B = $03;
+RS_V3_4H = $03;
+RS_V3_8H = $03;
+RS_V3_2S = $03;
+RS_V3_4S = $03;
+RS_V3_1D = $03;
+RS_V3_2D = $03;
 RS_B4 = $04;
 RS_H4 = $04;
 RS_S4 = $04;
 RS_D4 = $04;
 RS_Q4 = $04;
-RS_V48B = $04;
-RS_V416B = $04;
+RS_V4 = $04;
+RS_V4_B = $04;
+RS_V4_H = $04;
+RS_V4_S = $04;
+RS_V4_D = $04;
+RS_V4_8B = $04;
+RS_V4_16B = $04;
+RS_V4_4H = $04;
+RS_V4_8H = $04;
+RS_V4_2S = $04;
+RS_V4_4S = $04;
+RS_V4_1D = $04;
+RS_V4_2D = $04;
 RS_B5 = $05;
 RS_H5 = $05;
 RS_S5 = $05;
 RS_D5 = $05;
 RS_Q5 = $05;
-RS_V58B = $05;
-RS_V516B = $05;
+RS_V5 = $05;
+RS_V5_B = $05;
+RS_V5_H = $05;
+RS_V5_S = $05;
+RS_V5_D = $05;
+RS_V5_8B = $05;
+RS_V5_16B = $05;
+RS_V5_4H = $05;
+RS_V5_8H = $05;
+RS_V5_2S = $05;
+RS_V5_4S = $05;
+RS_V5_1D = $05;
+RS_V5_2D = $05;
 RS_B6 = $06;
 RS_H6 = $06;
 RS_S6 = $06;
 RS_D6 = $06;
 RS_Q6 = $06;
-RS_V68B = $06;
-RS_V616B = $06;
+RS_V6 = $06;
+RS_V6_B = $06;
+RS_V6_H = $06;
+RS_V6_S = $06;
+RS_V6_D = $06;
+RS_V6_8B = $06;
+RS_V6_16B = $06;
+RS_V6_4H = $06;
+RS_V6_8H = $06;
+RS_V6_2S = $06;
+RS_V6_4S = $06;
+RS_V6_1D = $06;
+RS_V6_2D = $06;
 RS_B7 = $07;
 RS_H7 = $07;
 RS_S7 = $07;
 RS_D7 = $07;
 RS_Q7 = $07;
-RS_V78B = $07;
-RS_V716B = $07;
+RS_V7 = $07;
+RS_V7_B = $07;
+RS_V7_H = $07;
+RS_V7_S = $07;
+RS_V7_D = $07;
+RS_V7_8B = $07;
+RS_V7_16B = $07;
+RS_V7_4H = $07;
+RS_V7_8H = $07;
+RS_V7_2S = $07;
+RS_V7_4S = $07;
+RS_V7_1D = $07;
+RS_V7_2D = $07;
 RS_B8 = $08;
 RS_H8 = $08;
 RS_S8 = $08;
 RS_D8 = $08;
 RS_Q8 = $08;
-RS_V88B = $08;
-RS_V816B = $08;
+RS_V8 = $08;
+RS_V8_B = $08;
+RS_V8_H = $08;
+RS_V8_S = $08;
+RS_V8_D = $08;
+RS_V8_8B = $08;
+RS_V8_16B = $08;
+RS_V8_4H = $08;
+RS_V8_8H = $08;
+RS_V8_2S = $08;
+RS_V8_4S = $08;
+RS_V8_1D = $08;
+RS_V8_2D = $08;
 RS_B9 = $09;
 RS_H9 = $09;
 RS_S9 = $09;
 RS_D9 = $09;
 RS_Q9 = $09;
-RS_V98B = $09;
-RS_V916B = $09;
+RS_V9 = $09;
+RS_V9_B = $09;
+RS_V9_H = $09;
+RS_V9_S = $09;
+RS_V9_D = $09;
+RS_V9_8B = $09;
+RS_V9_16B = $09;
+RS_V9_4H = $09;
+RS_V9_8H = $09;
+RS_V9_2S = $09;
+RS_V9_4S = $09;
+RS_V9_1D = $09;
+RS_V9_2D = $09;
 RS_B10 = $0A;
 RS_H10 = $0A;
 RS_S10 = $0A;
 RS_D10 = $0A;
 RS_Q10 = $0A;
-RS_V108B = $0A;
-RS_V1016B = $0A;
+RS_V10 = $0A;
+RS_V10_B = $0A;
+RS_V10_H = $0A;
+RS_V10_S = $0A;
+RS_V10_D = $0A;
+RS_V10_8B = $0A;
+RS_V10_16B = $0A;
+RS_V10_4H = $0A;
+RS_V10_8H = $0A;
+RS_V10_2S = $0A;
+RS_V10_4S = $0A;
+RS_V10_1D = $0A;
+RS_V10_2D = $0A;
 RS_B11 = $0B;
 RS_H11 = $0B;
 RS_S11 = $0B;
 RS_D11 = $0B;
 RS_Q11 = $0B;
-RS_V118B = $0B;
-RS_V1116B = $0B;
+RS_V11 = $0B;
+RS_V11_B = $0B;
+RS_V11_H = $0B;
+RS_V11_S = $0B;
+RS_V11_D = $0B;
+RS_V11_8B = $0B;
+RS_V11_16B = $0B;
+RS_V11_4H = $0B;
+RS_V11_8H = $0B;
+RS_V11_2S = $0B;
+RS_V11_4S = $0B;
+RS_V11_1D = $0B;
+RS_V11_2D = $0B;
 RS_B12 = $0C;
 RS_H12 = $0C;
 RS_S12 = $0C;
 RS_D12 = $0C;
 RS_Q12 = $0C;
-RS_V128B = $0C;
-RS_V1216B = $0C;
+RS_V12 = $0C;
+RS_V12_B = $0C;
+RS_V12_H = $0C;
+RS_V12_S = $0C;
+RS_V12_D = $0C;
+RS_V12_8B = $0C;
+RS_V12_16B = $0C;
+RS_V12_4H = $0C;
+RS_V12_8H = $0C;
+RS_V12_2S = $0C;
+RS_V12_4S = $0C;
+RS_V12_1D = $0C;
+RS_V12_2D = $0C;
 RS_B13 = $0D;
 RS_H13 = $0D;
 RS_S13 = $0D;
 RS_D13 = $0D;
 RS_Q13 = $0D;
-RS_V138B = $0D;
-RS_V1316B = $0D;
+RS_V13 = $0D;
+RS_V13_B = $0D;
+RS_V13_H = $0D;
+RS_V13_S = $0D;
+RS_V13_D = $0D;
+RS_V13_8B = $0D;
+RS_V13_16B = $0D;
+RS_V13_4H = $0D;
+RS_V13_8H = $0D;
+RS_V13_2S = $0D;
+RS_V13_4S = $0D;
+RS_V13_1D = $0D;
+RS_V13_2D = $0D;
 RS_B14 = $0E;
 RS_H14 = $0E;
 RS_S14 = $0E;
 RS_D14 = $0E;
 RS_Q14 = $0E;
-RS_V148B = $0E;
-RS_V1416B = $0E;
+RS_V14 = $0E;
+RS_V14_B = $0E;
+RS_V14_H = $0E;
+RS_V14_S = $0E;
+RS_V14_D = $0E;
+RS_V14_8B = $0E;
+RS_V14_16B = $0E;
+RS_V14_4H = $0E;
+RS_V14_8H = $0E;
+RS_V14_2S = $0E;
+RS_V14_4S = $0E;
+RS_V14_1D = $0E;
+RS_V14_2D = $0E;
 RS_B15 = $0F;
 RS_H15 = $0F;
 RS_S15 = $0F;
 RS_D15 = $0F;
 RS_Q15 = $0F;
-RS_V158B = $0F;
-RS_V1516B = $0F;
+RS_V15 = $0F;
+RS_V15_B = $0F;
+RS_V15_H = $0F;
+RS_V15_S = $0F;
+RS_V15_D = $0F;
+RS_V15_8B = $0F;
+RS_V15_16B = $0F;
+RS_V15_4H = $0F;
+RS_V15_8H = $0F;
+RS_V15_2S = $0F;
+RS_V15_4S = $0F;
+RS_V15_1D = $0F;
+RS_V15_2D = $0F;
 RS_B16 = $10;
 RS_H16 = $10;
 RS_S16 = $10;
 RS_D16 = $10;
 RS_Q16 = $10;
-RS_V168B = $10;
-RS_V1616B = $10;
+RS_V16 = $10;
+RS_V16_B = $10;
+RS_V16_H = $10;
+RS_V16_S = $10;
+RS_V16_D = $10;
+RS_V16_8B = $10;
+RS_V16_16B = $10;
+RS_V16_4H = $10;
+RS_V16_8H = $10;
+RS_V16_2S = $10;
+RS_V16_4S = $10;
+RS_V16_1D = $10;
+RS_V16_2D = $10;
 RS_B17 = $11;
 RS_H17 = $11;
 RS_S17 = $11;
 RS_D17 = $11;
 RS_Q17 = $11;
-RS_V178B = $11;
-RS_V1716B = $11;
+RS_V17 = $11;
+RS_V17_B = $11;
+RS_V17_H = $11;
+RS_V17_S = $11;
+RS_V17_D = $11;
+RS_V17_8B = $11;
+RS_V17_16B = $11;
+RS_V17_4H = $11;
+RS_V17_8H = $11;
+RS_V17_2S = $11;
+RS_V17_4S = $11;
+RS_V17_1D = $11;
+RS_V17_2D = $11;
 RS_B18 = $12;
 RS_H18 = $12;
 RS_S18 = $12;
 RS_D18 = $12;
 RS_Q18 = $12;
-RS_V188B = $12;
-RS_V1816B = $12;
+RS_V18 = $12;
+RS_V18_B = $12;
+RS_V18_H = $12;
+RS_V18_S = $12;
+RS_V18_D = $12;
+RS_V18_8B = $12;
+RS_V18_16B = $12;
+RS_V18_4H = $12;
+RS_V18_8H = $12;
+RS_V18_2S = $12;
+RS_V18_4S = $12;
+RS_V18_1D = $12;
+RS_V18_2D = $12;
 RS_B19 = $13;
 RS_H19 = $13;
 RS_S19 = $13;
 RS_D19 = $13;
 RS_Q19 = $13;
-RS_V198B = $13;
-RS_V1916B = $13;
+RS_V19 = $13;
+RS_V19_B = $13;
+RS_V19_H = $13;
+RS_V19_S = $13;
+RS_V19_D = $13;
+RS_V19_8B = $13;
+RS_V19_16B = $13;
+RS_V19_4H = $13;
+RS_V19_8H = $13;
+RS_V19_2S = $13;
+RS_V19_4S = $13;
+RS_V19_1D = $13;
+RS_V19_2D = $13;
 RS_B20 = $14;
 RS_H20 = $14;
 RS_S20 = $14;
 RS_D20 = $14;
 RS_Q20 = $14;
-RS_V208B = $14;
-RS_V2016B = $14;
+RS_V20 = $14;
+RS_V20_B = $14;
+RS_V20_H = $14;
+RS_V20_S = $14;
+RS_V20_D = $14;
+RS_V20_8B = $14;
+RS_V20_16B = $14;
+RS_V20_4H = $14;
+RS_V20_8H = $14;
+RS_V20_2S = $14;
+RS_V20_4S = $14;
+RS_V20_1D = $14;
+RS_V20_2D = $14;
 RS_B21 = $15;
 RS_H21 = $15;
 RS_S21 = $15;
 RS_D21 = $15;
 RS_Q21 = $15;
-RS_V218B = $15;
-RS_V2116B = $15;
+RS_V21 = $15;
+RS_V21_B = $15;
+RS_V21_H = $15;
+RS_V21_S = $15;
+RS_V21_D = $15;
+RS_V21_8B = $15;
+RS_V21_16B = $15;
+RS_V21_4H = $15;
+RS_V21_8H = $15;
+RS_V21_2S = $15;
+RS_V21_4S = $15;
+RS_V21_1D = $15;
+RS_V21_2D = $15;
 RS_B22 = $16;
 RS_H22 = $16;
 RS_S22 = $16;
 RS_D22 = $16;
 RS_Q22 = $16;
-RS_V228B = $16;
-RS_V2216B = $16;
+RS_V22 = $16;
+RS_V22_B = $16;
+RS_V22_H = $16;
+RS_V22_S = $16;
+RS_V22_D = $16;
+RS_V22_8B = $16;
+RS_V22_16B = $16;
+RS_V22_4H = $16;
+RS_V22_8H = $16;
+RS_V22_2S = $16;
+RS_V22_4S = $16;
+RS_V22_1D = $16;
+RS_V22_2D = $16;
 RS_B23 = $17;
 RS_H23 = $17;
 RS_S23 = $17;
 RS_D23 = $17;
 RS_Q23 = $17;
-RS_V238B = $17;
-RS_V2316B = $17;
+RS_V23 = $17;
+RS_V23_B = $17;
+RS_V23_H = $17;
+RS_V23_S = $17;
+RS_V23_D = $17;
+RS_V23_8B = $17;
+RS_V23_16B = $17;
+RS_V23_4H = $17;
+RS_V23_8H = $17;
+RS_V23_2S = $17;
+RS_V23_4S = $17;
+RS_V23_1D = $17;
+RS_V23_2D = $17;
 RS_B24 = $18;
 RS_H24 = $18;
 RS_S24 = $18;
 RS_D24 = $18;
 RS_Q24 = $18;
-RS_V248B = $18;
-RS_V2416B = $18;
+RS_V24 = $18;
+RS_V24_B = $18;
+RS_V24_H = $18;
+RS_V24_S = $18;
+RS_V24_D = $18;
+RS_V24_8B = $18;
+RS_V24_16B = $18;
+RS_V24_4H = $18;
+RS_V24_8H = $18;
+RS_V24_2S = $18;
+RS_V24_4S = $18;
+RS_V24_1D = $18;
+RS_V24_2D = $18;
 RS_B25 = $19;
 RS_H25 = $19;
 RS_S25 = $19;
 RS_D25 = $19;
 RS_Q25 = $19;
-RS_V258B = $19;
-RS_V2516B = $19;
+RS_V25 = $19;
+RS_V25_B = $19;
+RS_V25_H = $19;
+RS_V25_S = $19;
+RS_V25_D = $19;
+RS_V25_8B = $19;
+RS_V25_16B = $19;
+RS_V25_4H = $19;
+RS_V25_8H = $19;
+RS_V25_2S = $19;
+RS_V25_4S = $19;
+RS_V25_1D = $19;
+RS_V25_2D = $19;
 RS_B26 = $1A;
 RS_H26 = $1A;
 RS_S26 = $1A;
 RS_D26 = $1A;
 RS_Q26 = $1A;
-RS_V268B = $1A;
-RS_V2616B = $1A;
+RS_V26 = $1A;
+RS_V26_B = $1A;
+RS_V26_H = $1A;
+RS_V26_S = $1A;
+RS_V26_D = $1A;
+RS_V26_8B = $1A;
+RS_V26_16B = $1A;
+RS_V26_4H = $1A;
+RS_V26_8H = $1A;
+RS_V26_2S = $1A;
+RS_V26_4S = $1A;
+RS_V26_1D = $1A;
+RS_V26_2D = $1A;
 RS_B27 = $1B;
 RS_H27 = $1B;
 RS_S27 = $1B;
 RS_D27 = $1B;
 RS_Q27 = $1B;
-RS_V278B = $1B;
-RS_V2716B = $1B;
+RS_V27 = $1B;
+RS_V27_B = $1B;
+RS_V27_H = $1B;
+RS_V27_S = $1B;
+RS_V27_D = $1B;
+RS_V27_8B = $1B;
+RS_V27_16B = $1B;
+RS_V27_4H = $1B;
+RS_V27_8H = $1B;
+RS_V27_2S = $1B;
+RS_V27_4S = $1B;
+RS_V27_1D = $1B;
+RS_V27_2D = $1B;
 RS_B28 = $1C;
 RS_H28 = $1C;
 RS_S28 = $1C;
 RS_D28 = $1C;
 RS_Q28 = $1C;
-RS_V288B = $1C;
-RS_V2816B = $1C;
+RS_V28 = $1C;
+RS_V28_B = $1C;
+RS_V28_H = $1C;
+RS_V28_S = $1C;
+RS_V28_D = $1C;
+RS_V28_8B = $1C;
+RS_V28_16B = $1C;
+RS_V28_4H = $1C;
+RS_V28_8H = $1C;
+RS_V28_2S = $1C;
+RS_V28_4S = $1C;
+RS_V28_1D = $1C;
+RS_V28_2D = $1C;
 RS_B29 = $1D;
 RS_H29 = $1D;
 RS_S29 = $1D;
 RS_D29 = $1D;
 RS_Q29 = $1D;
-RS_V298B = $1D;
-RS_V2916B = $1D;
+RS_V29 = $1D;
+RS_V29_B = $1D;
+RS_V29_H = $1D;
+RS_V29_S = $1D;
+RS_V29_D = $1D;
+RS_V29_8B = $1D;
+RS_V29_16B = $1D;
+RS_V29_4H = $1D;
+RS_V29_8H = $1D;
+RS_V29_2S = $1D;
+RS_V29_4S = $1D;
+RS_V29_1D = $1D;
+RS_V29_2D = $1D;
 RS_B30 = $1E;
 RS_H30 = $1E;
 RS_S30 = $1E;
 RS_D30 = $1E;
 RS_Q30 = $1E;
-RS_V308B = $1E;
-RS_V3016B = $1E;
+RS_V30 = $1E;
+RS_V30_B = $1E;
+RS_V30_H = $1E;
+RS_V30_S = $1E;
+RS_V30_D = $1E;
+RS_V30_8B = $1E;
+RS_V30_16B = $1E;
+RS_V30_4H = $1E;
+RS_V30_8H = $1E;
+RS_V30_2S = $1E;
+RS_V30_4S = $1E;
+RS_V30_1D = $1E;
+RS_V30_2D = $1E;
 RS_B31 = $1F;
 RS_H31 = $1F;
 RS_S31 = $1F;
 RS_D31 = $1F;
 RS_Q31 = $1F;
-RS_V318B = $1F;
-RS_V3116B = $1F;
-RS_NZCV = $00;
-RS_FPCR = $01;
-RS_FPSR = $02;
-RS_TPIDR_EL0 = $03;
+RS_V31 = $1F;
+RS_V31_B = $1F;
+RS_V31_H = $1F;
+RS_V31_S = $1F;
+RS_V31_D = $1F;
+RS_V31_8B = $1F;
+RS_V31_16B = $1F;
+RS_V31_4H = $1F;
+RS_V31_8H = $1F;
+RS_V31_2S = $1F;
+RS_V31_4S = $1F;
+RS_V31_1D = $1F;
+RS_V31_2D = $1F;

compiler/aarch64/racpu.pas

@@ -69,9 +69,16 @@ unit racpu;
           internalerror(2014122001);
         if (ops=1) and (operands[1].opr.typ=OPR_REFERENCE) then
           exit(OS_NO);
-        if operands[1].opr.typ<>OPR_REGISTER then
-          internalerror(2014122002);
-        result:=reg_cgsize(operands[1].opr.reg);
+        case operands[1].opr.typ of
+          OPR_REGISTER:
+            result:=reg_cgsize(operands[1].opr.reg);
+          OPR_INDEXEDREG:
+            result:=reg_cgsize(operands[1].opr.indexedreg);
+          OPR_REGSET:
+            result:=OS_NO;
+          else
+           internalerror(2014122002);
+        end;
         { a 32 bit integer register could actually be 16 or 8 bit }
         if result=OS_32 then
           case oppostfix of

compiler/aarch64/racpugas.pas

@@ -29,7 +29,7 @@ Unit racpugas;
     uses
       raatt,racpu,
       aasmtai,
-      cpubase;
+      cgbase,cpubase;
 
     type
 
@@ -37,12 +37,14 @@ Unit racpugas;
 
       taarch64attreader = class(tattreader)
         actoppostfix : TOpPostfix;
+        actinsmmsubreg : TSubRegister;
         actsehdirective : TAsmSehDirective;
         function is_asmopcode(const s: string):boolean;override;
         function is_register(const s:string):boolean;override;
         function is_targetdirective(const s: string): boolean;override;
         procedure handleopcode;override;
         procedure handletargetdirective; override;
+       protected
         procedure BuildReference(oper: taarch64operand; is64bit: boolean);
         procedure BuildOperand(oper: taarch64operand; is64bit: boolean);
         function TryBuildShifterOp(instr: taarch64instruction; opnr: longint) : boolean;
@@ -50,6 +52,8 @@ Unit racpugas;
         procedure ReadSym(oper: taarch64operand; is64bit: boolean);
         procedure ConvertCalljmp(instr: taarch64instruction);
         function ToConditionCode(const hs: string; is_operand: boolean): tasmcond;
+        function ParseArrangementSpecifier(const hs: string): TSubRegister;
+        function ParseRegIndex(const hs: string): byte;
       end;
 
 
@@ -65,7 +69,7 @@ Unit racpugas;
       symconst,symsym,symdef,
       procinfo,
       rabase,rautils,
-      cgbase,cgutils,paramgr;
+      cgutils,paramgr;
 
 
     function taarch64attreader.is_register(const s:string):boolean;
@@ -76,9 +80,10 @@ Unit racpugas;
         end;
 
       const
-        extraregs : array[0..3] of treg2str = (
+        extraregs : array[0..4] of treg2str = (
           (name: 'FP' ; reg: NR_FP),
           (name: 'LR' ; reg: NR_LR),
+          (name: 'XR' ; reg: NR_XR),
           (name: 'IP0'; reg: NR_IP0),
           (name: 'IP1'; reg: NR_IP1));
 
@@ -88,9 +93,9 @@ Unit racpugas;
       begin
         result:=inherited is_register(s);
         { reg found?
-          possible aliases are always 2 or 3 chars
+          possible aliases are always 2 chars
         }
-        if result or not(length(s) in [2,3]) then
+        if result or not(length(s) in [2]) then
           exit;
         for i:=low(extraregs) to high(extraregs) do
           begin
@@ -577,6 +582,50 @@ Unit racpugas;
       end;
 
 
+    function taarch64attreader.ParseArrangementSpecifier(const hs: string): TSubRegister;
+{$push}{$j-}
+      const
+        arrangements: array[R_SUBMM8B..R_SUBMM2D] of string[4] =
+          ('.8B','.16B','.4H','.8H','.2S','.4S','.1D','.2D');
+{$pop}
+      begin
+        if length(hs)>2 then
+          begin
+            for result:=low(arrangements) to high(arrangements) do
+              if hs=arrangements[result] then
+                exit;
+            result:=R_SUBNONE;
+          end
+        else
+          case hs of
+            '.B': result:=R_SUBMMB1;
+            '.H': result:=R_SUBMMH1;
+            '.S': result:=R_SUBMMS1;
+            '.D': result:=R_SUBMMD1;
+            else
+              result:=R_SUBNONE;
+          end
+      end;
+
+
+    function taarch64attreader.ParseRegIndex(const hs: string): byte;
+      var
+        b: cardinal;
+        error: longint;
+      begin
+        b:=0;
+        val(hs,b,error);
+        if (error<>0) then
+          Message(asmr_e_syn_constant)
+        else if b > 31 then
+          begin
+            Message(asmr_e_constant_out_of_bounds);
+            b:=0;
+          end;
+        result:=b;
+      end;
+
+
     Procedure taarch64attreader.BuildOperand(oper: taarch64operand; is64bit: boolean);
       var
         expr: string;
@@ -723,11 +772,50 @@ Unit racpugas;
             end; { end case }
           end;
 
+      function parsereg: tregister;
+         var
+           subreg: tsubregister;
+        begin
+          result:=actasmregister;
+          Consume(AS_REGISTER);
+          if (actasmtoken=AS_ID) and
+             (actasmpattern[1]='.') then
+            begin
+              subreg:=ParseArrangementSpecifier(upper(actasmpattern));
+              if (subreg<>R_SUBNONE) and
+                 (getregtype(result)=R_MMREGISTER) and
+                 ((actinsmmsubreg=R_SUBNONE) or
+                  (actinsmmsubreg=subreg)) then
+                begin
+                  setsubreg(result,subreg);
+                  { they all have to be the same }
+                  actinsmmsubreg:=subreg;
+                end
+              else
+                Message1(asmr_e_invalid_arrangement,actasmpattern);
+              Consume(AS_ID);
+            end
+          else if (getregtype(result)=R_MMREGISTER) then
+            begin
+              if actinsmmsubreg<>R_SUBNONE then
+                begin
+                  if (getsubreg(result)=R_SUBNONE) or
+                     (getsubreg(result)=actinsmmsubreg) then
+                    setsubreg(result,actinsmmsubreg)
+                  else
+                     Message1(asmr_e_invalid_arrangement,actasmpattern);
+                end
+              else if getsubreg(result)=R_SUBNONE then
+                { Vxx without an arrangement is invalid, use Qxx to specify the entire 128 bits}
+                Message1(asmr_e_invalid_arrangement,'');
+            end;
+        end;
 
       var
         tempreg: tregister;
         hl: tasmlabel;
         icond: tasmcond;
+        regindex: byte;
       Begin
         expr:='';
         case actasmtoken of
@@ -737,6 +825,35 @@ Unit racpugas;
               BuildReference(oper,is64bit);
             end;
 
+          AS_LSBRACKET: { register set }
+            begin
+              consume(AS_LSBRACKET);
+              oper.opr.typ:=OPR_REGSET;
+              oper.opr.basereg:=parsereg;
+              oper.opr.nregs:=1;
+              while (oper.opr.nregs<4) and
+                    (actasmtoken=AS_COMMA) do
+                begin
+                  consume(AS_COMMA);
+                  tempreg:=parsereg;
+                  if getsupreg(tempreg)<>((getsupreg(oper.opr.basereg)+oper.opr.nregs) mod 32) then
+                    Message(asmr_e_a64_invalid_regset);
+                  inc(oper.opr.nregs);
+                end;
+              consume(AS_RSBRACKET);
+              if actasmtoken=AS_LBRACKET then
+                begin
+                  consume(AS_LBRACKET);
+                  oper.opr.regsetindex:=ParseRegIndex(actasmpattern);
+                  consume(AS_INTNUM);
+                  consume(AS_RBRACKET);
+                end
+              else
+                oper.opr.regsetindex:=255;
+              if not(actasmtoken in [AS_END,AS_SEPARATOR,AS_COMMA]) then
+                Message(asmr_e_syn_operand);
+            end;
+
           AS_HASH: { Constant expression  }
             Begin
               Consume(AS_HASH);
@@ -859,7 +976,7 @@ Unit racpugas;
                        OPR_REFERENCE :
                          inc(oper.opr.ref.offset,l);
                        else
-                         internalerror(200309202);
+                         internalerror(2003092005);
                      end;
                    end
                end;
@@ -872,14 +989,31 @@ Unit racpugas;
           AS_REGISTER:
             Begin
               { save the type of register used. }
-              tempreg:=actasmregister;
-              Consume(AS_REGISTER);
-              if (actasmtoken in [AS_end,AS_SEPARATOR,AS_COMMA]) then
-                Begin
-                  if not (oper.opr.typ in [OPR_NONE,OPR_REGISTER]) then
+              tempreg:=parsereg;
+              regindex:=255;
+              if (getregtype(tempreg)=R_MMREGISTER) and
+                 (actasmtoken=AS_LBRACKET) then
+                begin
+                  consume(AS_LBRACKET);
+                  regindex:=ParseRegIndex(actasmpattern);
+                  consume(AS_INTNUM);
+                  consume(AS_RBRACKET);
+                end;
+              if actasmtoken in [AS_END,AS_SEPARATOR,AS_COMMA] then
+                begin
+                  if (oper.opr.typ<>OPR_NONE) then
                     Message(asmr_e_invalid_operand_type);
-                  oper.opr.typ:=OPR_REGISTER;
-                  oper.opr.reg:=tempreg;
+                  if regindex=255 then
+                    begin
+                      oper.opr.typ:=OPR_REGISTER;
+                      oper.opr.reg:=tempreg;
+                    end
+                  else
+                    begin
+                      oper.opr.typ:=OPR_INDEXEDREG;
+                      oper.opr.indexedreg:=tempreg;
+                      oper.opr.regindex:=regindex;
+                    end;
                 end
               else
                 Message(asmr_e_syn_operand);
@@ -985,6 +1119,13 @@ Unit racpugas;
           PF_B,PF_H,PF_W,
           PF_S);
 
+                      { store replicate }
+        ldst14: array[boolean,boolean,'1'..'4'] of tasmop =
+          (((A_LD1,A_LD2,A_LD3,A_LD4),
+            (A_LD1R,A_LD2R,A_LD3R,A_LD4R)),
+           ((A_ST1,A_ST2,A_ST3,A_ST4),
+            (A_NONE,A_NONE,A_NONE,A_NONE)));
+
       var
         j  : longint;
         hs : string;
@@ -1011,6 +1152,29 @@ Unit racpugas;
             exit;
           end;
 
+        (* ldN(r)/stN.size ? (shorthand for "ldN(r)/stN { Vx.size, Vy.size } ..."
+          supported by clang and possibly gas *)
+        actinsmmsubreg:=R_SUBNONE;
+        if (length(s)>=5) and
+           (((hs[1]='L') and
+             (hs[2]='D')) or
+            ((hs[1]='S') and
+             (hs[2]='T'))) and
+           (hs[3] in ['1'..'4']) and
+           ((hs[4]='.') or
+            ((hs[4]='R') and
+             (hs[5]='.'))) then
+          begin
+            actinsmmsubreg:=ParseArrangementSpecifier(copy(hs,4+ord(hs[4]='R'),255));
+            if actinsmmsubreg=R_SUBNONE then
+              exit;
+            actopcode:=ldst14[hs[1]='S',hs[4]='R',hs[3]];
+            actasmtoken:=AS_OPCODE;
+            if actopcode<>A_NONE then
+              is_asmopcode:=true;
+            exit;
+          end;
+
         maxlen:=max(length(hs),7);
         actopcode:=A_NONE;
         for j:=maxlen downto 1 do

compiler/aasmbase.pas

@@ -313,7 +313,7 @@ implementation
             Delete(Result,(Length(Result)-charstoremove) div 2,charstoremove);
             Result:='_'+target_asm.dollarsign+'CRC'+hexstr(crc,8)+Result;
             if Length(Result)>target_asm.labelmaxlen then
-              Internalerror(2020042501);
+              Internalerror(2020042502);
           end;
       end;
 

compiler/aasmcnst.pas

@@ -155,7 +155,7 @@ type
     private
      fnextfieldname: TIDString;
      function getcuroffset: asizeint;
-     procedure setnextfieldname(AValue: TIDString);
+     procedure setnextfieldname(const AValue: TIDString);
     protected
      { type of the aggregate }
      fdef: tdef;
@@ -217,7 +217,7 @@ type
     private
      function getcurragginfo: taggregateinformation;
      procedure set_next_field(AValue: tfieldvarsym);
-     procedure set_next_field_name(AValue: TIDString);
+     procedure set_next_field_name(const AValue: TIDString);
     protected
      { temporary list in which all data is collected }
      fasmlist: tasmlist;
@@ -538,7 +538,7 @@ implementation
       end;
 
 
-    procedure taggregateinformation.setnextfieldname(AValue: TIDString);
+    procedure taggregateinformation.setnextfieldname(const AValue: TIDString);
       begin
         if (fnextfieldname<>'') or
            not anonrecord then
@@ -862,7 +862,7 @@ implementation
      end;
 
 
-    procedure ttai_typedconstbuilder.set_next_field_name(AValue: TIDString);
+    procedure ttai_typedconstbuilder.set_next_field_name(const AValue: TIDString);
       var
         info: taggregateinformation;
       begin
@@ -1312,7 +1312,7 @@ implementation
        else if (assigned(finternal_data_asmlist) and
            (list<>finternal_data_asmlist)) or
            not assigned(list) then
-         internalerror(2015032101);
+         internalerror(2015032102);
        finternal_data_asmlist:=list;
        if not assigned(l) then
          l:=get_internal_data_section_internal_label;

compiler/aasmtai.pas

@@ -243,15 +243,18 @@ interface
       toptype=(top_none,top_reg,top_ref,top_const,top_bool,top_local
 {$ifdef arm}
        { ARM only }
-       ,top_regset
        ,top_modeflags
        ,top_specialreg
 {$endif arm}
 {$if defined(arm) or defined(aarch64)}
+       ,top_regset
        ,top_conditioncode
        ,top_shifterop
        ,top_realconst
 {$endif defined(arm) or defined(aarch64)}
+{$ifdef aarch64}
+       ,top_indexedreg
+{$endif}
 {$ifdef m68k}
        { m68k only }
        ,top_regset
@@ -479,6 +482,10 @@ interface
             top_conditioncode : (cc : TAsmCond);
             top_realconst : (val_real:bestreal);
         {$endif defined(arm) or defined(aarch64)}
+        {$ifdef aarch64}
+            top_regset : (basereg: tregister; nregs, regsetindex: byte);
+            top_indexedreg : (indexedreg: tregister; regindex: byte);
+        {$endif}
         {$ifdef m68k}
             top_regset : (dataregset,addrregset,fpuregset: tcpuregisterset);
             top_regpair : (reghi,reglo: tregister);
@@ -702,6 +709,7 @@ interface
           constructor Create_rel_sym_offset(_typ : taiconst_type; _sym,_endsym : tasmsymbol; _ofs : int64);
           constructor Create_rva_sym(_sym:tasmsymbol);
           constructor Createname(const name:string;ofs:asizeint);
+          constructor Createname_rel(const name, endname: string);
           constructor Createname(const name:string;_symtyp:Tasmsymtype;ofs:asizeint);
           constructor Create_type_name(_typ:taiconst_type;const name:string;ofs:asizeint);
           constructor Create_type_name(_typ:taiconst_type;const name:string;_symtyp:Tasmsymtype;ofs:asizeint);
@@ -1877,6 +1885,13 @@ implementation
       end;
 
 
+    constructor tai_const.Createname_rel(const name,endname:string);
+      begin
+         self.create_sym_offset(current_asmdata.RefAsmSymbol(name,AT_NONE),0);
+         endsym:=current_asmdata.RefAsmSymbol(endname,AT_NONE)
+      end;
+
+
     constructor tai_const.Create_type_name(_typ:taiconst_type;const name:string;ofs:asizeint);
       begin
          self.Create_type_name(_typ,name,AT_NONE,ofs);

compiler/aggas.pas

@@ -524,6 +524,7 @@ implementation
                    include(secflags,SF_W);
                end;
            end;
+         system_i386_go32v2,
          system_i386_win32,
          system_x86_64_win64,
          system_i386_wince,

compiler/aopt.pas

@@ -273,28 +273,16 @@ Unit aopt;
     Procedure TAsmOptimizer.Optimize;
       Var
         HP: tai;
-        pass: longint;
       Begin
-        pass:=0;
         BlockStart := tai(AsmL.First);
         pass_1;
         While Assigned(BlockStart) Do
           Begin
             if (cs_opt_peephole in current_settings.optimizerswitches) then
               begin
-                if pass = 0 then
-                  PrePeepHoleOpts;
-                { Peephole optimizations }
+                PrePeepHoleOpts;
                 PeepHoleOptPass1;
-                { Only perform them twice in the first pass }
-                if pass = 0 then
-                  PeepHoleOptPass1;
-              end;
-            { more peephole optimizations }
-            if (cs_opt_peephole in current_settings.optimizerswitches) then
-              begin
                 PeepHoleOptPass2;
-                { if pass = last_pass then }
                 PostPeepHoleOpts;
               end;
             { free memory }

compiler/aoptobj.pas

@@ -1506,6 +1506,8 @@ Unit AoptObj;
 
     procedure TAOptObj.RemoveCurrentP(var p: tai; const hp1: tai); inline;
       begin
+        if (p=hp1) then
+          internalerror(2020120501);
         UpdateUsedRegs(tai(p.Next));
         AsmL.Remove(p);
         p.Free;
@@ -2464,13 +2466,26 @@ Unit AoptObj;
 
 
     procedure TAOptObj.PeepHoleOptPass1;
+      const
+        MaxPasses: array[1..3] of Cardinal = (1, 2, 8);
       var
         p : tai;
         stoploop, FirstInstruction, JumpOptsAvailable: boolean;
+        PassCount, MaxCount: Cardinal;
       begin
         JumpOptsAvailable := CanDoJumpOpts();
 
         StartPoint := BlockStart;
+        PassCount := 0;
+
+        { Determine the maximum number of passes allowed based on the compiler switches }
+        if (cs_opt_level3 in current_settings.optimizerswitches) then
+          { it should never take more than 8 passes, but the limit is finite to protect against faulty optimisations }
+          MaxCount := MaxPasses[3]
+        else if (cs_opt_level2 in current_settings.optimizerswitches) then
+          MaxCount := MaxPasses[2] { The original double run of Pass 1 }
+        else
+          MaxCount := MaxPasses[1];
 
         repeat
           stoploop:=true;
@@ -2523,7 +2538,10 @@ Unit AoptObj;
                 p := tai(UpdateUsedRegsAndOptimize(p).Next);
 
             end;
-        until stoploop or not(cs_opt_level3 in current_settings.optimizerswitches);
+
+          Inc(PassCount);
+
+        until stoploop or (PassCount >= MaxCount);
       end;
 
 

compiler/arm/aasmcpu.pas

@@ -723,7 +723,7 @@ implementation
           R_MMREGISTER :
             result:=taicpu.op_reg_ref(A_VLDR,r,ref);
           else
-            internalerror(200401041);
+            internalerror(2004010415);
         end;
       end;
 
@@ -741,7 +741,7 @@ implementation
           R_MMREGISTER :
             result:=taicpu.op_reg_ref(A_VSTR,r,ref);
           else
-            internalerror(200401041);
+            internalerror(2004010416);
         end;
       end;
 
@@ -925,7 +925,7 @@ implementation
             else
               begin
                 writeln(opcode);
-                internalerror(200403151);
+                internalerror(2004031502);
               end;
           end;
       end;

compiler/arm/agarmgas.pas

@@ -238,7 +238,7 @@ unit agarmgas;
                      else if shiftmode <> SM_None then
                        s:=s+', '+gas_shiftmode2str[shiftmode]+' #'+tostr(shiftimm);
                      if offset<>0 then
-                       Internalerror(2019012601);
+                       Internalerror(2019012602);
                   end
                 else if offset<>0 then
                   s:=s+', #'+tostr(offset);
@@ -426,7 +426,7 @@ unit agarmgas;
                      top_const:
                        s:=s+sep+tostr(taicpu(hp).oper[1]^.val);
                      else
-                       internalerror(200311292);
+                       internalerror(2003112903);
                    end;
                  end
                else

compiler/arm/aoptcpu.pas

@@ -220,11 +220,11 @@ Implementation
     var
       p: taicpu;
     begin
-      p := taicpu(hp);
       Result := false;
       if not ((assigned(hp)) and (hp.typ = ait_instruction)) then
         exit;
 
+      p := taicpu(hp);
       case p.opcode of
         { These operands do not write into a register at all }
         A_CMP, A_CMN, A_TST, A_TEQ, A_B, A_BL, A_BX, A_BLX, A_SWI, A_MSR, A_PLD,
@@ -1284,504 +1284,512 @@ Implementation
 
       { All the optimisations from this point on require GetNextInstructionUsingReg
         to return True }
-      if not (
+      while (
         GetNextInstructionUsingReg(p, hpfar1, taicpu(p).oper[0]^.reg) and
         (hpfar1.typ = ait_instruction)
-      ) then
-        Exit;
+      ) do
+        begin
 
-      { Change the common
-        mov r0, r0, lsr #xxx
-        and r0, r0, #yyy/bic r0, r0, #xxx
+          { Change the common
+            mov r0, r0, lsr #xxx
+            and r0, r0, #yyy/bic r0, r0, #xxx
 
-        and remove the superfluous and/bic if possible
+            and remove the superfluous and/bic if possible
 
-        This could be extended to handle more cases.
-      }
+            This could be extended to handle more cases.
+          }
 
-      { Change
-        mov rx, ry, lsr/ror #xxx
-        uxtb/uxth rz,rx/and rz,rx,0xFF
-        dealloc rx
+          { Change
+            mov rx, ry, lsr/ror #xxx
+            uxtb/uxth rz,rx/and rz,rx,0xFF
+            dealloc rx
 
-        to
+            to
 
-        uxtb/uxth rz,ry,ror #xxx
-      }
-      if (GenerateThumb2Code) and
-         (taicpu(p).ops=3) and
-         (taicpu(p).oper[2]^.typ = top_shifterop) and
-         (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
-         (taicpu(p).oper[2]^.shifterop^.shiftmode in [SM_LSR,SM_ROR]) and
-         RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
-         begin
-           if MatchInstruction(hpfar1, A_UXTB, [C_None], [PF_None]) and
-             (taicpu(hpfar1).ops = 2) and
-             (taicpu(p).oper[2]^.shifterop^.shiftimm in [8,16,24]) and
-             MatchOperand(taicpu(hpfar1).oper[1]^, taicpu(p).oper[0]^.reg) then
-             begin
-               taicpu(hpfar1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
-               taicpu(hpfar1).loadshifterop(2,taicpu(p).oper[2]^.shifterop^);
-               taicpu(hpfar1).oper[2]^.shifterop^.shiftmode:=SM_ROR;
-               taicpu(hpfar1).ops := 3;
-
-               if not Assigned(hp1) then
-                 GetNextInstruction(p,hp1);
-
-               RemoveCurrentP(p, hp1);
-
-               result:=true;
-               exit;
-             end
-           else if MatchInstruction(hpfar1, A_UXTH, [C_None], [PF_None]) and
-             (taicpu(hpfar1).ops=2) and
-             (taicpu(p).oper[2]^.shifterop^.shiftimm in [16]) and
-             MatchOperand(taicpu(hpfar1).oper[1]^, taicpu(p).oper[0]^.reg) then
-             begin
-               taicpu(hpfar1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
-               taicpu(hpfar1).loadshifterop(2,taicpu(p).oper[2]^.shifterop^);
-               taicpu(hpfar1).oper[2]^.shifterop^.shiftmode:=SM_ROR;
-               taicpu(hpfar1).ops := 3;
-
-               if not Assigned(hp1) then
-                 GetNextInstruction(p,hp1);
-
-               RemoveCurrentP(p, hp1);
-
-               result:=true;
-               exit;
-             end
-           else if MatchInstruction(hpfar1, A_AND, [C_None], [PF_None]) and
-             (taicpu(hpfar1).ops = 3) and
-             (taicpu(hpfar1).oper[2]^.typ = top_const) and
-             (taicpu(hpfar1).oper[2]^.val = $FF) and
-             (taicpu(p).oper[2]^.shifterop^.shiftimm in [8,16,24]) and
-             MatchOperand(taicpu(hpfar1).oper[1]^, taicpu(p).oper[0]^.reg) then
+            uxtb/uxth rz,ry,ror #xxx
+          }
+          if (GenerateThumb2Code) and
+             (taicpu(p).ops=3) and
+             (taicpu(p).oper[2]^.typ = top_shifterop) and
+             (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
+             (taicpu(p).oper[2]^.shifterop^.shiftmode in [SM_LSR,SM_ROR]) and
+             RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
              begin
-               taicpu(hpfar1).ops := 3;
-               taicpu(hpfar1).opcode := A_UXTB;
-               taicpu(hpfar1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
-               taicpu(hpfar1).loadshifterop(2,taicpu(p).oper[2]^.shifterop^);
-               taicpu(hpfar1).oper[2]^.shifterop^.shiftmode:=SM_ROR;
-
-               if not Assigned(hp1) then
-                 GetNextInstruction(p,hp1);
-
-               RemoveCurrentP(p, hp1);
-
-               result:=true;
-               exit;
+               if MatchInstruction(hpfar1, A_UXTB, [C_None], [PF_None]) and
+                 (taicpu(hpfar1).ops = 2) and
+                 (taicpu(p).oper[2]^.shifterop^.shiftimm in [8,16,24]) and
+                 MatchOperand(taicpu(hpfar1).oper[1]^, taicpu(p).oper[0]^.reg) then
+                 begin
+                   taicpu(hpfar1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
+                   taicpu(hpfar1).loadshifterop(2,taicpu(p).oper[2]^.shifterop^);
+                   taicpu(hpfar1).oper[2]^.shifterop^.shiftmode:=SM_ROR;
+                   taicpu(hpfar1).ops := 3;
+
+                   if not Assigned(hp1) then
+                     GetNextInstruction(p,hp1);
+
+                   RemoveCurrentP(p, hp1);
+
+                   result:=true;
+                   exit;
+                 end
+               else if MatchInstruction(hpfar1, A_UXTH, [C_None], [PF_None]) and
+                 (taicpu(hpfar1).ops=2) and
+                 (taicpu(p).oper[2]^.shifterop^.shiftimm in [16]) and
+                 MatchOperand(taicpu(hpfar1).oper[1]^, taicpu(p).oper[0]^.reg) then
+                 begin
+                   taicpu(hpfar1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
+                   taicpu(hpfar1).loadshifterop(2,taicpu(p).oper[2]^.shifterop^);
+                   taicpu(hpfar1).oper[2]^.shifterop^.shiftmode:=SM_ROR;
+                   taicpu(hpfar1).ops := 3;
+
+                   if not Assigned(hp1) then
+                     GetNextInstruction(p,hp1);
+
+                   RemoveCurrentP(p, hp1);
+
+                   result:=true;
+                   exit;
+                 end
+               else if MatchInstruction(hpfar1, A_AND, [C_None], [PF_None]) and
+                 (taicpu(hpfar1).ops = 3) and
+                 (taicpu(hpfar1).oper[2]^.typ = top_const) and
+                 (taicpu(hpfar1).oper[2]^.val = $FF) and
+                 (taicpu(p).oper[2]^.shifterop^.shiftimm in [8,16,24]) and
+                 MatchOperand(taicpu(hpfar1).oper[1]^, taicpu(p).oper[0]^.reg) then
+                 begin
+                   taicpu(hpfar1).ops := 3;
+                   taicpu(hpfar1).opcode := A_UXTB;
+                   taicpu(hpfar1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
+                   taicpu(hpfar1).loadshifterop(2,taicpu(p).oper[2]^.shifterop^);
+                   taicpu(hpfar1).oper[2]^.shifterop^.shiftmode:=SM_ROR;
+
+                   if not Assigned(hp1) then
+                     GetNextInstruction(p,hp1);
+
+                   RemoveCurrentP(p, hp1);
+
+                   result:=true;
+                   exit;
+                 end;
              end;
-         end;
 
-      { 2-operald mov optimisations }
-      if (taicpu(p).ops = 2) then
-        begin
-          {
-            This removes the mul from
-            mov rX,0
-            ...
-            mul ...,rX,...
-          }
-          if (taicpu(p).oper[1]^.typ = top_const) then
+          { 2-operald mov optimisations }
+          if (taicpu(p).ops = 2) then
             begin
-(*          if false and
-            (taicpu(p).oper[1]^.val=0) and
-            MatchInstruction(hpfar1, [A_MUL,A_MLA], [taicpu(p).condition], [taicpu(p).oppostfix]) and
-            (((taicpu(hpfar1).oper[1]^.typ=top_reg) and MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^)) or
-             ((taicpu(hpfar1).oper[2]^.typ=top_reg) and MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[2]^))) then
-              begin
-                TransferUsedRegs(TmpUsedRegs);
-                UpdateUsedRegs(TmpUsedRegs, tai(p.next));
-                UpdateUsedRegs(TmpUsedRegs, tai(hpfar1.next));
-                DebugMsg('Peephole Optimization: MovMUL/MLA2Mov0 done', p);
-                if taicpu(hpfar1).opcode=A_MUL then
-                  taicpu(hpfar1).loadconst(1,0)
-                else
-                  taicpu(hpfar1).loadreg(1,taicpu(hpfar1).oper[3]^.reg);
-                taicpu(hpfar1).ops:=2;
-                taicpu(hpfar1).opcode:=A_MOV;
-                if not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,hpfar1,TmpUsedRegs)) then
-                  RemoveCurrentP(p);
-                Result:=true;
-                exit;
-              end
-          else*) if (taicpu(p).oper[1]^.val=0) and
-              MatchInstruction(hpfar1, A_MLA, [taicpu(p).condition], [taicpu(p).oppostfix]) and
-              MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[3]^) then
+              {
+                This removes the mul from
+                mov rX,0
+                ...
+                mul ...,rX,...
+              }
+              if (taicpu(p).oper[1]^.typ = top_const) then
                 begin
-                  TransferUsedRegs(TmpUsedRegs);
-                  UpdateUsedRegs(TmpUsedRegs, tai(p.next));
-                  UpdateUsedRegs(TmpUsedRegs, tai(hpfar1.next));
-                  DebugMsg('Peephole Optimization: MovMLA2MUL 1 done', p);
-                  taicpu(hpfar1).ops:=3;
-                  taicpu(hpfar1).opcode:=A_MUL;
-                  if not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,hpfar1,TmpUsedRegs)) then
-                    begin
+    (*          if false and
+                (taicpu(p).oper[1]^.val=0) and
+                MatchInstruction(hpfar1, [A_MUL,A_MLA], [taicpu(p).condition], [taicpu(p).oppostfix]) and
+                (((taicpu(hpfar1).oper[1]^.typ=top_reg) and MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^)) or
+                 ((taicpu(hpfar1).oper[2]^.typ=top_reg) and MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[2]^))) then
+                  begin
+                    TransferUsedRegs(TmpUsedRegs);
+                    UpdateUsedRegs(TmpUsedRegs, tai(p.next));
+                    UpdateUsedRegs(TmpUsedRegs, tai(hpfar1.next));
+                    DebugMsg('Peephole Optimization: MovMUL/MLA2Mov0 done', p);
+                    if taicpu(hpfar1).opcode=A_MUL then
+                      taicpu(hpfar1).loadconst(1,0)
+                    else
+                      taicpu(hpfar1).loadreg(1,taicpu(hpfar1).oper[3]^.reg);
+                    taicpu(hpfar1).ops:=2;
+                    taicpu(hpfar1).opcode:=A_MOV;
+                    if not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,hpfar1,TmpUsedRegs)) then
                       RemoveCurrentP(p);
-                      Result:=true;
-                    end;
-                  exit;
-                end
-            {
-              This changes the very common
-              mov r0, #0
-              str r0, [...]
-              mov r0, #0
-              str r0, [...]
-
-              and removes all superfluous mov instructions
-            }
-            else if (taicpu(hpfar1).opcode=A_STR) then
-              begin
-                hp1 := hpfar1;
-                while MatchInstruction(hp1, A_STR, [taicpu(p).condition], []) and
-                      MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[0]^) and
-                      GetNextInstruction(hp1, hp2) and
-                      MatchInstruction(hp2, A_MOV, [taicpu(p).condition], [PF_None]) and
-                      (taicpu(hp2).ops = 2) and
-                      MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[0]^) and
-                      MatchOperand(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^) do
+                    Result:=true;
+                    exit;
+                  end
+              else*) if (taicpu(p).oper[1]^.val=0) and
+                  MatchInstruction(hpfar1, A_MLA, [taicpu(p).condition], [taicpu(p).oppostfix]) and
+                  MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[3]^) then
+                    begin
+                      TransferUsedRegs(TmpUsedRegs);
+                      UpdateUsedRegs(TmpUsedRegs, tai(p.next));
+                      UpdateUsedRegs(TmpUsedRegs, tai(hpfar1.next));
+                      DebugMsg('Peephole Optimization: MovMLA2MUL 1 done', p);
+                      taicpu(hpfar1).ops:=3;
+                      taicpu(hpfar1).opcode:=A_MUL;
+                      if not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,hpfar1,TmpUsedRegs)) then
+                        begin
+                          RemoveCurrentP(p);
+                          Result:=true;
+                        end;
+                      exit;
+                    end
+                {
+                  This changes the very common
+                  mov r0, #0
+                  str r0, [...]
+                  mov r0, #0
+                  str r0, [...]
+
+                  and removes all superfluous mov instructions
+                }
+                else if (taicpu(hpfar1).opcode=A_STR) then
                   begin
-                    DebugMsg('Peephole Optimization: MovStrMov done', hp2);
-                    GetNextInstruction(hp2,hp1);
-                    asml.remove(hp2);
-                    hp2.free;
-                    result:=true;
-                    if not assigned(hp1) then break;
-                  end;
+                    hp1 := hpfar1;
+                    while MatchInstruction(hp1, A_STR, [taicpu(p).condition], []) and
+                          MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[0]^) and
+                          GetNextInstruction(hp1, hp2) and
+                          MatchInstruction(hp2, A_MOV, [taicpu(p).condition], [PF_None]) and
+                          (taicpu(hp2).ops = 2) and
+                          MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[0]^) and
+                          MatchOperand(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^) do
+                      begin
+                        DebugMsg('Peephole Optimization: MovStrMov done', hp2);
+                        GetNextInstruction(hp2,hp1);
+                        asml.remove(hp2);
+                        hp2.free;
+                        result:=true;
+                        if not assigned(hp1) then break;
+                      end;
 
-                if Result then
-                  Exit;
-              end;
-            end;
-          {
-            This removes the first mov from
-            mov rX,...
-            mov rX,...
-          }
-          if taicpu(hpfar1).opcode=A_MOV then
-            begin
-              hp1 := p;
-              while MatchInstruction(hpfar1, A_MOV, [taicpu(hp1).condition], [taicpu(hp1).oppostfix]) and
-                    (taicpu(hpfar1).ops = 2) and
-                    MatchOperand(taicpu(hp1).oper[0]^, taicpu(hpfar1).oper[0]^) and
-                    { don't remove the first mov if the second is a mov rX,rX }
-                    not(MatchOperand(taicpu(hpfar1).oper[0]^, taicpu(hpfar1).oper[1]^)) do
+                    if Result then
+                      Exit;
+                  end;
+                end;
+              {
+                This removes the first mov from
+                mov rX,...
+                mov rX,...
+              }
+              if taicpu(hpfar1).opcode=A_MOV then
                 begin
-                  { Defer removing the first p until after the while loop }
-                  if p <> hp1 then
+                  hp1 := p;
+                  while MatchInstruction(hpfar1, A_MOV, [taicpu(hp1).condition], [taicpu(hp1).oppostfix]) and
+                        (taicpu(hpfar1).ops = 2) and
+                        MatchOperand(taicpu(hp1).oper[0]^, taicpu(hpfar1).oper[0]^) and
+                        { don't remove the first mov if the second is a mov rX,rX }
+                        not(MatchOperand(taicpu(hpfar1).oper[0]^, taicpu(hpfar1).oper[1]^)) do
                     begin
-                      DebugMsg('Peephole Optimization: MovMov done', hp1);
-                      asml.remove(hp1);
-                      hp1.free;
+                      { Defer removing the first p until after the while loop }
+                      if p <> hp1 then
+                        begin
+                          DebugMsg('Peephole Optimization: MovMov done', hp1);
+                          asml.remove(hp1);
+                          hp1.free;
+                        end;
+                      hp1:=hpfar1;
+                      GetNextInstruction(hpfar1,hpfar1);
+                      result:=true;
+                      if not assigned(hpfar1) then
+                        Break;
+                    end;
+
+                  if Result then
+                    begin
+                      DebugMsg('Peephole Optimization: MovMov done', p);
+                      RemoveCurrentp(p);
+                      Exit;
                     end;
-                  hp1:=hpfar1;
-                  GetNextInstruction(hpfar1,hpfar1);
-                  result:=true;
-                  if not assigned(hpfar1) then
-                    Break;
                 end;
 
-              if Result then
+              if RedundantMovProcess(p,hpfar1) then
                 begin
-                  DebugMsg('Peephole Optimization: MovMov done', p);
-                  RemoveCurrentp(p);
-                  Exit;
+                  Result:=true;
+                  { p might not point at a mov anymore }
+                  exit;
                 end;
-            end;
-
-          if RedundantMovProcess(p,hpfar1) then
-            begin
-              Result:=true;
-              { p might not point at a mov anymore }
-              exit;
-            end;
-
-          { Fold the very common sequence
-              mov  regA, regB
-              ldr* regA, [regA]
-            to
-              ldr* regA, [regB]
-            CAUTION! If this one is successful p might not be a mov instruction anymore!
-          }
-          if
-             // Make sure that Thumb code doesn't propagate a high register into a reference
-             (
-               (
-                 GenerateThumbCode and
-                 (getsupreg(taicpu(p).oper[1]^.reg) < RS_R8)
-               ) or (not GenerateThumbCode)
-             ) and
-             (taicpu(p).oper[1]^.typ = top_reg) and
-             (taicpu(p).oppostfix = PF_NONE) and
-             MatchInstruction(hpfar1, [A_LDR, A_STR], [taicpu(p).condition], []) and
-             (taicpu(hpfar1).oper[1]^.typ = top_ref) and
-             { We can change the base register only when the instruction uses AM_OFFSET }
-             ((taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg) or
-               ((taicpu(hpfar1).oper[1]^.ref^.addressmode = AM_OFFSET) and
-                (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg))
-             ) and
-             not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hpfar1)) and
-             RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
-            begin
-              DebugMsg('Peephole Optimization: MovLdr2Ldr done', hpfar1);
-              if (taicpu(hpfar1).oper[1]^.ref^.addressmode = AM_OFFSET) and
-                 (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg) then
-                taicpu(hpfar1).oper[1]^.ref^.base := taicpu(p).oper[1]^.reg;
 
-              if taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg then
-                taicpu(hpfar1).oper[1]^.ref^.index := taicpu(p).oper[1]^.reg;
+              { If hpfar1 is nil after the call to RedundantMovProcess, it is
+                because it would have become a dangling pointer, so reinitialise it. }
+              if not Assigned(hpfar1) then
+                Continue;
 
-              dealloc:=FindRegDeAlloc(taicpu(p).oper[1]^.reg, tai(p.Next));
-              if Assigned(dealloc) then
+              { Fold the very common sequence
+                  mov  regA, regB
+                  ldr* regA, [regA]
+                to
+                  ldr* regA, [regB]
+                CAUTION! If this one is successful p might not be a mov instruction anymore!
+              }
+              if
+                 // Make sure that Thumb code doesn't propagate a high register into a reference
+                 (
+                   (
+                     GenerateThumbCode and
+                     (getsupreg(taicpu(p).oper[1]^.reg) < RS_R8)
+                   ) or (not GenerateThumbCode)
+                 ) and
+                 (taicpu(p).oper[1]^.typ = top_reg) and
+                 (taicpu(p).oppostfix = PF_NONE) and
+                 MatchInstruction(hpfar1, [A_LDR, A_STR], [taicpu(p).condition], []) and
+                 (taicpu(hpfar1).oper[1]^.typ = top_ref) and
+                 { We can change the base register only when the instruction uses AM_OFFSET }
+                 ((taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg) or
+                   ((taicpu(hpfar1).oper[1]^.ref^.addressmode = AM_OFFSET) and
+                    (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg))
+                 ) and
+                 not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hpfar1)) and
+                 RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
                 begin
-                  asml.remove(dealloc);
-                  asml.InsertAfter(dealloc,hpfar1);
-                end;
+                  DebugMsg('Peephole Optimization: MovLdr2Ldr done', hpfar1);
+                  if (taicpu(hpfar1).oper[1]^.ref^.addressmode = AM_OFFSET) and
+                     (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg) then
+                    taicpu(hpfar1).oper[1]^.ref^.base := taicpu(p).oper[1]^.reg;
 
-              if not Assigned(hp1) then
-                GetNextInstruction(p, hp1);
+                  if taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg then
+                    taicpu(hpfar1).oper[1]^.ref^.index := taicpu(p).oper[1]^.reg;
 
-              RemoveCurrentP(p, hp1);
+                  dealloc:=FindRegDeAlloc(taicpu(p).oper[1]^.reg, tai(p.Next));
+                  if Assigned(dealloc) then
+                    begin
+                      asml.remove(dealloc);
+                      asml.InsertAfter(dealloc,hpfar1);
+                    end;
 
-              result:=true;
-              Exit;
-            end
-        end
+                  if (not Assigned(hp1)) or (p=hp1) then
+                    GetNextInstruction(p, hp1);
 
-      { 3-operald mov optimisations }
-      else if (taicpu(p).ops = 3) then
-        begin
+                  RemoveCurrentP(p, hp1);
 
-          if (taicpu(p).oper[2]^.typ = top_shifterop) and
-            (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
-            (taicpu(p).oper[2]^.shifterop^.shiftmode = SM_LSR) and
-            (taicpu(hpfar1).ops>=1) and
-            (taicpu(hpfar1).oper[0]^.typ=top_reg) and
-            (not RegModifiedBetween(taicpu(hpfar1).oper[0]^.reg, p, hpfar1)) and
-            RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
-            begin
-              if (taicpu(p).oper[2]^.shifterop^.shiftimm >= 24 ) and
-                MatchInstruction(hpfar1, A_AND, [taicpu(p).condition], [taicpu(p).oppostfix]) and
-                (taicpu(hpfar1).ops=3) and
-                MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^) and
-                (taicpu(hpfar1).oper[2]^.typ = top_const) and
-                { Check if the AND actually would only mask out bits being already zero because of the shift
-                }
-                ((($ffffffff shr taicpu(p).oper[2]^.shifterop^.shiftimm) and taicpu(hpfar1).oper[2]^.val) =
-                  ($ffffffff shr taicpu(p).oper[2]^.shifterop^.shiftimm)) then
-                begin
-                  DebugMsg('Peephole Optimization: LsrAnd2Lsr done', hpfar1);
-                  taicpu(p).oper[0]^.reg:=taicpu(hpfar1).oper[0]^.reg;
-                  asml.remove(hpfar1);
-                  hpfar1.free;
                   result:=true;
                   Exit;
                 end
-              else if MatchInstruction(hpfar1, A_BIC, [taicpu(p).condition], [taicpu(p).oppostfix]) and
-                (taicpu(hpfar1).ops=3) and
-                MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^) and
-                (taicpu(hpfar1).oper[2]^.typ = top_const) and
-                { Check if the BIC actually would only mask out bits beeing already zero because of the shift }
-                (taicpu(hpfar1).oper[2]^.val<>0) and
-                (BsfDWord(taicpu(hpfar1).oper[2]^.val)>=32-taicpu(p).oper[2]^.shifterop^.shiftimm) then
-                begin
-                  DebugMsg('Peephole Optimization: LsrBic2Lsr done', hpfar1);
-                  taicpu(p).oper[0]^.reg:=taicpu(hpfar1).oper[0]^.reg;
-                  asml.remove(hpfar1);
-                  hpfar1.free;
-                  result:=true;
-                  Exit;
-                end;
-            end;
-          { This folds shifterops into following instructions
-            mov r0, r1, lsl #8
-            add r2, r3, r0
+            end
 
-            to
+          { 3-operald mov optimisations }
+          else if (taicpu(p).ops = 3) then
+            begin
 
-            add r2, r3, r1, lsl #8
-            CAUTION! If this one is successful p might not be a mov instruction anymore!
-          }
-          if (taicpu(p).oper[1]^.typ = top_reg) and
-           (taicpu(p).oper[2]^.typ = top_shifterop) and
-           (taicpu(p).oppostfix = PF_NONE) and
-           MatchInstruction(hpfar1, [A_ADD, A_ADC, A_RSB, A_RSC, A_SUB, A_SBC,
-                                  A_AND, A_BIC, A_EOR, A_ORR, A_TEQ, A_TST,
-                                  A_CMP, A_CMN],
-                            [taicpu(p).condition], [PF_None]) and
-           (not ((GenerateThumb2Code) and
-                 (taicpu(hpfar1).opcode in [A_SBC]) and
-                 (((taicpu(hpfar1).ops=3) and
-                   MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^.reg)) or
-                  ((taicpu(hpfar1).ops=2) and
-                   MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[0]^.reg))))) and
-           RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) and
-           (taicpu(hpfar1).ops >= 2) and
-           {Currently we can't fold into another shifterop}
-           (taicpu(hpfar1).oper[taicpu(hpfar1).ops-1]^.typ = top_reg) and
-           {Folding rrx is problematic because of the C-Flag, as we currently can't check
-            NR_DEFAULTFLAGS for modification}
-           (
-             {Everything is fine if we don't use RRX}
-             (taicpu(p).oper[2]^.shifterop^.shiftmode <> SM_RRX) or
-             (
-               {If it is RRX, then check if we're just accessing the next instruction}
-               Assigned(hp1) and
-               (hpfar1 = hp1)
-             )
-           ) and
-           { reg1 might not be modified inbetween }
-           not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hpfar1)) and
-           { The shifterop can contain a register, might not be modified}
-           (
-             (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) or
-             not(RegModifiedBetween(taicpu(p).oper[2]^.shifterop^.rs, p, hpfar1))
-           ) and
-           (
-             {Only ONE of the two src operands is allowed to match}
-             MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[taicpu(hpfar1).ops-2]^) xor
-             MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[taicpu(hpfar1).ops-1]^)
-           ) then
-          begin
-            if taicpu(hpfar1).opcode in [A_TST, A_TEQ, A_CMN] then
-              I2:=0
-            else
-              I2:=1;
-            for I:=I2 to taicpu(hpfar1).ops-1 do
-              if MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[I]^.reg) then
+              if (taicpu(p).oper[2]^.typ = top_shifterop) and
+                (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
+                (taicpu(p).oper[2]^.shifterop^.shiftmode = SM_LSR) and
+                (taicpu(hpfar1).ops>=1) and
+                (taicpu(hpfar1).oper[0]^.typ=top_reg) and
+                (not RegModifiedBetween(taicpu(hpfar1).oper[0]^.reg, p, hpfar1)) and
+                RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
                 begin
-                  { If the parameter matched on the second op from the RIGHT
-                    we have to switch the parameters, this will not happen for CMP
-                    were we're only evaluating the most right parameter
-                  }
-                  if I <> taicpu(hpfar1).ops-1 then
+                  if (taicpu(p).oper[2]^.shifterop^.shiftimm >= 24 ) and
+                    MatchInstruction(hpfar1, A_AND, [taicpu(p).condition], [taicpu(p).oppostfix]) and
+                    (taicpu(hpfar1).ops=3) and
+                    MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^) and
+                    (taicpu(hpfar1).oper[2]^.typ = top_const) and
+                    { Check if the AND actually would only mask out bits being already zero because of the shift
+                    }
+                    ((($ffffffff shr taicpu(p).oper[2]^.shifterop^.shiftimm) and taicpu(hpfar1).oper[2]^.val) =
+                      ($ffffffff shr taicpu(p).oper[2]^.shifterop^.shiftimm)) then
                     begin
-                      {The SUB operators need to be changed when we swap parameters}
-                      case taicpu(hpfar1).opcode of
-                        A_SUB: tempop:=A_RSB;
-                        A_SBC: tempop:=A_RSC;
-                        A_RSB: tempop:=A_SUB;
-                        A_RSC: tempop:=A_SBC;
-                        else tempop:=taicpu(hpfar1).opcode;
-                      end;
-                      if taicpu(hpfar1).ops = 3 then
-                        hp2:=taicpu.op_reg_reg_reg_shifterop(tempop,
-                             taicpu(hpfar1).oper[0]^.reg, taicpu(hpfar1).oper[2]^.reg,
-                             taicpu(p).oper[1]^.reg, taicpu(p).oper[2]^.shifterop^)
-                      else
-                        hp2:=taicpu.op_reg_reg_shifterop(tempop,
-                             taicpu(hpfar1).oper[0]^.reg, taicpu(p).oper[1]^.reg,
-                             taicpu(p).oper[2]^.shifterop^);
+                      DebugMsg('Peephole Optimization: LsrAnd2Lsr done', hpfar1);
+                      taicpu(p).oper[0]^.reg:=taicpu(hpfar1).oper[0]^.reg;
+                      asml.remove(hpfar1);
+                      hpfar1.free;
+                      result:=true;
+                      Exit;
                     end
-                  else
-                    if taicpu(hpfar1).ops = 3 then
-                      hp2:=taicpu.op_reg_reg_reg_shifterop(taicpu(hpfar1).opcode,
-                           taicpu(hpfar1).oper[0]^.reg, taicpu(hpfar1).oper[1]^.reg,
-                           taicpu(p).oper[1]^.reg, taicpu(p).oper[2]^.shifterop^)
-                    else
-                      hp2:=taicpu.op_reg_reg_shifterop(taicpu(hpfar1).opcode,
-                           taicpu(hpfar1).oper[0]^.reg, taicpu(p).oper[1]^.reg,
-                           taicpu(p).oper[2]^.shifterop^);
-                  if taicpu(p).oper[2]^.shifterop^.rs<>NR_NO then
-                    AllocRegBetween(taicpu(p).oper[2]^.shifterop^.rs,p,hpfar1,UsedRegs);
-                  AllocRegBetween(taicpu(p).oper[1]^.reg,p,hpfar1,UsedRegs);
-                  asml.insertbefore(hp2, hpfar1);
-                  asml.remove(hpfar1);
-                  hpfar1.free;
-                  DebugMsg('Peephole Optimization: FoldShiftProcess done', hp2);
-
-                  if not Assigned(hp1) then
-                    GetNextInstruction(p, hp1)
-                  else if hp1 = hpfar1 then
-                    { If hp1 = hpfar1, then it's a dangling pointer }
-                    hp1 := hp2;
-
-                  RemoveCurrentP(p, hp1);
-                  Result:=true;
-                  Exit;
+                  else if MatchInstruction(hpfar1, A_BIC, [taicpu(p).condition], [taicpu(p).oppostfix]) and
+                    (taicpu(hpfar1).ops=3) and
+                    MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^) and
+                    (taicpu(hpfar1).oper[2]^.typ = top_const) and
+                    { Check if the BIC actually would only mask out bits beeing already zero because of the shift }
+                    (taicpu(hpfar1).oper[2]^.val<>0) and
+                    (BsfDWord(taicpu(hpfar1).oper[2]^.val)>=32-taicpu(p).oper[2]^.shifterop^.shiftimm) then
+                    begin
+                      DebugMsg('Peephole Optimization: LsrBic2Lsr done', hpfar1);
+                      taicpu(p).oper[0]^.reg:=taicpu(hpfar1).oper[0]^.reg;
+                      asml.remove(hpfar1);
+                      hpfar1.free;
+                      result:=true;
+                      Exit;
+                    end;
                 end;
-          end;
-        {
-          Fold
-            mov r1, r1, lsl #2
-            ldr/ldrb r0, [r0, r1]
-          to
-            ldr/ldrb r0, [r0, r1, lsl #2]
-
-          XXX: This still needs some work, as we quite often encounter something like
-                 mov r1, r2, lsl #2
-                 add r2, r3, #imm
-                 ldr r0, [r2, r1]
-               which can't be folded because r2 is overwritten between the shift and the ldr.
-               We could try to shuffle the registers around and fold it into.
-                 add r1, r3, #imm
-                 ldr r0, [r1, r2, lsl #2]
-        }
-        if (not(GenerateThumbCode)) and
-          { thumb2 allows only lsl #0..#3 }
-          (not(GenerateThumb2Code) or
-           ((taicpu(p).oper[2]^.shifterop^.shiftimm in [0..3]) and
-            (taicpu(p).oper[2]^.shifterop^.shiftmode=SM_LSL)
-           )
-          ) and
-           (taicpu(p).oper[1]^.typ = top_reg) and
-           (taicpu(p).oper[2]^.typ = top_shifterop) and
-           { RRX is tough to handle, because it requires tracking the C-Flag,
-             it is also extremly unlikely to be emitted this way}
-           (taicpu(p).oper[2]^.shifterop^.shiftmode <> SM_RRX) and
-           (taicpu(p).oper[2]^.shifterop^.shiftimm <> 0) and
-           (taicpu(p).oppostfix = PF_NONE) and
-           {Only LDR, LDRB, STR, STRB can handle scaled register indexing}
-           (MatchInstruction(hpfar1, [A_LDR, A_STR], [taicpu(p).condition], [PF_None, PF_B]) or
-            (GenerateThumb2Code and
-             MatchInstruction(hpfar1, [A_LDR, A_STR], [taicpu(p).condition], [PF_None, PF_B, PF_SB, PF_H, PF_SH]))
-           ) and
-           (
-             {If this is address by offset, one of the two registers can be used}
-             ((taicpu(hpfar1).oper[1]^.ref^.addressmode=AM_OFFSET) and
+              { This folds shifterops into following instructions
+                mov r0, r1, lsl #8
+                add r2, r3, r0
+
+                to
+
+                add r2, r3, r1, lsl #8
+                CAUTION! If this one is successful p might not be a mov instruction anymore!
+              }
+              if (taicpu(p).oper[1]^.typ = top_reg) and
+               (taicpu(p).oper[2]^.typ = top_shifterop) and
+               (taicpu(p).oppostfix = PF_NONE) and
+               MatchInstruction(hpfar1, [A_ADD, A_ADC, A_RSB, A_RSC, A_SUB, A_SBC,
+                                      A_AND, A_BIC, A_EOR, A_ORR, A_TEQ, A_TST,
+                                      A_CMP, A_CMN],
+                                [taicpu(p).condition], [PF_None]) and
+               (not ((GenerateThumb2Code) and
+                     (taicpu(hpfar1).opcode in [A_SBC]) and
+                     (((taicpu(hpfar1).ops=3) and
+                       MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[1]^.reg)) or
+                      ((taicpu(hpfar1).ops=2) and
+                       MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[0]^.reg))))) and
+               RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) and
+               (taicpu(hpfar1).ops >= 2) and
+               {Currently we can't fold into another shifterop}
+               (taicpu(hpfar1).oper[taicpu(hpfar1).ops-1]^.typ = top_reg) and
+               {Folding rrx is problematic because of the C-Flag, as we currently can't check
+                NR_DEFAULTFLAGS for modification}
+               (
+                 {Everything is fine if we don't use RRX}
+                 (taicpu(p).oper[2]^.shifterop^.shiftmode <> SM_RRX) or
+                 (
+                   {If it is RRX, then check if we're just accessing the next instruction}
+                   Assigned(hp1) and
+                   (hpfar1 = hp1)
+                 )
+               ) and
+               { reg1 might not be modified inbetween }
+               not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hpfar1)) and
+               { The shifterop can contain a register, might not be modified}
                (
-                 (taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg) xor
-                 (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg)
+                 (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) or
+                 not(RegModifiedBetween(taicpu(p).oper[2]^.shifterop^.rs, p, hpfar1))
+               ) and
+               (
+                 {Only ONE of the two src operands is allowed to match}
+                 MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[taicpu(hpfar1).ops-2]^) xor
+                 MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[taicpu(hpfar1).ops-1]^)
+               ) then
+              begin
+                if taicpu(hpfar1).opcode in [A_TST, A_TEQ, A_CMN] then
+                  I2:=0
+                else
+                  I2:=1;
+                for I:=I2 to taicpu(hpfar1).ops-1 do
+                  if MatchOperand(taicpu(p).oper[0]^, taicpu(hpfar1).oper[I]^.reg) then
+                    begin
+                      { If the parameter matched on the second op from the RIGHT
+                        we have to switch the parameters, this will not happen for CMP
+                        were we're only evaluating the most right parameter
+                      }
+                      if I <> taicpu(hpfar1).ops-1 then
+                        begin
+                          {The SUB operators need to be changed when we swap parameters}
+                          case taicpu(hpfar1).opcode of
+                            A_SUB: tempop:=A_RSB;
+                            A_SBC: tempop:=A_RSC;
+                            A_RSB: tempop:=A_SUB;
+                            A_RSC: tempop:=A_SBC;
+                            else tempop:=taicpu(hpfar1).opcode;
+                          end;
+                          if taicpu(hpfar1).ops = 3 then
+                            hp2:=taicpu.op_reg_reg_reg_shifterop(tempop,
+                                 taicpu(hpfar1).oper[0]^.reg, taicpu(hpfar1).oper[2]^.reg,
+                                 taicpu(p).oper[1]^.reg, taicpu(p).oper[2]^.shifterop^)
+                          else
+                            hp2:=taicpu.op_reg_reg_shifterop(tempop,
+                                 taicpu(hpfar1).oper[0]^.reg, taicpu(p).oper[1]^.reg,
+                                 taicpu(p).oper[2]^.shifterop^);
+                        end
+                      else
+                        if taicpu(hpfar1).ops = 3 then
+                          hp2:=taicpu.op_reg_reg_reg_shifterop(taicpu(hpfar1).opcode,
+                               taicpu(hpfar1).oper[0]^.reg, taicpu(hpfar1).oper[1]^.reg,
+                               taicpu(p).oper[1]^.reg, taicpu(p).oper[2]^.shifterop^)
+                        else
+                          hp2:=taicpu.op_reg_reg_shifterop(taicpu(hpfar1).opcode,
+                               taicpu(hpfar1).oper[0]^.reg, taicpu(p).oper[1]^.reg,
+                               taicpu(p).oper[2]^.shifterop^);
+                      if taicpu(p).oper[2]^.shifterop^.rs<>NR_NO then
+                        AllocRegBetween(taicpu(p).oper[2]^.shifterop^.rs,p,hpfar1,UsedRegs);
+                      AllocRegBetween(taicpu(p).oper[1]^.reg,p,hpfar1,UsedRegs);
+                      asml.insertbefore(hp2, hpfar1);
+                      asml.remove(hpfar1);
+                      hpfar1.free;
+                      DebugMsg('Peephole Optimization: FoldShiftProcess done', hp2);
+
+                      if not Assigned(hp1) then
+                        GetNextInstruction(p, hp1)
+                      else if hp1 = hpfar1 then
+                        { If hp1 = hpfar1, then it's a dangling pointer }
+                        hp1 := hp2;
+
+                      RemoveCurrentP(p, hp1);
+                      Result:=true;
+                      Exit;
+                    end;
+              end;
+            {
+              Fold
+                mov r1, r1, lsl #2
+                ldr/ldrb r0, [r0, r1]
+              to
+                ldr/ldrb r0, [r0, r1, lsl #2]
+
+              XXX: This still needs some work, as we quite often encounter something like
+                     mov r1, r2, lsl #2
+                     add r2, r3, #imm
+                     ldr r0, [r2, r1]
+                   which can't be folded because r2 is overwritten between the shift and the ldr.
+                   We could try to shuffle the registers around and fold it into.
+                     add r1, r3, #imm
+                     ldr r0, [r1, r2, lsl #2]
+            }
+            if (not(GenerateThumbCode)) and
+              { thumb2 allows only lsl #0..#3 }
+              (not(GenerateThumb2Code) or
+               ((taicpu(p).oper[2]^.shifterop^.shiftimm in [0..3]) and
+                (taicpu(p).oper[2]^.shifterop^.shiftmode=SM_LSL)
                )
-             ) or
-             {For post and preindexed only the index register can be used}
-             ((taicpu(hpfar1).oper[1]^.ref^.addressmode in [AM_POSTINDEXED, AM_PREINDEXED]) and
+              ) and
+               (taicpu(p).oper[1]^.typ = top_reg) and
+               (taicpu(p).oper[2]^.typ = top_shifterop) and
+               { RRX is tough to handle, because it requires tracking the C-Flag,
+                 it is also extremly unlikely to be emitted this way}
+               (taicpu(p).oper[2]^.shifterop^.shiftmode <> SM_RRX) and
+               (taicpu(p).oper[2]^.shifterop^.shiftimm <> 0) and
+               (taicpu(p).oppostfix = PF_NONE) and
+               {Only LDR, LDRB, STR, STRB can handle scaled register indexing}
+               (MatchInstruction(hpfar1, [A_LDR, A_STR], [taicpu(p).condition], [PF_None, PF_B]) or
+                (GenerateThumb2Code and
+                 MatchInstruction(hpfar1, [A_LDR, A_STR], [taicpu(p).condition], [PF_None, PF_B, PF_SB, PF_H, PF_SH]))
+               ) and
                (
-                 (taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg) and
-                 (taicpu(hpfar1).oper[1]^.ref^.base <> taicpu(p).oper[0]^.reg)
+                 {If this is address by offset, one of the two registers can be used}
+                 ((taicpu(hpfar1).oper[1]^.ref^.addressmode=AM_OFFSET) and
+                   (
+                     (taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg) xor
+                     (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg)
+                   )
+                 ) or
+                 {For post and preindexed only the index register can be used}
+                 ((taicpu(hpfar1).oper[1]^.ref^.addressmode in [AM_POSTINDEXED, AM_PREINDEXED]) and
+                   (
+                     (taicpu(hpfar1).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg) and
+                     (taicpu(hpfar1).oper[1]^.ref^.base <> taicpu(p).oper[0]^.reg)
+                   ) and
+                   (not GenerateThumb2Code)
+                 )
                ) and
-               (not GenerateThumb2Code)
-             )
-           ) and
-           { Only fold if both registers are used. Otherwise we are folding p with itself }
-           (taicpu(hpfar1).oper[1]^.ref^.index<>NR_NO) and
-           (taicpu(hpfar1).oper[1]^.ref^.base<>NR_NO) and
-           { Only fold if there isn't another shifterop already, and offset is zero. }
-           (taicpu(hpfar1).oper[1]^.ref^.offset = 0) and
-           (taicpu(hpfar1).oper[1]^.ref^.shiftmode = SM_None) and
-           not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hpfar1)) and
-           RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
-           begin
-             { If the register we want to do the shift for resides in base, we need to swap that}
-             if (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg) then
-               taicpu(hpfar1).oper[1]^.ref^.base := taicpu(hpfar1).oper[1]^.ref^.index;
-             taicpu(hpfar1).oper[1]^.ref^.index := taicpu(p).oper[1]^.reg;
-             taicpu(hpfar1).oper[1]^.ref^.shiftmode := taicpu(p).oper[2]^.shifterop^.shiftmode;
-             taicpu(hpfar1).oper[1]^.ref^.shiftimm := taicpu(p).oper[2]^.shifterop^.shiftimm;
-             DebugMsg('Peephole Optimization: FoldShiftLdrStr done', hpfar1);
-             RemoveCurrentP(p);
-             Result:=true;
-             Exit;
-           end;
+               { Only fold if both registers are used. Otherwise we are folding p with itself }
+               (taicpu(hpfar1).oper[1]^.ref^.index<>NR_NO) and
+               (taicpu(hpfar1).oper[1]^.ref^.base<>NR_NO) and
+               { Only fold if there isn't another shifterop already, and offset is zero. }
+               (taicpu(hpfar1).oper[1]^.ref^.offset = 0) and
+               (taicpu(hpfar1).oper[1]^.ref^.shiftmode = SM_None) and
+               not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hpfar1)) and
+               RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hpfar1)) then
+               begin
+                 { If the register we want to do the shift for resides in base, we need to swap that}
+                 if (taicpu(hpfar1).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg) then
+                   taicpu(hpfar1).oper[1]^.ref^.base := taicpu(hpfar1).oper[1]^.ref^.index;
+                 taicpu(hpfar1).oper[1]^.ref^.index := taicpu(p).oper[1]^.reg;
+                 taicpu(hpfar1).oper[1]^.ref^.shiftmode := taicpu(p).oper[2]^.shifterop^.shiftmode;
+                 taicpu(hpfar1).oper[1]^.ref^.shiftimm := taicpu(p).oper[2]^.shifterop^.shiftimm;
+                 DebugMsg('Peephole Optimization: FoldShiftLdrStr done', hpfar1);
+                 RemoveCurrentP(p);
+                 Result:=true;
+                 Exit;
+               end;
+            end;
+          {
+            Often we see shifts and then a superfluous mov to another register
+            In the future this might be handled in RedundantMovProcess when it uses RegisterTracking
+          }
+          if RemoveSuperfluousMove(p, hpfar1, 'MovMov2Mov') then
+            Result:=true;
+
+          Exit;
         end;
-      {
-        Often we see shifts and then a superfluous mov to another register
-        In the future this might be handled in RedundantMovProcess when it uses RegisterTracking
-      }
-      if RemoveSuperfluousMove(p, hpfar1, 'MovMov2Mov') then
-        Result:=true;
     end;
 
 

compiler/arm/armins.dat

@@ -259,7 +259,7 @@ fpureg,immshifter,memam2 \xA0\xC\x10\x2\x0              ARM32,FPA
 
 [CLZcc]
 reg32,reg32              \x80\xFA\xB0\xF0\x80           THUMB32,ARMv6T2
-reg32,reg32              \x32\x01\x6F\xF\x10            ARM32,ARMv4
+reg32,reg32              \x32\x01\x6F\xF\x10            ARM32,ARMv5T
 
 [CPS]
 immshifter               \x8F\xF3\xAF\x81\x00           THUMB32,ARMv6T2

compiler/arm/armtab.inc

@@ -768,7 +768,7 @@
     ops     : 2;
     optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #50#1#111#15#16;
-    flags   : if_arm32 or if_armv4
+    flags   : if_arm32 or if_armv5t
   ),
   (
     opcode  : A_CPS;

compiler/arm/cgcpu.pas

@@ -329,7 +329,7 @@ unit cgcpu;
           imm1, imm2: DWord;
        begin
           if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
-            internalerror(2002090902);
+            internalerror(2002090907);
           if is_shifter_const(a,imm_shift) then
             list.concat(taicpu.op_reg_const(A_MOV,reg,a))
           else if is_shifter_const(not(a),imm_shift) then
@@ -516,7 +516,7 @@ unit cgcpu;
         hsym:=tsym(procdef.parast.Find('self'));
         if not(assigned(hsym) and
           (hsym.typ=paravarsym)) then
-          internalerror(200305251);
+          internalerror(2003052503);
         paraloc:=tparavarsym(hsym).paraloc[callerside].location;
         while paraloc<>nil do
           with paraloc^ do
@@ -546,7 +546,7 @@ unit cgcpu;
                       end;
                   end
                 else
-                  internalerror(200309189);
+                  internalerror(2003091803);
               end;
               paraloc:=next;
             end;
@@ -1089,7 +1089,7 @@ unit cgcpu;
           OP_ROL:
             begin
               if not(size in [OS_32,OS_S32]) then
-                internalerror(2008072801);
+                internalerror(2008072804);
               { simulate ROL by ror'ing 32-value }
               tmpreg:=getintregister(list,OS_32);
               list.concat(taicpu.op_reg_reg_const(A_RSB,tmpreg,src1, 32));
@@ -1210,7 +1210,7 @@ unit cgcpu;
         if (ref.base=NR_NO) then
           begin
             if ref.shiftmode<>SM_None then
-              internalerror(2014020701);
+              internalerror(2014020707);
             ref.base:=ref.index;
             ref.index:=NR_NO;
           end;
@@ -1368,7 +1368,7 @@ unit cgcpu;
            OS_F32:
              oppostfix:=PF_None;
            else
-             InternalError(200308299);
+             InternalError(2003082912);
          end;
 
          if ((ref.alignment in [1,2]) and (ref.alignment<tcgsize2size[tosize])) or
@@ -2187,7 +2187,7 @@ unit cgcpu;
                   mmregs:=(rg[R_MMREGISTER].used_in_proc-paramanager.get_volatile_registers_mm(pocall_stdcall))*[0..31];
                 end
               else
-                internalerror(2019050926);
+                internalerror(2019050908);
             end;
 
             if (firstfloatreg<>RS_NO) or
@@ -3193,14 +3193,14 @@ unit cgcpu;
               tosize:=OS_F32;
               { since we are loading an integer, no conversion may be required }
               if (fromsize<>tosize) then
-                internalerror(2009112801);
+                internalerror(2009112802);
             end;
           OS_64,OS_S64:
             begin
               tosize:=OS_F64;
               { since we are loading an integer, no conversion may be required }
               if (fromsize<>tosize) then
-                internalerror(2009112901);
+                internalerror(2009112902);
             end;
           OS_F32,OS_F64:
             ;
@@ -3264,7 +3264,7 @@ unit cgcpu;
         if (fromsize<>OS_F32) then
           internalerror(2009112430);
         if not(tosize in [OS_32,OS_S32]) then
-          internalerror(2009112420);
+          internalerror(2009112409);
         if assigned(shuffle) and
            not shufflescalar(shuffle) then
           internalerror(2009112514);
@@ -3595,7 +3595,7 @@ unit cgcpu;
                   list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi),PF_S));
                 end;
               else
-                internalerror(2003083101);
+                internalerror(2003083102);
             end;
             if size=OS_64 then
               begin
@@ -3634,7 +3634,7 @@ unit cgcpu;
                   cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
                 end;
               else
-                internalerror(2003083101);
+                internalerror(2003083104);
             end;
           end;
       end;
@@ -3976,7 +3976,7 @@ unit cgcpu;
           hr : treference;
        begin
           if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
-            internalerror(2002090902);
+            internalerror(2002090908);
           if is_thumb_imm(a) then
             list.concat(taicpu.op_reg_const(A_MOV,reg,a))
           else
@@ -4008,7 +4008,7 @@ unit cgcpu;
         hsym:=tsym(procdef.parast.Find('self'));
         if not(assigned(hsym) and
           (hsym.typ=paravarsym)) then
-          internalerror(200305251);
+          internalerror(2003052504);
         paraloc:=tparavarsym(hsym).paraloc[callerside].location;
         while paraloc<>nil do
           with paraloc^ do
@@ -4058,7 +4058,7 @@ unit cgcpu;
                       end;
                   end
                 else
-                  internalerror(200309189);
+                  internalerror(2003091804);
               end;
               paraloc:=next;
             end;
@@ -4145,7 +4145,7 @@ unit cgcpu;
           OP_ROL:
             begin
               if not(size in [OS_32,OS_S32]) then
-                internalerror(2008072801);
+                internalerror(2008072805);
               { simulate ROL by ror'ing 32-value }
               tmpreg:=getintregister(list,OS_32);
               a_load_const_reg(list,OS_32,32,tmpreg);
@@ -4227,7 +4227,7 @@ unit cgcpu;
             else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
               begin
                 if l1>32 then{roozbeh does this ever happen?}
-                  internalerror(200308296);
+                  internalerror(2003082903);
                 shifterop_reset(so);
                 so.shiftmode:=SM_LSL;
                 so.shiftimm:=l1;
@@ -4237,7 +4237,7 @@ unit cgcpu;
             else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a+1,l1) and not(cgsetflags or setflags) then
               begin
                 if l1>32 then{does this ever happen?}
-                  internalerror(201205181);
+                  internalerror(2012051802);
                 shifterop_reset(so);
                 so.shiftmode:=SM_LSL;
                 so.shiftimm:=l1;
@@ -4384,7 +4384,7 @@ unit cgcpu;
           hr : treference;
        begin
           if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
-            internalerror(2002090902);
+            internalerror(2002090909);
           if is_thumb32_imm(a) then
             list.concat(taicpu.op_reg_const(A_MOV,reg,a))
           else if is_thumb32_imm(not(a)) then
@@ -4431,7 +4431,7 @@ unit cgcpu;
            OS_S32:
              oppostfix:=PF_None;
            else
-             InternalError(200308299);
+             InternalError(2003082913);
          end;
          if (ref.alignment in [1,2]) and (ref.alignment<tcgsize2size[fromsize]) then
            begin
@@ -4702,7 +4702,7 @@ unit cgcpu;
             else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
               begin
                 if l1>32 then{roozbeh does this ever happen?}
-                  internalerror(200308296);
+                  internalerror(2003082911);
                 shifterop_reset(so);
                 so.shiftmode:=SM_LSL;
                 so.shiftimm:=l1;
@@ -4712,7 +4712,7 @@ unit cgcpu;
             else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a+1,l1) and not(cgsetflags or setflags) then
               begin
                 if l1>32 then{does this ever happen?}
-                  internalerror(201205181);
+                  internalerror(2012051803);
                 shifterop_reset(so);
                 so.shiftmode:=SM_LSL;
                 so.shiftimm:=l1;
@@ -4774,7 +4774,7 @@ unit cgcpu;
            OP_ROL:
               begin
                 if not(size in [OS_32,OS_S32]) then
-                   internalerror(2008072801);
+                   internalerror(2008072806);
                 { simulate ROL by ror'ing 32-value }
                 tmpreg:=getintregister(list,OS_32);
                 list.concat(taicpu.op_reg_const(A_MOV,tmpreg,32));
@@ -5154,7 +5154,7 @@ unit cgcpu;
                 else if ref.refaddr=addr_tpoff then
                   begin
                     if assigned(ref.relsymbol) or (ref.offset<>0) then
-                      Internalerror(2019092805);
+                      Internalerror(2019092807);
 
                     current_procinfo.aktlocaldata.concat(tai_const.Create_type_sym(aitconst_tpoff,ref.symbol));
                   end
@@ -5224,7 +5224,7 @@ unit cgcpu;
         if ((op in [A_LDF,A_STF,A_FLDS,A_FLDD,A_FSTS,A_FSTD]) or (op=A_VSTR) or (op=A_VLDR)) and (ref.index<>NR_NO) then
           begin
             if ref.shiftmode<>SM_none then
-              internalerror(200309121);
+              internalerror(2003091202);
             if tmpreg<>NR_NO then
               begin
                 if ref.base=tmpreg then
@@ -5238,7 +5238,7 @@ unit cgcpu;
                 else
                   begin
                     if ref.index<>tmpreg then
-                      internalerror(200403161);
+                      internalerror(2004031602);
                     if ref.signindex<0 then
                       list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg,ref.base,tmpreg))
                     else
@@ -5377,7 +5377,7 @@ unit cgcpu;
               list.concat(taicpu.op_reg_reg(A_SBC,regdst.reghi,regsrc.reghi));
             end;
           else
-            internalerror(2003083101);
+            internalerror(2003083105);
         end;
       end;
 
@@ -5431,7 +5431,7 @@ unit cgcpu;
               list.concat(taicpu.op_reg_reg(A_SBC,reg.reghi,tmpreg));
             end;
           else
-            internalerror(2003083101);
+            internalerror(2003083106);
         end;
       end;
 

compiler/arm/cpubase.pas

@@ -44,10 +44,6 @@ unit cpubase;
 
     type
       TAsmOp= {$i armop.inc}
-      {This is a bit of a hack, because there are more than 256 ARM Assembly Ops
-       But FPC currently can't handle more than 256 elements in a set.}
-      TCommonAsmOps = Set of A_None .. A_UADD16;
-
       { This should define the array of instructions as string }
       op2strtable=array[tasmop] of string[11];
 
@@ -56,6 +52,14 @@ unit cpubase;
       firstop = low(tasmop);
       { Last value of opcode enumeration  }
       lastop  = high(tasmop);
+      { Last value of opcode for TCommonAsmOps set below  }
+      LastCommonAsmOp = A_UADD16;
+
+
+    type
+      {This is a bit of a hack, because there are more than 256 ARM Assembly Ops
+       But FPC currently can't handle more than 256 elements in a set.}
+      TCommonAsmOps = Set of A_None .. LastCommonAsmOp;
 
 {*****************************************************************************
                                   Registers

compiler/arm/cpuelf.pas

@@ -923,7 +923,7 @@ implementation
           else
             begin
               writeln(objreloc.ftype);
-              internalerror(200604014);
+              internalerror(2006040107);
             end;
           end
         else           { not relocsec.Used }

compiler/arm/cpupara.pas

@@ -915,7 +915,7 @@ unit cpupara;
               end;
           end
         else
-          internalerror(200410231);
+          internalerror(2004102306);
 
         create_funcretloc_info(p,side);
       end;

compiler/arm/hlcgcpu.pas

@@ -106,7 +106,7 @@ implementation
         l : TAsmLabel;
       begin
         if (procdef.extnumber=$ffff) then
-          Internalerror(200006139);
+          Internalerror(2000061311);
         if GenerateThumbCode then
           begin
             reference_reset_base(href,voidpointertype,NR_R0,tobjectdef(procdef.struct).vmtmethodoffset(procdef.extnumber),ctempposinvalid,sizeof(pint),[]);

compiler/arm/narmadd.pas

@@ -207,7 +207,7 @@ interface
             end;
           fpu_soft:
             { this case should be handled already by pass1 }
-            internalerror(200308252);
+            internalerror(2003082503);
           else if FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype] then
             begin
               { force mmreg as location, left right doesn't matter
@@ -260,7 +260,7 @@ interface
                 slashn :
                   op:=A_VDIV;
                 else
-                  internalerror(2009111401);
+                  internalerror(2009111404);
               end;
 
               current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op, location.register,left.location.register,right.location.register), PF_F32));

compiler/arm/narmcnv.pas

@@ -128,7 +128,7 @@ implementation
                       left:=nil;
                     end;
                   else
-                    internalerror(200610151);
+                    internalerror(2006101504);
                 end;
               s64real:
                 case tfloatdef(resultdef).floattype of
@@ -141,10 +141,10 @@ implementation
                       left:=nil;
                     end;
                   else
-                    internalerror(200610152);
+                    internalerror(2006101505);
                 end;
               else
-                internalerror(200610153);
+                internalerror(2006101506);
             end;
             left:=nil;
             firstpass(result);
@@ -223,7 +223,7 @@ implementation
                           end;
                       end;
                     else
-                      internalerror(200410031);
+                      internalerror(2004100307);
                   end;
               end;
             end;
@@ -248,7 +248,7 @@ implementation
               signed:=left.location.size=OS_S32;
               hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,false);
               if (left.location.size<>OS_F32) then
-                internalerror(2009112703);
+                internalerror(2009112704);
               if left.location.size<>location.size then
                 location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size)
               else
@@ -260,7 +260,7 @@ implementation
             end
           else
             { should be handled in pass 1 }
-            internalerror(2019050934);
+            internalerror(2019050909);
         end;
       end;
 
@@ -358,7 +358,7 @@ implementation
                 tbasecgarm(cg).cgsetflags:=false;
               end;
             else
-              internalerror(200311301);
+              internalerror(2003113002);
          end;
          { load flags to register }
          location_reset(location,LOC_REGISTER,def_cgsize(resultdef));

compiler/arm/narminl.pas

@@ -333,7 +333,7 @@ implementation
               cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
             end
           else
-            internalerror(2009111402);
+            internalerror(2009111405);
         end;
       end;
 

compiler/arm/narmld.pas

@@ -157,7 +157,7 @@ implementation
                       handled:=true;
                     end;
                   else
-                    Internalerror(2019092802);
+                    Internalerror(2019092806);
                 end;
               end;
           end;

compiler/arm/narmmat.pas

@@ -420,7 +420,7 @@ implementation
                 OS_64:
                   cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),location.registerhi);
               else
-                internalerror(2014033101);
+                internalerror(2014033103);
               end;
             end
           else if FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[init_settings.fputype] then

compiler/arm/raarmgas.pas

@@ -988,7 +988,7 @@ Unit raarmgas;
                        OPR_REFERENCE :
                          inc(oper.opr.ref.offset,l);
                        else
-                         internalerror(200309202);
+                         internalerror(2003092021);
                      end;
                    end
                end;

compiler/arm/rgcpu.pas

@@ -491,7 +491,7 @@ unit rgcpu;
             tmpref.index:=hreg;
 
             if spilltemp.index<>NR_NO then
-              internalerror(200401263);
+              internalerror(2004012601);
 
             helplist.concat(spilling_create_load(tmpref,tempreg));
             if getregtype(tempreg)=R_INTREGISTER then
@@ -545,7 +545,7 @@ unit rgcpu;
             helplist.concat(taicpu.op_reg_ref(A_LDR,hreg,tmpref));
 
             if spilltemp.index<>NR_NO then
-              internalerror(200401263);
+              internalerror(2004012602);
 
             reference_reset_base(tmpref,current_procinfo.framepointer,0,ctempposinvalid,sizeof(pint),[]);
             tmpref.index:=hreg;

compiler/armgen/aoptarm.pas

@@ -40,7 +40,7 @@ Type
     procedure DebugMsg(const s : string; p : tai);
 
     function RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string): boolean;
-    function RedundantMovProcess(var p: tai; hp1: tai): boolean;
+    function RedundantMovProcess(var p: tai; var hp1: tai): boolean;
     function GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
 
     function OptPass1UXTB(var p: tai): Boolean;
@@ -53,7 +53,7 @@ Type
   function MatchInstruction(const instr: tai; const op: TCommonAsmOps; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
   function MatchInstruction(const instr: tai; const op: TAsmOp; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
 {$ifdef AARCH64}
-  function MatchInstruction(const instr: tai; const op: TAsmOps; const postfix: TOpPostfixes): boolean;
+  function MatchInstruction(const instr: tai; const ops : array of TAsmOp; const postfix: TOpPostfixes): boolean;
 {$endif AARCH64}
   function MatchInstruction(const instr: tai; const op: TAsmOp; const postfix: TOpPostfixes): boolean;
 
@@ -87,7 +87,7 @@ Implementation
     begin
       result :=
         (instr.typ = ait_instruction) and
-        ((op = []) or ((ord(taicpu(instr).opcode)<256) and (taicpu(instr).opcode in op))) and
+        ((op = []) or ((taicpu(instr).opcode<=LastCommonAsmOp) and (taicpu(instr).opcode in op))) and
         ((cond = []) or (taicpu(instr).condition in cond)) and
         ((postfix = []) or (taicpu(instr).oppostfix in postfix));
     end;
@@ -104,12 +104,22 @@ Implementation
 
 
 {$ifdef AARCH64}
-  function MatchInstruction(const instr: tai; const op: TAsmOps; const postfix: TOpPostfixes): boolean;
-    begin
-      result :=
-        (instr.typ = ait_instruction) and
-        ((op = []) or (taicpu(instr).opcode in op)) and
-        ((postfix = []) or (taicpu(instr).oppostfix in postfix));
+  function MatchInstruction(const instr: tai; const ops : array of TAsmOp; const postfix: TOpPostfixes): boolean;
+  var
+    op : TAsmOp;
+  begin
+    result:=false;
+    if instr.typ <> ait_instruction then
+      exit;
+    for op in ops do
+      begin
+        if (taicpu(instr).opcode = op) and
+           ((postfix = []) or (taicpu(instr).oppostfix in postfix)) then
+          begin
+            result:=true;
+            exit;
+          end;
+      end;
     end;
 {$endif AARCH64}
 
@@ -282,9 +292,11 @@ Implementation
     end;
 
 
-  function TARMAsmOptimizer.RedundantMovProcess(var p: tai;hp1: tai):boolean;
+  function TARMAsmOptimizer.RedundantMovProcess(var p: tai; var hp1: tai):boolean;
     var
       I: Integer;
+      current_hp, next_hp: tai;
+      LDRChange: Boolean;
     begin
       Result:=false;
       {
@@ -300,58 +312,281 @@ Implementation
       }
       if (taicpu(p).ops = 2) and
          (taicpu(p).oper[1]^.typ = top_reg) and
-         (taicpu(p).oppostfix = PF_NONE) and
+         (taicpu(p).oppostfix = PF_NONE) then
+        begin
 
-         MatchInstruction(hp1, [A_ADD, A_ADC,
+          if
+            MatchInstruction(hp1, [A_ADD, A_ADC,
 {$ifdef ARM}
-                                A_RSB, A_RSC,
+                                   A_RSB, A_RSC,
 {$endif ARM}
-                                A_SUB, A_SBC,
-                                A_AND, A_BIC, A_EOR, A_ORR, A_MOV, A_MVN],
-                          [taicpu(p).condition], []) and
-         { MOV and MVN might only have 2 ops }
-         (taicpu(hp1).ops >= 2) and
-         MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) and
-         (taicpu(hp1).oper[1]^.typ = top_reg) and
-         (
-           (taicpu(hp1).ops = 2) or
-           (taicpu(hp1).oper[2]^.typ in [top_reg, top_const, top_shifterop])
-         ) and
+                                   A_SUB, A_SBC,
+                                   A_AND, A_BIC, A_EOR, A_ORR, A_MOV, A_MVN],
+                             [taicpu(p).condition], []) and
+            { MOV and MVN might only have 2 ops }
+            (taicpu(hp1).ops >= 2) and
+            MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) and
+            (taicpu(hp1).oper[1]^.typ = top_reg) and
+            (
+              (taicpu(hp1).ops = 2) or
+              (taicpu(hp1).oper[2]^.typ in [top_reg, top_const, top_shifterop])
+            ) and
 {$ifdef AARCH64}
-         (taicpu(p).oper[1]^.reg<>NR_SP) and
+            (taicpu(p).oper[1]^.reg<>NR_SP) and
 {$endif AARCH64}
-         not(RegUsedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
-        begin
-        { When we get here we still don't know if the registers match }
-          for I:=1 to 2 do
-            {
-              If the first loop was successful p will be replaced with hp1.
-              The checks will still be ok, because all required information
-              will also be in hp1 then.
-            }
-            if (taicpu(hp1).ops > I) and
-               MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[I]^.reg)
+            not(RegUsedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
+            begin
+              { When we get here we still don't know if the registers match }
+              for I:=1 to 2 do
+                {
+                  If the first loop was successful p will be replaced with hp1.
+                  The checks will still be ok, because all required information
+                  will also be in hp1 then.
+                }
+                if (taicpu(hp1).ops > I) and
+                   MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[I]^.reg)
 {$ifdef ARM}
-               { prevent certain combinations on thumb(2), this is only a safe approximation }
-               and (not(GenerateThumbCode or GenerateThumb2Code) or
-                ((getsupreg(taicpu(p).oper[1]^.reg)<>RS_R13) and
-                 (getsupreg(taicpu(p).oper[1]^.reg)<>RS_R15)))
+                   { prevent certain combinations on thumb(2), this is only a safe approximation }
+                   and (not(GenerateThumbCode or GenerateThumb2Code) or
+                    ((getsupreg(taicpu(p).oper[1]^.reg)<>RS_R13) and
+                     (getsupreg(taicpu(p).oper[1]^.reg)<>RS_R15)))
 {$endif ARM}
 
-               then
-              begin
-                DebugMsg('Peephole RedundantMovProcess done', hp1);
-                taicpu(hp1).oper[I]^.reg := taicpu(p).oper[1]^.reg;
-                if p<>hp1 then
+                then
+                  begin
+                    DebugMsg('Peephole RedundantMovProcess done', hp1);
+                    taicpu(hp1).oper[I]^.reg := taicpu(p).oper[1]^.reg;
+                    if p<>hp1 then
+                      begin
+                        asml.remove(p);
+                        p.free;
+                        p:=hp1;
+                        Result:=true;
+                      end;
+                  end;
+
+              if Result then Exit;
+            end
+          { Change:                   Change:
+              mov     r1, r0            mov     r1, r0
+              ...                       ...
+              ldr/str r2, [r1, etc.]    mov     r2, r1
+            To:                       To:
+              ldr/str r2, [r0, etc.]    mov     r2, r0
+          }
+          else if (taicpu(p).condition = C_None) and (taicpu(p).oper[1]^.typ = top_reg)
+{$ifdef ARM}
+            and not (getsupreg(taicpu(p).oper[0]^.reg) in [RS_PC, RS_R14, RS_STACK_POINTER_REG])
+            and (getsupreg(taicpu(p).oper[1]^.reg) <> RS_PC)
+            { Thumb does not support references with base and index one being SP }
+            and (not(GenerateThumbCode) or (getsupreg(taicpu(p).oper[1]^.reg) <> RS_STACK_POINTER_REG))
+{$endif ARM}
+{$ifdef AARCH64}
+            and (getsupreg(taicpu(p).oper[0]^.reg) <> RS_STACK_POINTER_REG)
+{$endif AARCH64}
+            then
+            begin
+              current_hp := p;
+              TransferUsedRegs(TmpUsedRegs);
+
+              { Search local instruction block }
+              while GetNextInstruction(current_hp, next_hp) and (next_hp <> BlockEnd) and (next_hp.typ = ait_instruction) do
                 begin
-                  asml.remove(p);
-                  p.free;
-                  p:=hp1;
-                  Result:=true;
+                  UpdateUsedRegs(TmpUsedRegs, tai(current_hp.Next));
+                  LDRChange := False;
+
+                  if (taicpu(next_hp).opcode in [A_LDR,A_STR]) and (taicpu(next_hp).ops = 2) then
+                    begin
+
+                      { Change the registers from r1 to r0 }
+                      if (taicpu(next_hp).oper[1]^.ref^.base = taicpu(p).oper[0]^.reg) and
+{$ifdef ARM}
+                        { This optimisation conflicts with something and raises
+                          an access violation - needs further investigation. [Kit] }
+                        (taicpu(next_hp).opcode <> A_LDR) and
+{$endif ARM}
+                        { Don't mess around with the base register if the
+                          reference is pre- or post-indexed }
+                        (taicpu(next_hp).oper[1]^.ref^.addressmode = AM_OFFSET) then
+                        begin
+                          taicpu(next_hp).oper[1]^.ref^.base := taicpu(p).oper[1]^.reg;
+                          LDRChange := True;
+                        end;
+
+                      if taicpu(next_hp).oper[1]^.ref^.index = taicpu(p).oper[0]^.reg then
+                        begin
+                          taicpu(next_hp).oper[1]^.ref^.index := taicpu(p).oper[1]^.reg;
+                          LDRChange := True;
+                        end;
+
+                      if LDRChange then
+                        DebugMsg('Peephole Optimization: ' + std_regname(taicpu(p).oper[0]^.reg) + ' = ' + std_regname(taicpu(p).oper[1]^.reg) + ' (MovLdr2Ldr 1)', next_hp);
+
+                      { Drop out if we're dealing with pre-indexed references }
+                      if (taicpu(next_hp).oper[1]^.ref^.addressmode = AM_PREINDEXED) and
+                        (
+                          RegInRef(taicpu(p).oper[0]^.reg, taicpu(next_hp).oper[1]^.ref^) or
+                          RegInRef(taicpu(p).oper[1]^.reg, taicpu(next_hp).oper[1]^.ref^)
+                        ) then
+                        begin
+                          { Remember to update register allocations }
+                          if LDRChange then
+                            AllocRegBetween(taicpu(p).oper[1]^.reg, p, next_hp, UsedRegs);
+
+                          Break;
+                        end;
+
+                      { The register being stored can be potentially changed (as long as it's not the stack pointer) }
+                      if (taicpu(next_hp).opcode = A_STR) and (getsupreg(taicpu(p).oper[1]^.reg) <> RS_STACK_POINTER_REG) and
+                        MatchOperand(taicpu(next_hp).oper[0]^, taicpu(p).oper[0]^.reg) then
+                        begin
+                          DebugMsg('Peephole Optimization: ' + std_regname(taicpu(p).oper[0]^.reg) + ' = ' + std_regname(taicpu(p).oper[1]^.reg) + ' (MovLdr2Ldr 2)', next_hp);
+                          taicpu(next_hp).oper[0]^.reg := taicpu(p).oper[1]^.reg;
+                          LDRChange := True;
+                        end;
+
+                      if LDRChange and (getsupreg(taicpu(p).oper[1]^.reg) <> RS_STACK_POINTER_REG) then
+                        begin
+                          AllocRegBetween(taicpu(p).oper[1]^.reg, p, next_hp, UsedRegs);
+                          if (taicpu(p).oppostfix = PF_None) and
+                            (
+                              (
+                                (taicpu(next_hp).opcode = A_LDR) and
+                                MatchOperand(taicpu(next_hp).oper[0]^, taicpu(p).oper[0]^.reg)
+                              ) or
+                              not RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, next_hp, TmpUsedRegs)
+                            ) and
+                            { Double-check to see if the old registers were actually
+                              changed (e.g. if the super registers matched, but not
+                              the sizes, they won't be changed). }
+                            (
+                              (taicpu(next_hp).opcode = A_LDR) or
+                              not RegInOp(taicpu(p).oper[0]^.reg, taicpu(next_hp).oper[0]^)
+                            ) and
+                            not RegInRef(taicpu(p).oper[0]^.reg, taicpu(next_hp).oper[1]^.ref^) then
+                            begin
+                              DebugMsg('Peephole Optimization: RedundantMovProcess 2a done', p);
+                              RemoveCurrentP(p);
+                              Result := True;
+                              Exit;
+                            end;
+                        end;
+                    end
+                  else if (taicpu(next_hp).opcode = A_MOV) and (taicpu(next_hp).oppostfix = PF_None) and
+                    (taicpu(next_hp).ops = 2) then
+                    begin
+                      if MatchOperand(taicpu(next_hp).oper[0]^, taicpu(p).oper[0]^.reg) then
+                        begin
+                          { Found another mov that writes entirely to the register }
+                          if RegUsedBetween(taicpu(p).oper[0]^.reg, p, next_hp) then
+                            begin
+                              { Register was used beforehand }
+                              if MatchOperand(taicpu(next_hp).oper[1]^, taicpu(p).oper[1]^.reg) then
+                                begin
+                                  { This MOV is exactly the same as the first one.
+                                    Since none of the registers have changed value
+                                    at this point, we can remove it. }
+                                  DebugMsg('Peephole Optimization: RedundantMovProcess 3a done', next_hp);
+
+                                  if (next_hp = hp1) then
+                                    { Don't let hp1 become a dangling pointer }
+                                    hp1 := nil;
+
+                                  asml.Remove(next_hp);
+                                  next_hp.Free;
+
+                                  { We still have the original p, so we can continue optimising;
+                                   if it was -O2 or below, this instruction appeared immediately
+                                   after the first MOV, so we're technically not looking more
+                                   than one instruction ahead after it's removed! [Kit] }
+                                  Continue;
+                                end
+                              else
+                                { Register changes value - drop out }
+                                Break;
+                            end;
+
+                          { We can delete the first MOV (only if the second MOV is unconditional) }
+{$ifdef ARM}
+                          if (taicpu(p).oppostfix = PF_None) and
+                            (taicpu(next_hp).condition = C_None) then
+{$endif ARM}
+                            begin
+                              DebugMsg('Peephole Optimization: RedundantMovProcess 2b done', p);
+                              RemoveCurrentP(p);
+                              Result := True;
+                            end;
+                          Exit;
+                        end
+                      else if MatchOperand(taicpu(next_hp).oper[1]^, taicpu(p).oper[0]^.reg) then
+                        begin
+                          if MatchOperand(taicpu(next_hp).oper[0]^, taicpu(p).oper[1]^.reg)
+                            { Be careful - if the entire register is not used, removing this
+                              instruction will leave the unused part uninitialised }
+{$ifdef AARCH64}
+                            and (getsubreg(taicpu(p).oper[1]^.reg) = R_SUBQ)
+{$endif AARCH64}
+                            then
+                            begin
+                              { Instruction will become mov r1,r1 }
+                              DebugMsg('Peephole Optimization: Mov2None 2 done', next_hp);
+
+                              if (next_hp = hp1) then
+                                { Don't let hp1 become a dangling pointer }
+                                hp1 := nil;
+
+                              asml.Remove(next_hp);
+                              next_hp.Free;
+                              Continue;
+                            end;
+
+                          { Change the old register (checking the first operand again
+                            forces it to be left alone if the full register is not
+                            used, lest mov w1,w1 gets optimised out by mistake. [Kit] }
+{$ifdef AARCH64}
+                          if not MatchOperand(taicpu(next_hp).oper[0]^, taicpu(p).oper[1]^.reg) then
+{$endif AARCH64}
+                            begin
+                              DebugMsg('Peephole Optimization: ' + std_regname(taicpu(p).oper[0]^.reg) + ' = ' + std_regname(taicpu(p).oper[1]^.reg) + ' (MovMov2Mov 2)', next_hp);
+                              taicpu(next_hp).oper[1]^.reg := taicpu(p).oper[1]^.reg;
+                              AllocRegBetween(taicpu(p).oper[1]^.reg, p, next_hp, UsedRegs);
+
+                              { If this was the only reference to the old register,
+                                then we can remove the original MOV now }
+
+                              if (taicpu(p).oppostfix = PF_None) and
+                                { A bit of a hack - sometimes registers aren't tracked properly, so do not
+                                  remove if the register was apparently not allocated when its value is
+                                  first set at the MOV command (this is especially true for the stack
+                                  register). [Kit] }
+                                (getsupreg(taicpu(p).oper[1]^.reg) <> RS_STACK_POINTER_REG) and
+                                RegInUsedRegs(taicpu(p).oper[0]^.reg, UsedRegs) and
+                                not RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, next_hp, TmpUsedRegs) then
+                                begin
+                                  DebugMsg('Peephole Optimization: RedundantMovProcess 2c done', p);
+                                  RemoveCurrentP(p);
+                                  Result := True;
+                                  Exit;
+                                end;
+                            end;
+                        end;
+                    end;
+
+                  { On low optimisation settions, don't search more than one instruction ahead }
+                  if not(cs_opt_level3 in current_settings.optimizerswitches) or
+                    { Stop at procedure calls and jumps }
+                    is_calljmp(taicpu(next_hp).opcode) or
+                    { If the read register has changed value, or the MOV
+                      destination register has been used, drop out }
+                    RegInInstruction(taicpu(p).oper[0]^.reg, next_hp) or
+                    RegModifiedByInstruction(taicpu(p).oper[1]^.reg, next_hp) then
+                    Break;
+
+                  current_hp := next_hp;
                 end;
-              end;
+            end;
         end;
-      end;
+    end;
 
 
   function TARMAsmOptimizer.OptPass1UXTB(var p : tai) : Boolean;

compiler/assemble.pas

@@ -587,7 +587,7 @@ Implementation
         index: longint;
       begin
         MaybeAddLinePostfix;
-        if (cs_link_on_target in current_settings.globalswitches) then
+        if (cs_assemble_on_target in current_settings.globalswitches) then
           newline:=@target_info.newline
         else
           newline:=@source_info.newline;
@@ -623,7 +623,7 @@ Implementation
           compiler itself, especially on hardware with slow disk I/O.
           Consider this as a poor man's pipe on Amiga, because real pipe handling
           would be much more complex and error prone to implement. (KB) }
-        if (([cs_asm_extern,cs_asm_leave,cs_link_on_target] * current_settings.globalswitches) = []) then
+        if (([cs_asm_extern,cs_asm_leave,cs_assemble_on_target] * current_settings.globalswitches) = []) then
          begin
           { try to have an unique name for the .s file }
           tempFileName:=HexStr(GetProcessID shr 4,7)+ExtractFileName(owner.AsmFileName);
@@ -745,7 +745,7 @@ Implementation
       begin
 {$ifdef hasunix}
         DoPipe:=(cs_asm_pipe in current_settings.globalswitches) and
-                (([cs_asm_extern,cs_asm_leave,cs_link_on_target] * current_settings.globalswitches) = []) and
+                (([cs_asm_extern,cs_asm_leave,cs_assemble_on_target] * current_settings.globalswitches) = []) and
                 ((asminfo^.id in [as_gas,as_ggas,as_darwin,as_powerpc_xcoff,as_clang_gas,as_clang_llvm,as_solaris_as]));
 {$else hasunix}
         DoPipe:=false;
@@ -829,9 +829,9 @@ Implementation
         asmbin:=asminfo^.asmbin;
         if (af_llvm in asminfo^.flags) then
           asmbin:=asmbin+llvmutilssuffix;
-        if cs_link_on_target in current_settings.globalswitches then
+        if cs_assemble_on_target in current_settings.globalswitches then
          begin
-           { If linking on target, don't add any path PM }
+           { If assembling on target, don't add any path PM }
            FindAssembler:=utilsprefix+ChangeFileExt(asmbin,target_info.exeext);
            exit;
          end
@@ -937,7 +937,7 @@ Implementation
           Replace(result,'$ARCH',lower(cputypestr[current_settings.cputype]))
 {$endif arm}
         ;
-        if (cs_link_on_target in current_settings.globalswitches) then
+        if (cs_assemble_on_target in current_settings.globalswitches) then
          begin
            Replace(result,'$ASM',maybequoted(ScriptFixFileName(AsmFileName)));
            Replace(result,'$OBJ',maybequoted(ScriptFixFileName(ObjFileName)));
@@ -1140,7 +1140,7 @@ Implementation
 	      else if sizeof(tai_realconst(hp).value.s80val) = sizeof(single) then
 	        eextended:=float32_to_floatx80(float32(single(tai_realconst(hp).value.s80val)))
 	      else
-	        internalerror(2017091901);
+	        internalerror(2017091902);
               pdata:=@eextended;
             end;
 {$pop}
@@ -2062,7 +2062,7 @@ Implementation
 		       else if sizeof(tai_realconst(hp).value.s80val) = sizeof(single) then
 			 eextended:=float32_to_floatx80(float32(single(tai_realconst(hp).value.s80val)))
 		       else
-			 internalerror(2017091901);
+			 internalerror(2017091903);
                        pdata:=@eextended;
                      end;
            {$pop}
@@ -2101,7 +2101,7 @@ Implementation
                      else if Tai_const(hp).consttype in [aitconst_tlsgd,aitconst_tlsdesc] then
                        begin
                          if objsymend.objsection<>ObjData.CurrObjSec then
-                           Internalerror(2019092802);
+                           Internalerror(2019092803);
                          Tai_const(hp).value:=ObjData.CurrObjSec.Size-objsymend.address+Tai_const(hp).symofs;
                        end
                      else if objsymend.objsection<>objsym.objsection then

compiler/avr/aasmcpu.pas

@@ -355,7 +355,7 @@ implementation
             else
               result:=taicpu.op_reg_ref(A_LD,r,ref);
           else
-            internalerror(200401041);
+            internalerror(2004010413);
         end;
       end;
 
@@ -374,7 +374,7 @@ implementation
             else
               result:=taicpu.op_ref_reg(A_ST,ref,r);
           else
-            internalerror(200401041);
+            internalerror(2004010414);
         end;
       end;
 

compiler/avr/agavrgas.pas

@@ -93,7 +93,7 @@ unit agavrgas;
               //   internalerror(200308293);
   {$endif extdebug}
               if index<>NR_NO then
-                internalerror(2011021701)
+                internalerror(2011021707)
               else if base<>NR_NO then
                 begin
                   if addressmode=AM_PREDRECEMENT then

compiler/avr/aoptcpu.pas

@@ -423,7 +423,7 @@ Implementation
 
                             DebugMsg('Peephole LdiOp2Opi performed', p);
 
-                            RemoveCurrentP(p);
+                            result:=RemoveCurrentP(p);
                           end;
                       end;
                   end;
@@ -447,6 +447,7 @@ Implementation
                         taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset)
                       else
                         taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset-32);
+                      result:=true;
                     end;
                 A_LDS:
                   if (taicpu(p).oper[1]^.ref^.symbol=nil) and
@@ -468,6 +469,8 @@ Implementation
                         taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset)
                       else
                         taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset-32);
+
+                      result:=true;
                     end;
                 A_IN:
                     if GetNextInstruction(p,hp1) then
@@ -1101,13 +1104,16 @@ Implementation
                       mov rX,...
                       mov rX,...
                     }
-                    else if GetNextInstruction(p,hp1) and MatchInstruction(hp1,A_MOV) then
+                    else if GetNextInstruction(p,hp1) and MatchInstruction(hp1,A_MOV) and
+                      { test condition here already instead in the while loop only, else MovMov2Mov 2 might be oversight }
+                      MatchInstruction(hp1,A_MOV) and
+                      MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^) then
                       while MatchInstruction(hp1,A_MOV) and
                             MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^) and
                             { don't remove the first mov if the second is a mov rX,rX }
                             not(MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^)) do
                         begin
-                          DebugMsg('Peephole MovMov2Mov performed', p);
+                          DebugMsg('Peephole MovMov2Mov 1 performed', p);
 
                           RemoveCurrentP(p,hp1);
                           Result := True;
@@ -1115,7 +1121,28 @@ Implementation
                           GetNextInstruction(hp1,hp1);
                           if not assigned(hp1) then
                             break;
-                        end;
+                        end
+                    {
+                      This removes the second mov from
+                      mov rX,rY
+
+                      ...
+
+                      mov rX,rY
+
+                      if rX and rY are not modified in-between
+                    }
+                    else if GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[1]^.reg) and
+                      MatchInstruction(hp1,A_MOV) and
+                      MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^) and
+                      MatchOperand(taicpu(p).oper[1]^, taicpu(hp1).oper[1]^) and
+                      not(RegModifiedBetween(taicpu(p).oper[0]^.reg,p,hp1)) then
+                      begin
+                        DebugMsg('Peephole MovMov2Mov 2 performed', p);
+                        AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,UsedRegs);
+                        RemoveInstruction(hp1);
+                        Result := True;
+                      end;
                   end;
                 A_SBIC,
                 A_SBIS:

compiler/avr/cgcpu.pas

@@ -214,7 +214,7 @@ unit cgcpu;
                  list.concat(taicpu.op_reg(A_PUSH,r));
                end;
              else
-               internalerror(2002071004);
+               internalerror(2002071007);
           end;
         end;
 
@@ -224,7 +224,7 @@ unit cgcpu;
 
       begin
         if not(tcgsize2size[cgpara.Size] in [1..4]) then
-          internalerror(2014011101);
+          internalerror(2014011106);
 
         hp:=cgpara.location;
 
@@ -268,7 +268,7 @@ unit cgcpu;
         tmpreg: TRegister;
       begin
         if not(tcgsize2size[paraloc.Size] in [1..4]) then
-          internalerror(2014011101);
+          internalerror(2014011107);
 
         hp:=paraloc.location;
 
@@ -302,7 +302,7 @@ unit cgcpu;
                   hp:=hp^.Next;
                 end;
               else
-                internalerror(2002071004);
+                internalerror(2002071008);
             end;
           end;
       end;
@@ -955,7 +955,7 @@ unit cgcpu;
                              list.concat(taicpu.op_reg(A_ROL,reg))
                            end;
                          else
-                           internalerror(2011030901);
+                           internalerror(2011030903);
                        end;
                        if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
                          begin
@@ -971,7 +971,7 @@ unit cgcpu;
                                  OP_SAR:
                                    list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-i)));
                                  else
-                                   internalerror(2011030902);
+                                   internalerror(2011030904);
                                end;
                            end;
                          end;
@@ -1098,7 +1098,7 @@ unit cgcpu;
         Result:=ref;
 
          if ref.addressmode<>AM_UNCHANGED then
-           internalerror(2011021701);
+           internalerror(2011021705);
 
         { Be sure to have a base register }
         if (ref.base=NR_NO) then
@@ -1248,7 +1248,7 @@ unit cgcpu;
            QuickRef:=true;
 
          if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
-           internalerror(2011021307);
+           internalerror(2011021303);
 
          conv_done:=false;
          if tosize<>fromsize then
@@ -1469,7 +1469,7 @@ unit cgcpu;
            QuickRef:=true;
 
          if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
-           internalerror(2011021307);
+           internalerror(2011021304);
 
          conv_done:=false;
          if tosize<>fromsize then
@@ -2362,7 +2362,7 @@ unit cgcpu;
         tmpref : treference;
       begin
          if ref.addressmode<>AM_UNCHANGED then
-           internalerror(2011021701);
+           internalerror(2011021706);
 
         if assigned(ref.symbol) or (ref.offset<>0) then
           begin
@@ -2530,7 +2530,7 @@ unit cgcpu;
             SrcQuickRef:=false;
             DestQuickRef:=false;
             if ((CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) and
-              not((source.Base=NR_NO) and (source.Index=NR_NO) and (source.symbol=nil) and (source.Offset in [0..192-len]))) or
+              not((source.Base=NR_NO) and (source.Index=NR_NO) and (source.Offset in [0..192-len]))) or
               (
                  not((source.addressmode=AM_UNCHANGED) and
                      (source.symbol=nil) and
@@ -2552,7 +2552,7 @@ unit cgcpu;
               end;
 
             if ((CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) and
-              not((dest.Base=NR_NO) and (dest.Index=NR_NO) and (dest.symbol=nil) and (dest.Offset in [0..192-len]))) or
+              not((dest.Base=NR_NO) and (dest.Index=NR_NO) and (dest.Offset in [0..192-len]))) or
               (
                  not((dest.addressmode=AM_UNCHANGED) and
                    (dest.symbol=nil) and

compiler/avr/cpupara.pas

@@ -58,7 +58,7 @@ unit cpupara;
     function tcpuparamanager.get_volatile_registers_int(calloption : tproccalloption):tcpuregisterset;
       begin
         if CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype] then
-          result:=VOLATILE_INTREGISTERS-[RS_R18,RS_R19]
+          result:=VOLATILE_INTREGISTERS-[RS_R0,RS_R1,RS_R18,RS_R19]
         else
           result:=VOLATILE_INTREGISTERS;
       end;
@@ -555,7 +555,7 @@ unit cpupara;
               end;
           end
         else
-          internalerror(200410231);
+          internalerror(2004102305);
       end;
 
 begin

compiler/avr/navrmat.pas

@@ -166,7 +166,7 @@ implementation
           shln: op:=OP_SHL;
           shrn: op:=OP_SHR;
           else
-            internalerror(2013120102);
+            internalerror(2013120109);
         end;
         opsize:=left.location.size;
         opdef:=left.resultdef;

compiler/avr/raavrgas.pas

@@ -415,7 +415,7 @@ Unit raavrgas;
                     OPR_REFERENCE :
                       inc(oper.opr.ref.offset,l);
                     else
-                      internalerror(200309202);
+                      internalerror(2003092012);
                   end;
                   Consume(AS_RPAREN);
                 end
@@ -499,7 +499,7 @@ Unit raavrgas;
                        OPR_REFERENCE :
                          inc(oper.opr.ref.offset,l);
                        else
-                         internalerror(200309202);
+                         internalerror(2003092013);
                      end;
                    end
                end;

compiler/cepiktimer.pas

@@ -25,6 +25,7 @@
 {$define epiktimer:=cepiktimer}
 { do not depend on the classes unit }
 {$DEFINE NOCLASSES}
+
 { include the original file }
 {$i ../../epiktimer/epiktimer.pas}
 

compiler/cg64f32.pas

@@ -705,7 +705,7 @@ unit cg64f32;
           LOC_CONSTANT :
             cg.a_load_const_reg(list,OS_32,longint(hi(l.value64)),reg);
           else
-            internalerror(200203244);
+            internalerror(2002032411);
         end;
       end;
 

compiler/cgbase.pas

@@ -261,10 +261,22 @@ interface
         R_SUBFLAGINTERRUPT, { = 21; Interrupt enable flag }
         R_SUBFLAGDIRECTION, { = 22; Direction flag }
 {$endif Z80}
-        R_SUBMM8B,          { = 23; for part of v regs on aarch64 }
-        R_SUBMM16B,         { = 24; for part of v regs on aarch64 }
         { subregisters for the metadata register (llvm) }
-        R_SUBMETASTRING     { = 25 }
+        R_SUBMETASTRING    { = 23 }
+{$ifdef aarch64}
+        , R_SUBMM8B          { = 24; for arrangement of v regs on aarch64 }
+        , R_SUBMM16B         { = 25; for arrangement of v regs on aarch64 }
+        , R_SUBMM4H          { = 26; for arrangement of v regs on aarch64 }
+        , R_SUBMM8H          { = 27; for arrangement of v regs on aarch64 }
+        , R_SUBMM2S          { = 28; for arrangement of v regs on aarch64 }
+        , R_SUBMM4S          { = 29; for arrangement of v regs on aarch64 }
+        , R_SUBMM1D          { = 30; for arrangement of v regs on aarch64 }
+        , R_SUBMM2D          { = 31; for arrangement of v regs on aarch64 }
+        , R_SUBMMB1          { = 32; for arrangement of v regs on aarch64; for use with ldN/stN }
+        , R_SUBMMH1          { = 33; for arrangement of v regs on aarch64; for use with ldN/stN }
+        , R_SUBMMS1          { = 34; for arrangement of v regs on aarch64; for use with ldN/stN }
+        , R_SUBMMD1          { = 35; for arrangement of v regs on aarch64; for use with ldN/stN }
+{$endif aarch64}
       );
       TSubRegisterSet = set of TSubRegister;
 
@@ -730,8 +742,30 @@ implementation
             result:=result+'my';
           R_SUBMMZ:
             result:=result+'mz';
+{$ifdef aarch64}
           R_SUBMM8B:
             result:=result+'m8b';
+          R_SUBMM16B:
+            result:=result+'m16b';
+          R_SUBMM4H:
+            result:=result+'m4h';
+          R_SUBMM8H:
+            result:=result+'m8h';
+          R_SUBMM2S:
+            result:=result+'m2s';
+          R_SUBMM4S:
+            result:=result+'m4s';
+          R_SUBMM2D:
+            result:=result+'m2d';
+          R_SUBMMB1:
+            result:=result+'mb1';
+          R_SUBMMH1:
+            result:=result+'mh1';
+          R_SUBMMS1:
+            result:=result+'ms1';
+          R_SUBMMD1:
+            result:=result+'md1';
+{$endif}
           else
             internalerror(200308252);
         end;

compiler/cgobj.pas

@@ -586,7 +586,8 @@ implementation
     uses
        globals,systems,fmodule,
        verbose,paramgr,symsym,symtable,
-       tgobj,cutils,procinfo;
+       tgobj,cutils,procinfo,
+       cpuinfo;
 
 {*****************************************************************************
                             basic functionallity
@@ -1427,7 +1428,7 @@ implementation
                        OS_M8..OS_M512:
                          a_loadmm_reg_reg(list,paraloc.size,paraloc.size,paraloc.register,reg,nil);
                        else
-                         internalerror(2010053102);
+                         internalerror(2010053106);
                      end;
                    end;
                  else
@@ -1464,7 +1465,7 @@ implementation
                end;
              end;
            else
-             internalerror(2002081302);
+             internalerror(2002081303);
          end;
       end;
 
@@ -1997,7 +1998,12 @@ implementation
         tmpreg : tregister;
         tmpref : treference;
       begin
-        if assigned(ref.symbol) then
+        if assigned(ref.symbol)
+          { for avrtiny, the code generator generates a ref which is Z relative and while using it,
+            Z is changed, so the following code breaks }
+          {$ifdef avr}
+            and not((CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) or (tcgsize2size[size]=1))
+          {$endif avr} then
           begin
             tmpreg:=getaddressregister(list);
             a_loadaddr_ref_reg(list,ref,tmpreg);
@@ -2030,7 +2036,12 @@ implementation
         tmpreg : tregister;
         tmpref : treference;
       begin
-        if assigned(ref.symbol) then
+        if assigned(ref.symbol)
+          { for avrtiny, the code generator generates a ref which is Z relative and while using it,
+            Z is changed, so the following code breaks }
+          {$ifdef avr}
+            and not((CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) or (tcgsize2size[size]=1))
+          {$endif avr} then
           begin
             tmpreg:=getaddressregister(list);
             a_loadaddr_ref_reg(list,ref,tmpreg);
@@ -2086,7 +2097,7 @@ implementation
           LOC_REFERENCE, LOC_CREFERENCE:
             a_op_reg_ref(list,op,loc.size,reg,loc.reference);
           else
-            internalerror(200109061);
+            internalerror(2001090602);
         end;
       end;
 
@@ -2123,7 +2134,7 @@ implementation
               a_op_reg_ref(list,op,loc.size,tmpreg,loc.reference);
             end;
           else
-            internalerror(200109061);
+            internalerror(2001090603);
         end;
       end;
 
@@ -2265,8 +2276,13 @@ implementation
         tmpref: treference;
       begin
         if not (Op in [OP_NOT,OP_NEG]) then
-          internalerror(2020050701);
-        if assigned(ref.symbol) then
+          internalerror(2020050710);
+        if assigned(ref.symbol)
+          { for avrtiny, the code generator generates a ref which is Z relative and while using it,
+            Z is changed, so the following code breaks }
+          {$ifdef avr}
+            and not((CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) or (tcgsize2size[size]=1))
+          {$endif avr} then
           begin
             tmpreg:=getaddressregister(list);
             a_loadaddr_ref_reg(list,ref,tmpreg);
@@ -2325,7 +2341,7 @@ implementation
           LOC_REFERENCE,LOC_CREFERENCE:
             a_cmp_const_ref_label(list,size,cmp_op,a,loc.reference,l);
           else
-            internalerror(200109061);
+            internalerror(2001090604);
         end;
       end;
 
@@ -2388,7 +2404,7 @@ implementation
               a_cmp_ref_reg_label(list,size,cmp_op,ref,tmpreg,l);
             end;
           else
-            internalerror(200109061);
+            internalerror(2001090605);
         end;
       end;
 
@@ -2522,7 +2538,7 @@ implementation
           LOC_REFERENCE,LOC_CREFERENCE:
             a_loadmm_ref_cgpara(list,loc.size,loc.reference,cgpara,shuffle);
           else
-            internalerror(200310123);
+            internalerror(2003101204);
         end;
       end;
 
@@ -2616,7 +2632,7 @@ implementation
           LOC_CREFERENCE,LOC_REFERENCE:
             a_opmm_ref_reg_reg(list,op,size,loc.reference,src,dst,shuffle);
           else
-            internalerror(200312232);
+            internalerror(2003122304);
         end;
       end;
 
@@ -3163,7 +3179,7 @@ implementation
         tempreg: tregister64;
       begin
         if not (op in [OP_NOT,OP_NEG]) then
-          internalerror(2020050706);
+          internalerror(2020050713);
         tempreg.reghi:=cg.getintregister(list,OS_32);
         tempreg.reglo:=cg.getintregister(list,OS_32);
         a_load64_ref_reg(list,ref,tempreg);

compiler/comphook.pas

@@ -169,8 +169,7 @@ const
 implementation
 
   uses
-   cutils, systems, globals
-   ;
+   cutils, systems, globals, comptty;
 
 {****************************************************************************
                           Helper Routines
@@ -205,7 +204,36 @@ begin
   tostr:=hs;
 end;
 
+type
+  TOutputColor = (oc_black,oc_red,oc_green,oc_orange,og_blue,oc_magenta,oc_cyan,oc_lightgray);
 
+procedure WriteColoredOutput(var t: Text;color: TOutputColor;const s : AnsiString);
+  begin
+     if TTYCheckSupported and IsATTY(t) then
+       begin
+         case color of
+           oc_black:
+             write(t,#27'[1m'#27'[30m');
+           oc_red:
+             write(t,#27'[1m'#27'[31m');
+           oc_green:
+             write(t,#27'[1m'#27'[32m');
+           oc_orange:
+             write(t,#27'[1m'#27'[33m');
+           og_blue:
+             write(t,#27'[1m'#27'[34m');
+           oc_magenta:
+             write(t,#27'[1m'#27'[35m');
+           oc_cyan:
+             write(t,#27'[1m'#27'[36m');
+           oc_lightgray:
+             write(t,#27'[1m'#27'[37m');
+         end;
+       end;
+    write(t,s);
+    if TTYCheckSupported and IsATTY(t) then
+      write(t,#27'[0m');
+  end;
 {****************************************************************************
                           Stopping the compiler
 ****************************************************************************}
@@ -259,91 +287,102 @@ Function def_comment(Level:Longint;const s:ansistring):boolean;
 const
   rh_errorstr   = 'error:';
   rh_warningstr = 'warning:';
+
+  procedure WriteMsgTypeColored(var t : text;const s : AnsiString);
+    begin
+      case (status.verbosity and Level) of
+        V_Warning:
+          WriteColoredOutput(t,oc_magenta,s);
+        V_Error,
+        V_Fatal:
+          WriteColoredOutput(t,oc_red,s);
+        else
+          write(t,s);
+      end;
+    end;
+
 var
-  hs : ansistring;
-  hs2 : ansistring;
+  hs2,
+  MsgTypeStr,
+  MsgLocStr,
+  MsgTimeStr: AnsiString;
 begin
   def_comment:=false; { never stop }
-  hs:='';
+  MsgTypeStr:='';
+  MsgLocStr:='';
+  MsgTimeStr:='';
   if not(status.use_gccoutput) then
     begin
       if (status.verbosity and Level)=V_Hint then
-        hs:=hintstr;
+        MsgTypeStr:=hintstr;
       if (status.verbosity and Level)=V_Note then
-        hs:=notestr;
+        MsgTypeStr:=notestr;
       if (status.verbosity and Level)=V_Warning then
-        hs:=warningstr;
+        MsgTypeStr:=warningstr;
       if (status.verbosity and Level)=V_Error then
-        hs:=errorstr;
+        MsgTypeStr:=errorstr;
       if (status.verbosity and Level)=V_Fatal then
-        hs:=fatalstr;
+        MsgTypeStr:=fatalstr;
       if (status.verbosity and Level)=V_Used then
-        hs:=PadSpace('('+status.currentmodule+')',10);
+        MsgTypeStr:=PadSpace('('+status.currentmodule+')',10);
     end
   else
     begin
       if (status.verbosity and Level)=V_Hint then
-        hs:=rh_warningstr;
+        MsgTypeStr:=rh_warningstr;
       if (status.verbosity and Level)=V_Note then
-        hs:=rh_warningstr;
+        MsgTypeStr:=rh_warningstr;
       if (status.verbosity and Level)=V_Warning then
-        hs:=rh_warningstr;
+        MsgTypeStr:=rh_warningstr;
       if (status.verbosity and Level)=V_Error then
-        hs:=rh_errorstr;
+        MsgTypeStr:=rh_errorstr;
       if (status.verbosity and Level)=V_Fatal then
-        hs:=rh_errorstr;
+        MsgTypeStr:=rh_errorstr;
     end;
   { Generate line prefix }
   if ((Level and V_LineInfo)=V_LineInfo) and
      (status.currentsource<>'') and
      (status.currentline>0) then
-   begin
-     {$ifndef macos}
-     { Adding the column should not confuse RHIDE,
-     even if it does not yet use it PM
-     but only if it is after error or warning !! PM }
-     if status.currentcolumn>0 then
-      begin
-        if status.use_gccoutput then
-          hs:=gccfilename(status.currentsource)+':'+tostr(status.currentline)+':'+tostr(status.currentcolumn)+': '+hs+' '+s
-        else
-          begin
-            hs:=status.currentsource+'('+tostr(status.currentline)+
-              ','+tostr(status.currentcolumn)+') '+hs+' '+s;
-          end;
-        if status.print_source_path then
-          if status.sources_avail then
-            hs:=status.currentsourcepath+hs
+    begin
+{$ifndef macos}
+      { Adding the column should not confuse RHIDE,
+      even if it does not yet use it PM
+      but only if it is after error or warning !! PM }
+      if status.currentcolumn>0 then
+        begin
+          if status.use_gccoutput then
+            MsgLocStr:=gccfilename(status.currentsource)+':'+tostr(status.currentline)+':'+tostr(status.currentcolumn)+':'
           else
-            hs:=status.currentsourceppufilename+':'+hs;
-      end
-     else
-      begin
-        if status.use_gccoutput then
-          hs:=gccfilename(status.currentsource)+': '+hs+' '+tostr(status.currentline)+': '+s
-        else
-          hs:=status.currentsource+'('+tostr(status.currentline)+') '+hs+' '+s;
-      end;
-     {$else}
-     {MPW style error}
-     if status.currentcolumn>0 then
-       hs:='File "'+status.currentsourcepath+status.currentsource+'"; Line '+tostr(status.currentline)+
-         ' #[' + tostr(status.currentcolumn) + '] ' +hs+' '+s
-     else
-       hs:='File "'+status.currentsourcepath+status.currentsource+'"; Line '+tostr(status.currentline)+' # '+hs+' '+s;
-     {$endif}
-   end
-  else
-   begin
-     if hs<>'' then
-      hs:=hs+' '+s
-     else
-      hs:=s;
-   end;
+            MsgLocStr:=status.currentsource+'('+tostr(status.currentline)+','+tostr(status.currentcolumn)+')';
+          if status.print_source_path then
+            if status.sources_avail then
+              MsgLocStr:=status.currentsourcepath+MsgLocStr
+            else
+              MsgLocStr:=status.currentsourceppufilename+':'+MsgLocStr;
+        end
+      else
+        begin
+          if status.use_gccoutput then
+            MsgLocStr:=gccfilename(status.currentsource)+':'+tostr(status.currentline)+':'
+          else
+            MsgLocStr:=status.currentsource+'('+tostr(status.currentline)+')';
+        end;
+ {$else macos}
+      { MPW style error }
+      if status.currentcolumn>0 then
+        MsgLocStr:='File "'+status.currentsourcepath+status.currentsource+'"; Line '+tostr(status.currentline)+' #[' + tostr(status.currentcolumn) + ']'
+      else
+        MsgLocStr:='File "'+status.currentsourcepath+status.currentsource+'"; Line '+tostr(status.currentline)+' # ';
+ {$endif macos}
+    end;
+  if MsgLocStr<>'' then
+    MsgLocStr:=MsgLocStr+' ';
+  if MsgTypeStr<>'' then
+    MsgTypeStr:=MsgTypeStr+' ';
   if (status.verbosity and V_TimeStamps)<>0 then
     begin
       system.str(getrealtime-starttime:0:3,hs2);
-      hs:='['+hs2+'] '+hs;
+      MsgTimeStr:='['+hs2+'] ';
     end;
 
   { Display line }
@@ -351,24 +390,30 @@ begin
      ((status.verbosity and (Level and V_LevelMask))=(Level and V_LevelMask)) then
    begin
      if status.use_stderr then
-      begin
-        writeln(stderr,hs);
-        flush(stderr);
-      end
+       begin
+         write(StdErr,MsgTimeStr+MsgLocStr);
+         WriteMsgTypeColored(StdErr,MsgTypeStr);
+         writeln(StdErr,s);
+         flush(StdErr);
+       end
      else
-      begin
-        if status.use_redir then
-         writeln(status.redirfile,hs)
-        else
-         writeln(hs);
-      end;
+       begin
+         if status.use_redir then
+           writeln(status.redirfile,MsgTimeStr+MsgLocStr+MsgTypeStr+s)
+         else
+           begin
+             write(MsgTimeStr+MsgLocStr);
+             WriteMsgTypeColored(Output,MsgTypeStr);
+             writeln(s);
+           end;
+       end;
    end;
   { include everything in the bugreport file }
   if status.use_bugreport then
-   begin
-     Write(status.reportbugfile,hexstr(level,8)+':');
-     Writeln(status.reportbugfile,hs);
-   end;
+    begin
+      Write(status.reportbugfile,hexstr(level,8)+':');
+      Writeln(status.reportbugfile,MsgTimeStr+MsgLocStr+MsgTypeStr+s);
+    end;
 end;
 
 

compiler/compinnr.pas

@@ -154,6 +154,25 @@ type
      in_fma_extended     = 135,
      in_fma_float128     = 136,
 
+     { the min/max intrinsics must follow the x86 sse
+       behaviour of min/max regarding handling
+       NaN: in case of a NaN the result is always the second
+       operand. This allows a simple translation of
+       if a>b then result:=a else result:=b;
+       statements into these intrinsics
+
+       The min/max intrinsics are not supposed to
+       be exposed to the user but only
+       used internally by the compiler/optimizer }
+     in_max_single       = 137,
+     in_max_double       = 138,
+     in_min_single       = 139,
+     in_min_double       = 140,
+     in_min_dword        = 141,
+     in_min_longint      = 142,
+     in_max_dword        = 143,
+     in_max_longint      = 144,
+
 { MMX functions }
 { these contants are used by the mmx unit }
 

compiler/comptty.pas

@@ -0,0 +1,172 @@
+{
+    This file is part of the Free Pascal compiler.
+    Copyright (c) 2020 by the Free Pascal development team
+
+    This unit contains platform-specific code for checking TTY output
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit comptty;
+
+{$i fpcdefs.inc}
+
+interface
+
+function IsATTY(var t : text) : Boolean;
+
+const
+(* This allows compile-time removal of the colouring functionality under not supported platforms *)
+{$if defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM)}
+  TTYCheckSupported = true;
+{$else defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM)}
+  TTYCheckSupported = false;
+{$endif defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM)}
+
+
+implementation
+
+{$ifdef linux}
+  uses
+   termio;
+{$endif linux}
+{$ifdef mswindows}
+  uses
+   windows;
+{$endif mswindows}
+{$ifdef os2}
+  uses
+   doscalls;
+{$endif os2}
+{$if defined(GO32V2) or defined(WATCOM)}
+  uses
+   dos;
+{$endif defined(GO32V2) or defined(WATCOM)}
+
+const
+  CachedIsATTY : Boolean = false;
+  IsATTYValue : Boolean = false;
+
+{$ifdef linux}
+function LinuxIsATTY(var t : text) : Boolean; inline;
+begin
+  LinuxIsATTY:=termio.IsATTY(t)=1;
+end;
+{$endif linux}
+
+{$ifdef MSWINDOWS}
+const
+  ENABLE_VIRTUAL_TERMINAL_PROCESSING = $0004;
+
+function WindowsIsATTY(var t : text) : Boolean; inline;
+const
+  dwMode: dword = 0;
+begin
+  WindowsIsATTY := false;
+  if GetConsoleMode(TextRec(t).handle, dwMode) then
+   begin
+    dwMode := dwMode or ENABLE_VIRTUAL_TERMINAL_PROCESSING;
+    if SetConsoleMode(TextRec(t).handle, dwMode) then
+                                     WindowsIsATTY := true;
+   end;
+end;
+{$endif MSWINDOWS}
+
+{$IFDEF OS2}
+function OS2IsATTY(var t : text) : Boolean; inline;
+var
+  HT, Attr: cardinal;
+ {$IFDEF EMX}
+  OK: boolean;
+ {$ENDIF EMX}
+const
+  dhDevice = 1;
+begin
+ {$IFDEF EMX}
+  if os_mode = osOS2 then
+    begin
+ {$ENDIF EMX}
+      OS2IsATTY := (DosQueryHType (TextRec (T).Handle, HT, Attr) = 0)
+                                                           and (HT = dhDevice);
+ {$IFDEF EMX}
+    end
+  else
+    begin
+      OK := false;
+{$ASMMODE INTEL}
+      asm
+        mov ebx, TextRec (T).Handle
+        mov eax, 4400h
+        call syscall
+        jc @IsDevEnd
+        test edx, 80h           { bit 7 is set if it is a device or a pipe }
+        jz @IsDevEnd
+        mov eax, 1A00h          { Check ANSI.SYS availability }
+        int 2Fh
+        inc al                  { If it was FFh, then OK }
+        jnz @IsDevEnd
+        mov OK, true
+@IsDevEnd:
+      end;
+    OS2IsATTY := OK;
+  end;
+ {$ENDIF EMX}
+end;
+{$ENDIF OS2}
+
+{$if defined(GO32V2) or defined(WATCOM)}
+function DosIsATTY(var t : text) : Boolean; inline;
+var
+  Regs: Registers;
+begin
+  Regs.EBX := TextRec (T).Handle;
+  Regs.EAX := $4400;
+  MsDos (Regs);
+  if (Regs.Flags and FCarry <> 0) or (Regs.EDX and $80 = 0) then
+{ bit 7 is set if it is a device or a pipe }
+    DosIsATTY := false
+  else
+    begin
+      Regs.EAX := $1A00;             { Check ANSI.SYS availability }
+      Intr ($2F, Regs);
+      DosIsATTY := Regs.AL = $FF;    { If it was FFh, then OK }
+    end;
+end;
+{$endif defined(GO32V2) or defined(WATCOM)}
+
+function IsATTY(var t : text) : Boolean;
+begin
+  if not(CachedIsATTY) then
+    begin
+(* If none of the supported values is defined, false is returned by default. *)
+{$ifdef linux}
+      IsATTYValue:=LinuxIsATTY(t);
+{$endif linux}
+{$ifdef MSWINDOWS}
+      IsATTYValue:=WindowsIsATTY(t);
+{$endif MSWINDOWS}
+{$ifdef OS2}
+      IsATTYValue:=OS2IsATTY(t);
+{$endif OS2}
+{$if defined(GO32V2) or defined(WATCOM)}
+      IsATTYValue:=DosIsATTY(t);
+{$endif defined(GO32V2) or defined(WATCOM)}
+      CachedIsATTY:=true;
+    end;
+  Result:=IsATTYValue;
+end;
+
+end.

compiler/cstreams.pas

@@ -104,11 +104,11 @@ type
 
   TCCustomFileStream = class(TCStream)
   protected
-    FFileName : String;
+    FFileName : AnsiString;
   public
-    constructor Create(const AFileName: string;{shortstring!} Mode: Word); virtual; abstract;
+    constructor Create(const AFileName: AnsiString; Mode: Word); virtual; abstract;
     function EOF: boolean; virtual; abstract;
-    property FileName : String Read FFilename;
+    property FileName : AnsiString Read FFilename;
   end;
 
 { TFileStream class }
@@ -119,7 +119,7 @@ type
   protected
     procedure SetSize(NewSize: Longint); override;
   public
-    constructor Create(const AFileName: string; Mode: Word); override;
+    constructor Create(const AFileName: AnsiString; Mode: Word); override;
     destructor Destroy; override;
     function Read(var Buffer; Count: Longint): Longint; override;
     function Write(const Buffer; Count: Longint): Longint; override;
@@ -378,7 +378,7 @@ implementation
 {*                             TCFileStream                                  *}
 {****************************************************************************}
 
-constructor TCFileStream.Create(const AFileName: string; Mode: Word);
+constructor TCFileStream.Create(const AFileName: AnsiString; Mode: Word);
 var
   oldfilemode : byte;
 begin

compiler/cutils.pas

@@ -92,10 +92,11 @@ interface
     function lower(const s : ansistring) : ansistring;
     function rpos(const needle: char; const haystack: shortstring): longint; overload;
     function rpos(const needle: shortstring; const haystack: shortstring): longint; overload;
-    function trimbspace(const s:string):string;
     function trimspace(const s:string):string;
+    function trimspace(const s:AnsiString):AnsiString;
     function space (b : longint): string;
     function PadSpace(const s:string;len:longint):string;
+    function PadSpace(const s:AnsiString;len:longint):AnsiString;
     function GetToken(var s:string;endchar:char):string;
     procedure uppervar(var s : string);
     function realtostr(e:extended):string;{$ifdef USEINLINE}inline;{$endif}
@@ -769,23 +770,24 @@ implementation
       end;
 
 
-    function trimbspace(const s:string):string;
+    function trimspace(const s:string):string;
     {
-      return s with all leading spaces and tabs removed
+      return s with all leading and ending spaces and tabs removed
     }
       var
         i,j : longint;
       begin
-        j:=1;
         i:=length(s);
+        while (i>0) and (s[i] in [#9,' ']) do
+         dec(i);
+        j:=1;
         while (j<i) and (s[j] in [#9,' ']) do
          inc(j);
-        trimbspace:=Copy(s,j,i-j+1);
+        trimspace:=Copy(s,j,i-j+1);
       end;
 
 
-
-    function trimspace(const s:string):string;
+    function trimspace(const s:AnsiString):AnsiString;
     {
       return s with all leading and ending spaces and tabs removed
     }
@@ -825,6 +827,18 @@ implementation
       end;
 
 
+    function PadSpace(const s:AnsiString;len:longint):AnsiString;
+    {
+      return s with spaces add to the end
+    }
+      begin
+         if length(s)<len then
+          PadSpace:=s+Space(len-length(s))
+         else
+          PadSpace:=s;
+      end;
+
+
     function GetToken(var s:string;endchar:char):string;
       var
         i : longint;

compiler/dbgdwarf.pas

@@ -1309,7 +1309,7 @@ implementation
             if data[i].VType<>vtInteger then
               internalerror(200601261);
             if data[i+1].VType<>vtInteger then
-              internalerror(200601261);
+              internalerror(2006012602);
             append_attribute(tdwarf_attribute(data[i].VInteger),tdwarf_form(data[i+1].VInteger),data[i+2]);
             inc(i,3);
           end;
@@ -2552,7 +2552,7 @@ implementation
                 currdef:=tarraydef(currdef).elementdef;
               end;
             else
-              internalerror(2009031401);
+              internalerror(2009031403);
           end;
           symlist:=symlist^.next;
         until not assigned(symlist);

compiler/dbgstabs.pas

@@ -480,6 +480,9 @@ implementation
       begin
         if tsym(p).typ = procsym then
          begin
+           if (sp_generic_dummy in tsym(p).symoptions) and
+               (tprocsym(p).procdeflist.count=0) then
+             exit;
            pd :=tprocdef(tprocsym(p).ProcdefList[0]);
            if (po_virtualmethod in pd.procoptions) and
                not is_objectpascal_helper(pd.struct) then
@@ -1561,7 +1564,7 @@ implementation
                   ss:=sym_stabstr_evaluate(sym,'"${name}:$1",'+base_stabs_str(paravarsymref_stab,'0','${line}','$2'),[c+st,getoffsetstr(sym.localloc.reference)])
                 end;
               else
-                internalerror(2003091814);
+                internalerror(2003091805);
             end;
           end;
         write_sym_stabstr(list,sym,ss);

compiler/defcmp.pas

@@ -843,11 +843,11 @@ implementation
                          { and conversion to float is favoured)                }
                          doconv:=tc_int_2_real;
                          if is_extended(def_to) then
-                           eq:=te_convert_l2
+                           eq:=te_convert_l1
                          else if is_double(def_to) then
-                           eq:=te_convert_l3
+                           eq:=te_convert_l2
                          else if is_single(def_to) then
-                           eq:=te_convert_l4
+                           eq:=te_convert_l3
                          else
                            eq:=te_convert_l2;
                        end;
@@ -2622,8 +2622,9 @@ implementation
     function equal_genfunc_paradefs(fwdef,currdef:tdef;fwpdst,currpdst:tsymtable): boolean;
       begin
         result:=false;
-        if (sp_generic_para in fwdef.typesym.symoptions) and
-            (sp_generic_para in currdef.typesym.symoptions) and
+        { for open array parameters, typesym might not be assigned }
+        if assigned(fwdef.typesym) and (sp_generic_para in fwdef.typesym.symoptions) and
+           assigned(currdef.typesym) and (sp_generic_para in currdef.typesym.symoptions) and
             (fwdef.owner=fwpdst) and
             (currdef.owner=currpdst) then
           begin

compiler/defutil.pas

@@ -229,6 +229,9 @@ interface
     {# Returns true, if def is a currency type }
     function is_currency(def : tdef) : boolean;
 
+    {# Returns true, if def is a comp type (handled by the fpu) }
+    function is_fpucomp(def : tdef) : boolean;
+
     {# Returns true, if def is a single type }
     function is_single(def : tdef) : boolean;
 
@@ -265,9 +268,18 @@ interface
     {# Returns true, if def is a 64 bit integer type }
     function is_64bitint(def : tdef) : boolean;
 
-    {# Returns true, if def is a 64 bit type }
+    {# Returns true, if def is a 64 bit signed integer type }
+    function is_s64bitint(def : tdef) : boolean;
+
+    {# Returns true, if def is a 64 bit ordinal type }
     function is_64bit(def : tdef) : boolean;
 
+    { returns true, if def is a longint type }
+    function is_s32bitint(def : tdef) : boolean;
+
+    { returns true, if def is a dword type }
+    function is_u32bitint(def : tdef) : boolean;
+
     { true, if def1 and def2 are both integers of the same bit size and sign }
     function are_equal_ints(def1, def2: tdef): boolean;
 
@@ -402,6 +414,12 @@ implementation
       end;
 
 
+    function is_fpucomp(def: tdef): boolean;
+      begin
+        result:=(def.typ=floatdef) and
+           (tfloatdef(def).floattype=s64comp);
+      end;
+
     { returns true, if def is a single type }
     function is_single(def : tdef) : boolean;
       begin
@@ -1003,6 +1021,7 @@ implementation
          result:=(def.typ=orddef) and (torddef(def).ordtype in [u32bit,s32bit,pasbool32,bool32bit])
       end;
 
+
     { true, if def is a 64 bit int type }
     function is_64bitint(def : tdef) : boolean;
       begin
@@ -1010,6 +1029,12 @@ implementation
       end;
 
 
+    function is_s64bitint(def: tdef): boolean;
+      begin
+        is_s64bitint:=(def.typ=orddef) and (torddef(def).ordtype=s64bit)
+      end;
+
+
     { true, if def is a 64 bit type }
     function is_64bit(def : tdef) : boolean;
       begin
@@ -1017,6 +1042,22 @@ implementation
       end;
 
 
+    { returns true, if def is a longint type }
+    function is_s32bitint(def : tdef) : boolean;
+      begin
+        result:=(def.typ=orddef) and
+          (torddef(def).ordtype=s32bit);
+      end;
+
+
+    { returns true, if def is a dword type }
+    function is_u32bitint(def : tdef) : boolean;
+      begin
+        result:=(def.typ=orddef) and
+          (torddef(def).ordtype=u32bit);
+      end;
+
+
     { true, if def1 and def2 are both integers of the same bit size and sign }
     function are_equal_ints(def1, def2: tdef): boolean;
       begin
@@ -1358,7 +1399,10 @@ implementation
                    (tarraydef(p).elementdef.typ=floatdef) and
                    (
                     (tarraydef(p).lowrange=0) and
-                    (tarraydef(p).highrange=3) and
+                    ((tarraydef(p).highrange=3) or
+                     (UseAVX and (tarraydef(p).highrange=7)) or
+                     (UseAVX512 and (tarraydef(p).highrange=15))
+                    ) and
                     (tfloatdef(tarraydef(p).elementdef).floattype=s32real)
                    )
                   ) or
@@ -1367,7 +1411,10 @@ implementation
                    (tarraydef(p).elementdef.typ=floatdef) and
                    (
                     (tarraydef(p).lowrange=0) and
-                    (tarraydef(p).highrange=1) and
+                    ((tarraydef(p).highrange=1) or
+                     (UseAVX and (tarraydef(p).highrange=3)) or
+                     (UseAVX512 and (tarraydef(p).highrange=7))
+                    )and
                     (tfloatdef(tarraydef(p).elementdef).floattype=s64real)
                    )
                   ) {or

compiler/dirparse.pas

@@ -99,6 +99,12 @@ implementation
            end
           else if tok='RECORDMAX' then
            b.recordalignmax:=l
+
+{          disabled for now as - as Jonas pointed out - this
+           is a matter of abi
+
+           else if tok='MAXCRECORD' then
+           b.maxCrecordalign:=l }
           else { Error }
            UpdateAlignmentStr:=false;
         until false;

compiler/entfile.pas

@@ -1400,7 +1400,7 @@ begin
     for i:=low(arr) to high(arr) do
       arr[i]:=reverse_byte(arr[i]);
 {$ifdef DEBUG_PPU}
-  for i:=0 to 3 do
+  for i:=low(arr) to high(arr) do
     ppu_log_val('byte['+tostr(i)+']=$'+hexstr(arr[i],2));
   dec_log_level;
 {$endif}
@@ -1871,7 +1871,7 @@ procedure tentryfile.putset(const arr: array of byte);
 {$endif}
     putdata(arr,sizeof(arr));
 {$ifdef DEBUG_PPU}
-  for i:=0 to 31 do
+  for i:=0 to sizeof(arr)-1 do
     ppu_log_val('byte['+tostr(i)+']=$'+hexstr(arr[i],2));
   dec_log_level;
 {$endif}

compiler/fpcdefs.inc

@@ -2,7 +2,9 @@
 {$asmmode default}
 {$H-}
 {$goto on}
-{$inline on}
+{$ifndef DISABLE_INLINE}
+  {$inline on}
+{$endif}
 {$interfaces corba}
 
 { This reduces the memory requirements a lot }
@@ -39,7 +41,7 @@
 { This fake CPU is used to allow incorporation of globtype unit
   into utils/ppudump without any CPU specific code PM }
 {$ifdef generic_cpu}
-  {$define #cpu32bit}
+  {$define cpu32bit}
   {$define cpu32bitaddr}
   {$define cpu32bitalu}
   {$define cpuflags}
@@ -314,10 +316,6 @@
   {$define cpucapabilities}
 {$endif z80}
 
-{$IFDEF MACOS}
-{$DEFINE USE_FAKE_SYSUTILS}
-{$ENDIF MACOS}
-
 {$ifdef riscv64}
   {$define riscv}
   {$define cpu64bit}

compiler/fpcp.pas

@@ -326,7 +326,7 @@ implementation
       if pcpfile.readentry<>ibpackagefiles then
         begin
           message(package_f_pcp_read_error);
-          internalerror(424242);
+          internalerror(2020100818);
         end;
       pplfilename:=pcpfile.getstring;
 
@@ -342,13 +342,13 @@ implementation
       if pcpfile.readentry<>ibstartcontained then
         begin
           message(package_f_pcp_read_error);
-          internalerror(424242);
+          internalerror(2020100819);
         end;
       cnt:=pcpfile.getlongint;
       if pcpfile.readentry<>ibendcontained then
         begin
           message(package_f_pcp_read_error);
-          internalerror(424242);
+          internalerror(2020100820);
         end;
       for i:=0 to cnt-1 do
         begin

compiler/fppu.pas

@@ -51,10 +51,15 @@ interface
           comments   : TCmdStrList;
           nsprefix   : TCmdStr; { Namespace prefix the unit was found with }
 {$ifdef Test_Double_checksum}
-          crc_array  : pointer;
-          crc_size   : longint;
-          crc_array2 : pointer;
-          crc_size2  : longint;
+          interface_read_crc_index,
+          interface_write_crc_index,
+          indirect_read_crc_index,
+          indirect_write_crc_index,
+          implementation_read_crc_index,
+          implementation_write_crc_index : cardinal;
+          interface_crc_array,
+          indirect_crc_array,
+          implementation_crc_array  : pointer;
 {$endif def Test_Double_checksum}
           constructor create(LoadedFrom:TModule;const amodulename: string; const afilename:TPathStr;_is_unit:boolean);
           destructor destroy;override;
@@ -1511,16 +1516,41 @@ var
          if (cs_fp_emulation in current_settings.moduleswitches) then
            headerflags:=headerflags or uf_fpu_emulation;
 {$endif cpufpemu}
-{$ifdef Test_Double_checksum_write}
-         Assign(CRCFile,ppufilename+'.IMP');
-         Rewrite(CRCFile);
-{$endif def Test_Double_checksum_write}
-
          { create new ppufile }
          ppufile:=tcompilerppufile.create(ppufilename);
          if not ppufile.createfile then
           Message(unit_f_ppu_cannot_write);
 
+{$ifdef Test_Double_checksum_write}
+         { Re-use the values collected in .INT part }
+         if assigned(interface_crc_array) then
+           begin
+             ppufile.implementation_write_crc_index:=implementation_write_crc_index;
+             ppufile.interface_write_crc_index:=interface_write_crc_index;
+             ppufile.indirect_write_crc_index:=indirect_write_crc_index;
+             if assigned(ppufile.interface_crc_array) then
+               begin
+                 dispose(ppufile.interface_crc_array);
+                 ppufile.interface_crc_array:=interface_crc_array;
+               end; 
+             if assigned(ppufile.implementation_crc_array) then
+               begin
+                 dispose(ppufile.implementation_crc_array);
+                 ppufile.implementation_crc_array:=implementation_crc_array;
+               end; 
+             if assigned(ppufile.indirect_crc_array) then
+               begin
+                 dispose(ppufile.indirect_crc_array);
+                 ppufile.indirect_crc_array:=indirect_crc_array;
+               end; 
+           end;
+         if FileExists(ppufilename+'.IMP',false) then
+           RenameFile(ppufilename+'.IMP',ppufilename+'.IMP-old');
+         Assign(ppufile.CRCFile,ppufilename+'.IMP');
+         Rewrite(ppufile.CRCFile);
+         Writeln(ppufile.CRCFile,'CRC in writeppu method of implementation of ',ppufilename,' defsgeneration=',defsgeneration);
+{$endif def Test_Double_checksum_write}
+
          { extra header (sub version, module flags) }
          writeextraheader;
 
@@ -1681,7 +1711,15 @@ var
          indirect_crc:=ppufile.indirect_crc;
 
 {$ifdef Test_Double_checksum_write}
-         close(CRCFile);
+         Writeln(ppufile.CRCFile,'End of implementation CRC in writeppu method of ',ppufilename,
+                 ' implementation_crc=$',hexstr(ppufile.crc,8),
+                 ' interface_crc=$',hexstr(ppufile.interface_crc,8),
+                 ' indirect_crc=$',hexstr(ppufile.indirect_crc,8),
+                 ' implementation_crc_size=',ppufile.implementation_read_crc_index,
+                 ' interface_crc_size=',ppufile.interface_read_crc_index,
+                 ' indirect_crc_size=',ppufile.indirect_read_crc_index,
+                 ' defsgeneration=',defsgeneration);
+         close(ppufile.CRCFile);
 {$endif Test_Double_checksum_write}
 
          ppufile.closefile;
@@ -1692,10 +1730,6 @@ var
 
     procedure tppumodule.getppucrc;
       begin
-{$ifdef Test_Double_checksum_write}
-         Assign(CRCFile,ppufilename+'.INT');
-         Rewrite(CRCFile);
-{$endif def Test_Double_checksum_write}
 
          { create new ppufile }
          ppufile:=tcompilerppufile.create(ppufilename);
@@ -1703,6 +1737,14 @@ var
          if not ppufile.createfile then
            Message(unit_f_ppu_cannot_write);
 
+{$ifdef Test_Double_checksum_write}
+         if FileExists(ppufilename+'.INT',false) then
+           RenameFile(ppufilename+'.INT',ppufilename+'.INT-old');
+         Assign(ppufile.CRCFile,ppufilename+'.INT');
+         Rewrite(ppufile.CRCFile);
+         Writeln(ppufile.CRCFile,'CRC of getppucrc of ',ppufilename,
+                 ' defsgeneration=',defsgeneration);
+{$endif def Test_Double_checksum_write}
          { first the (JVM) namespace }
          if assigned(namespace) then
            begin
@@ -1757,17 +1799,26 @@ var
            for ppudump when using INTFPPU define }
          ppufile.writeentry(ibendimplementation);
 
-{$ifdef Test_Double_checksum}
-         crc_array:=ppufile.crc_test;
-         ppufile.crc_test:=nil;
-         crc_size:=ppufile.crc_index2;
-         crc_array2:=ppufile.crc_test2;
-         ppufile.crc_test2:=nil;
-         crc_size2:=ppufile.crc_index2;
-{$endif Test_Double_checksum}
-
 {$ifdef Test_Double_checksum_write}
-         close(CRCFile);
+         Writeln(ppufile.CRCFile,'End of CRC of getppucrc of ',ppufilename,
+                 ' implementation_crc=$',hexstr(ppufile.crc,8),
+                 ' interface_crc=$',hexstr(ppufile.interface_crc,8),
+                 ' indirect_crc=$',hexstr(ppufile.indirect_crc,8),
+                 ' implementation_crc_size=',ppufile.implementation_write_crc_index,
+                 ' interface_crc_size=',ppufile.interface_write_crc_index,
+                 ' indirect_crc_size=',ppufile.indirect_write_crc_index,
+                 ' defsgeneration=',defsgeneration);
+         close(ppufile.CRCFile);
+         { Remember the values generated in .INT part }
+          implementation_write_crc_index:=ppufile.implementation_write_crc_index;
+          interface_write_crc_index:=ppufile.interface_write_crc_index;
+          indirect_write_crc_index:=ppufile.indirect_write_crc_index;
+          interface_crc_array:=ppufile.interface_crc_array;
+          ppufile.interface_crc_array:=nil;
+          implementation_crc_array:=ppufile.implementation_crc_array;
+          ppufile.implementation_crc_array:=nil;
+          indirect_crc_array:=ppufile.indirect_crc_array;
+          ppufile.indirect_crc_array:=nil;
 {$endif Test_Double_checksum_write}
 
          { create and write header, this will only be used
@@ -1821,11 +1872,11 @@ var
                  Message2(unit_u_recompile_crc_change,realmodulename^,pu.u.ppufilename,@queuecomment);
 {$ifdef DEBUG_UNIT_CRC_CHANGES}
                  if (pu.u.interface_crc<>pu.interface_checksum) then
-                   writeln('  intfcrc change: ',hexstr(pu.u.interface_crc,8),' <> ',hexstr(pu.interface_checksum,8))
+                   Comment(V_Normal,'  intfcrc change: '+hexstr(pu.u.interface_crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.interface_checksum,8)+' in unit '+realmodulename^)
                  else if (pu.u.indirect_crc<>pu.indirect_checksum) then
-                   writeln('  indcrc change: ',hexstr(pu.u.indirect_crc,8),' <> ',hexstr(pu.indirect_checksum,8))
+                   Comment(V_Normal,'  indcrc change: '+hexstr(pu.u.indirect_crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.indirect_checksum,8)+' in unit '+realmodulename^)
                  else
-                   writeln('  implcrc change: ',hexstr(pu.u.crc,8),' <> ',hexstr(pu.checksum,8));
+                   Comment(V_Normal,'  implcrc change: '+hexstr(pu.u.crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.checksum,8)+' in unit '+realmodulename^);
 {$endif DEBUG_UNIT_CRC_CHANGES}
                  recompile_reason:=rr_crcchanged;
                  do_compile:=true;
@@ -1877,9 +1928,9 @@ var
                   Message2(unit_u_recompile_crc_change,realmodulename^,pu.u.ppufilename+' {impl}',@queuecomment);
 {$ifdef DEBUG_UNIT_CRC_CHANGES}
                   if (pu.u.interface_crc<>pu.interface_checksum) then
-                    writeln('  intfcrc change (2): ',hexstr(pu.u.interface_crc,8),' <> ',hexstr(pu.interface_checksum,8))
+                    Comment(V_Normal,'  intfcrc change (2): '+hexstr(pu.u.interface_crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.interface_checksum,8)+' in unit '+realmodulename^)
                   else if (pu.u.indirect_crc<>pu.indirect_checksum) then
-                    writeln('  indcrc change (2): ',hexstr(pu.u.indirect_crc,8),' <> ',hexstr(pu.indirect_checksum,8));
+                    Comment(V_Normal,'  indcrc change (2): '+hexstr(pu.u.indirect_crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.indirect_checksum,8)+' in unit '+realmodulename^);
 {$endif DEBUG_UNIT_CRC_CHANGES}
                   recompile_reason:=rr_crcchanged;
                   do_compile:=true;
@@ -1933,11 +1984,11 @@ var
              begin
 {$ifdef DEBUG_UNIT_CRC_CHANGES}
                if (pu.u.interface_crc<>pu.interface_checksum) then
-                 writeln('  intfcrc change (3): ',hexstr(pu.u.interface_crc,8),' <> ',hexstr(pu.interface_checksum,8))
+                 Comment(V_Normal,'  intfcrc change (3): '+hexstr(pu.u.interface_crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.interface_checksum,8)+' in unit '+realmodulename^)
                else if (pu.u.indirect_crc<>pu.indirect_checksum) then
-                 writeln('  indcrc change (3): ',hexstr(pu.u.indirect_crc,8),' <> ',hexstr(pu.indirect_checksum,8))
+                 Comment(V_Normal,'  indcrc change (3): '+hexstr(pu.u.indirect_crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.indirect_checksum,8)+' in unit '+realmodulename^)
                else
-                 writeln('  implcrc change (3): ',hexstr(pu.u.crc,8),' <> ',hexstr(pu.checksum,8));
+                 Comment(V_Normal,'  implcrc change (3): '+hexstr(pu.u.crc,8)+' for '+pu.u.ppufilename+' <> '+hexstr(pu.checksum,8)+' in unit '+realmodulename^);
 {$endif DEBUG_UNIT_CRC_CHANGES}
                result:=true;
                exit;

compiler/generic/cpuinfo.pas

@@ -44,6 +44,10 @@ Type
       (cpu_none
       );
 
+   { copied from arm/cpuinfo unit for arm specific
+     TSettings field }
+   tinstructionset = (is_thumb,is_arm);
+
 
 Type
    tfputype =

compiler/globals.pas

@@ -44,9 +44,9 @@ interface
       { comphook pulls in sysutils anyways }
       cutils,cclasses,cfileutl,
       cpuinfo,
-{$if defined(LLVM) and not defined(GENERIC_CPU)}
+{$if defined(LLVM) or defined(GENERIC_CPU)}
       llvminfo,
-{$endif LLVM and not GENERIC_CPU}
+{$endif LLVM or GENERIC_CPU}
       globtype,version,systems;
 
     const
@@ -166,23 +166,31 @@ interface
 
          tlsmodel : ttlsmodel;
 
-{$if defined(i8086)}
-         x86memorymodel  : tx86memorymodel;
-{$endif defined(i8086)}
-
-{$if defined(ARM)}
-         instructionset : tinstructionset;
-{$endif defined(ARM)}
-
-{$if defined(LLVM) and not defined(GENERIC_CPU)}
-         llvmversion: tllvmversion;
-{$endif defined(LLVM) and not defined(GENERIC_CPU)}
-
         { CPU targets with microcontroller support can add a controller specific unit }
          controllertype   : tcontrollertype;
 
          { WARNING: this pointer cannot be written as such in record token }
          pmessage : pmessagestaterecord;
+{$if defined(generic_cpu)}
+         case byte of
+{$endif}
+{$if defined(i8086) or defined(generic_cpu)}
+   {$ifdef generic_cpu} 1:({$endif}
+           x86memorymodel  : tx86memorymodel;
+   {$ifdef generic_cpu}   );{$endif}
+{$endif defined(i8086) or defined(generic_cpu)}
+
+{$if defined(ARM) or defined(generic_cpu)}
+   {$ifdef generic_cpu} 2:({$endif}
+         instructionset : tinstructionset;
+   {$ifdef generic_cpu}   );{$endif}
+{$endif defined(ARM) or defined(generic_cpu)}
+
+{$if defined(LLVM) or defined(GENERIC_CPU)}
+   {$ifdef generic_cpu} 3:({$endif}
+         llvmversion: tllvmversion;
+   {$ifdef generic_cpu}   );{$endif}
+{$endif defined(LLVM) or defined(GENERIC_CPU)}
        end;
 
     const
@@ -289,6 +297,9 @@ interface
        do_build,
        do_release,
        do_make       : boolean;
+
+       timestr,
+       datestr : string;
        { Path to ppc }
        exepath       : TPathStr;
        { Path to unicode charmap/collation binaries }
@@ -402,6 +413,10 @@ interface
        palmos_applicationname : string = 'FPC Application';
        palmos_applicationid : string[4] = 'FPCA';
 {$endif defined(m68k) or defined(arm)}
+{$if defined(m68k)}
+       { Sinclair QL specific }
+       sinclairql_metadata_format: string[4] = 'QHDR';
+{$endif defined(m68k)}
 
        { default name of the C-style "main" procedure of the library/program }
        { (this will be prefixed with the target_info.cprefix)                }
@@ -465,7 +480,7 @@ interface
         fputype : fpu_none;
 {$else not GENERIC_CPU}
   {$ifdef i386}
-        cputype : cpu_Pentium;
+        cputype : cpu_Pentium2;
         optimizecputype : cpu_Pentium3;
         asmcputype : cpu_none;
         fputype : fpu_x87;
@@ -588,17 +603,17 @@ interface
         disabledircache : false;
 
         tlsmodel : tlsm_none;
-{$if defined(i8086)}
+        controllertype : ct_none;
+        pmessage : nil;
+{$if defined(i8086) or defined(GENERIC_CPU)}
         x86memorymodel : mm_small;
-{$endif defined(i8086)}
+{$endif defined(i8086) or defined(GENERIC_CPU)}
 {$if defined(ARM)}
         instructionset : is_arm;
 {$endif defined(ARM)}
 {$if defined(LLVM) and not defined(GENERIC_CPU)}
         llvmversion    : llvmver_7_0;
 {$endif defined(LLVM) and not defined(GENERIC_CPU)}
-        controllertype : ct_none;
-        pmessage : nil;
       );
 
     var
@@ -1499,7 +1514,7 @@ implementation
        if localexepath='' then
         begin
           hs1 := ExtractFileName(exeName);
-	  hs1 := ChangeFileExt(hs1,source_info.exeext);
+          hs1 := ChangeFileExt(hs1,source_info.exeext);
 {$ifdef macos}
           FindFile(hs1,GetEnvironmentVariable('Commands'),false,localExepath);
 {$else macos}

compiler/globtype.pas

@@ -229,7 +229,11 @@ interface
          cs_link_pre_binutils_2_19,
          cs_link_vlink,
          { disable LTO for the system unit (needed to work around linker bugs on macOS) }
-         cs_lto_nosystem
+         cs_lto_nosystem,
+         cs_assemble_on_target,
+         { use a memory model which allows large data structures, e.g. > 2 GB static data on x86-64 targets
+           this not supported on all OSes }
+         cs_large
        );
        tglobalswitches = set of tglobalswitch;
 
@@ -787,7 +791,11 @@ interface
       TRADirection = (rad_forward, rad_backwards, rad_backwards_reinit);
 
     type
+{$ifndef symansistr}
       TIDString = string[maxidlen];
+{$else}
+      TIDString = TSymStr;
+{$endif}
 
       tnormalset = set of byte; { 256 elements set }
       pnormalset = ^tnormalset;

compiler/hlcg2ll.pas

@@ -837,7 +837,7 @@ implementation
     begin
 {$ifdef extdebug}
       if def_cgsize(size)<>loc.size then
-        internalerror(2010112101);
+        internalerror(2010112103);
 {$endif}
       case loc.loc of
         LOC_SUBSETREG,LOC_CSUBSETREG,

compiler/hlcgobj.pas

@@ -999,7 +999,7 @@ implementation
                    begin
                      { should be the last part }
                      if assigned(location^.next) then
-                       internalerror(2010052907);
+                       internalerror(2010052902);
                      { load the value piecewise to get it into the register }
                      orgsizeleft:=sizeleft;
                      reghasvalue:=false;
@@ -1083,7 +1083,7 @@ implementation
                    OS_M8..OS_M128:
                      a_loadmm_ref_reg(list,location^.def,location^.def,tmpref,location^.register,nil);
                    else
-                     internalerror(2010053101);
+                     internalerror(2010053103);
                  end;
               end
             else
@@ -1644,7 +1644,7 @@ implementation
       if sref.bitlen>AIntBits then
         begin
           if ((sref.bitlen mod AIntBits)<>0) then
-            internalerror(2019052901);
+            internalerror(2019052902);
           tmpsref:=sref;
           tmpsref.bitlen:=AIntBits;
           if target_info.endian=endian_big then
@@ -2762,7 +2762,7 @@ implementation
         LOC_REFERENCE,LOC_CREFERENCE:
           a_loadmm_reg_ref(list,fromsize,tosize,reg,loc.reference,shuffle);
         else
-          internalerror(2010120415);
+          internalerror(2010120417);
       end;
     end;
 
@@ -3069,7 +3069,7 @@ implementation
             a_load_reg_subsetref(list,size,size,tmpreg,loc.sref);
           end;
         else
-          internalerror(2010120429);
+          internalerror(2010120418);
       end;
     end;
 
@@ -3124,7 +3124,7 @@ implementation
   procedure thlcgobj.a_op_reg(list: TAsmList; Op: TOpCG; size: tdef; reg: TRegister);
     begin
       if not (Op in [OP_NOT,OP_NEG]) then
-        internalerror(2020050701);
+        internalerror(2020050711);
       a_op_reg_reg(list,op,size,reg,reg);
     end;
 
@@ -3133,7 +3133,7 @@ implementation
       tmpreg: TRegister;
     begin
       if not (Op in [OP_NOT,OP_NEG]) then
-        internalerror(2020050701);
+        internalerror(2020050712);
       tmpreg:=getintregister(list,size);
       a_load_ref_reg(list,size,size,ref,tmpreg);
       a_op_reg_reg(list,op,size,tmpreg,tmpreg);
@@ -4252,7 +4252,7 @@ implementation
           begin
             { vectors can't be represented yet using tdef }
             if size.typ<>floatdef then
-              internalerror(2012062301);
+              internalerror(2012062302);
             tg.gethltemp(list,size,size.size,tt_normal,r);
             a_loadmm_reg_ref(list,size,size,l.register,r,mms_movescalar);
             location_reset_ref(l,LOC_REFERENCE,l.size,size.alignment,[]);
@@ -5036,7 +5036,7 @@ implementation
                            begin
                              hsym:=tparavarsym(get_high_value_sym(tparavarsym(p)));
                              if not assigned(hsym) then
-                               internalerror(201003032);
+                               internalerror(2010030303);
                              highloc:=hsym.initialloc
                            end
                          else
@@ -5067,7 +5067,7 @@ implementation
                              begin
                                hsym:=tparavarsym(get_high_value_sym(tparavarsym(p)));
                                if not assigned(hsym) then
-                                 internalerror(201003032);
+                                 internalerror(2010030304);
                                highloc:=hsym.initialloc
                              end
                            else
@@ -5232,7 +5232,7 @@ implementation
                 a_loadfpu_reg_cgpara(list,size,tmploc.register,cgpara);
               end;
             else
-              internalerror(200204249);
+              internalerror(2002042402);
           end;
         LOC_FPUREGISTER,
         LOC_CFPUREGISTER:
@@ -5381,7 +5381,7 @@ implementation
                       a_load_ref_ref(list,para.def,para.def,href,destloc.reference);
                     end;
                   else
-                    internalerror(2013102301);
+                    internalerror(2013102305);
                 end;
               end;
           end;

compiler/htypechk.pas

@@ -62,7 +62,10 @@ interface
          cl6_count,
          coper_count : integer; { should be signed }
          ordinal_distance : double;
-         invalid     : boolean;
+         invalid : boolean;
+{$ifndef DISABLE_FAST_OVERLOAD_PATCH}
+         saved_validity : boolean;
+{$endif}
          wrongparanr : byte;
       end;
 
@@ -670,17 +673,7 @@ implementation
                     eq:=compare_defs_ext(ld,pf.returndef,nothingn,conv,pd,cdo);
                     result:=
                       (eq=te_exact) or
-                      (
-                        (eq=te_incompatible) and
-                        { don't allow overloading assigning to custom shortstring
-                          types, because we also don't want to differentiate based
-                          on different shortstring types (e.g.,
-                          "operator :=(const v: variant) res: shorstring" also
-                          has to work for assigning a variant to a string[80])
-                        }
-                        (not is_shortstring(pf.returndef) or
-                         (tstringdef(pf.returndef).len=255))
-                      );
+                      (eq=te_incompatible);
                   end
                 else
                 { enumerator is a special case too }
@@ -2306,7 +2299,8 @@ implementation
               srsym:=tsym(helperdef.symtable.FindWithHash(hashedid));
               if assigned(srsym) and
                   { Delphi allows hiding a property by a procedure with the same name }
-                  (srsym.typ=procsym) then
+                  (srsym.typ=procsym) and
+                  (tprocsym(srsym).procdeflist.count>0) then
                 begin
                   hasoverload:=processprocsym(tprocsym(srsym),foundanything);
                   { when there is no explicit overload we stop searching }
@@ -2395,7 +2389,8 @@ implementation
                srsym:=tprocsym(tabstractrecorddef(tobjectdef(structdef).extendeddef).symtable.FindWithHash(hashedid));
                if assigned(srsym) and
                   { Delphi allows hiding a property by a procedure with the same name }
-                  (srsym.typ=procsym) then
+                  (srsym.typ=procsym) and
+                  (tprocsym(srsym).procdeflist.count>0) then
                  begin
                    hasoverload:=processprocsym(tprocsym(srsym),foundanything);
                    { when there is no explicit overload we stop searching }
@@ -2470,7 +2465,8 @@ implementation
               begin
                 srsym:=tsym(srsymtable.FindWithHash(hashedid));
                 if assigned(srsym) and
-                   (srsym.typ=procsym) then
+                   (srsym.typ=procsym) and
+                   (tprocsym(srsym).procdeflist.count>0) then
                   begin
                     { add all definitions }
                     hasoverload:=false;
@@ -2585,7 +2581,11 @@ implementation
 
             { only when the # of parameter are supported by the procedure and
               it is visible }
+{$ifdef DISABLE_FAST_OVERLOAD_PATCH}
             if (FParalength>=pd.minparacount) and
+{$else}
+            if (pd.seenmarker<>pointer(self)) and (FParalength>=pd.minparacount) and
+{$endif}
                (
                 (
                  allowdefaultparas and
@@ -2625,6 +2625,7 @@ implementation
                   cpoptions:=cpoptions+[cpo_rtlproc];
                 found:=false;
                 hp:=FCandidateProcs;
+{$ifdef DISABLE_FAST_OVERLOAD_PATCH}
                 while assigned(hp) do
                   begin
                     if (compare_paras(hp^.data.paras,pd.paras,cp_value_equal_const,cpoptions)>=te_equal) and
@@ -2636,10 +2637,14 @@ implementation
                       end;
                     hp:=hp^.next;
                   end;
+{$endif}
                 if not found then
                   begin
                     proc_add(st,pd,objcidcall);
                     added:=true;
+{$ifndef DISABLE_FAST_OVERLOAD_PATCH}
+                    pd.seenmarker:=self;
+{$endif}
                   end;
               end;
 
@@ -2653,6 +2658,14 @@ implementation
                 pd.free;
               end;
           end;
+{$ifndef DISABLE_FAST_OVERLOAD_PATCH}
+        {cleanup modified duplicate pd markers}
+        hp := FCandidateProcs;
+        while assigned(hp) do begin
+          hp^.data.seenmarker := nil;
+          hp := hp^.next;
+        end;
+{$endif}
 
         calc_distance(st,objcidcall);
 
@@ -3239,6 +3252,8 @@ implementation
       end;
 
 
+
+
     function is_better_candidate(currpd,bestpd:pcandidate):integer;
       var
         res : integer;
@@ -3489,6 +3504,9 @@ implementation
       end;
 
 
+
+{$ifdef DISABLE_FAST_OVERLOAD_PATCH}
+
     function tcallcandidates.choose_best(var bestpd:tabstractprocdef; singlevariant: boolean):integer;
       var
         pd: tprocdef;
@@ -3576,6 +3594,232 @@ implementation
       end;
 
 
+{$else}
+
+    function compare_by_old_sortout_check(pd,bestpd:pcandidate):integer;
+      var cpoptions : tcompare_paras_options;
+      begin
+        { don't add duplicates, only compare visible parameters for the user }
+        cpoptions:=[cpo_ignorehidden];
+        if (po_compilerproc in bestpd^.data.procoptions) then
+          cpoptions:=cpoptions+[cpo_compilerproc];
+        if (po_rtlproc in bestpd^.data.procoptions) then
+          cpoptions:=cpoptions+[cpo_rtlproc];
+
+        compare_by_old_sortout_check := 0; // can't decide, bestpd probably wasn't sorted out in unpatched
+        if (compare_paras(pd^.data.paras,bestpd^.data.paras,cp_value_equal_const,cpoptions)>=te_equal) and
+          (not(po_objc in bestpd^.data.procoptions) or (bestpd^.data.messageinf.str^=pd^.data.messageinf.str^)) then
+          compare_by_old_sortout_check := 1; // bestpd was sorted out before patch
+     end;
+
+    function decide_restart(pd,bestpd:pcandidate) : boolean;
+      begin
+        decide_restart := false;
+        if assigned(bestpd) then
+          begin
+            { don't restart if bestpd is marked invalid already }
+            if not bestpd^.invalid then
+              decide_restart := compare_by_old_sortout_check(pd,bestpd)<>0;
+        end;
+      end;
+
+
+    procedure save_validity(c : pcandidate);
+      begin
+        while assigned(c) do
+          begin
+            c^.saved_validity := c^.invalid;
+            c := c^.next;
+          end;
+      end;
+
+
+    procedure restore_validity(c : pcandidate);
+      begin
+        while assigned(c) do begin
+          c^.invalid := c^.saved_validity;
+          c := c^.next;
+        end;
+      end;
+
+
+    function tcallcandidates.choose_best(var bestpd:tabstractprocdef; singlevariant: boolean):integer;
+      var
+        pd: tprocdef;
+        besthpstart,
+        hp,hp2        : pcandidate;
+        cntpd,
+        res           : integer;
+        restart : boolean;
+      begin
+        res:=0;
+        {
+          Returns the number of candidates left and the
+          first candidate is returned in pdbest
+        }
+       if not(assigned(FCandidateProcs)) then
+         begin
+           choose_best := 0;
+           exit;
+         end;
+
+        bestpd:=FCandidateProcs^.data;
+        if FCandidateProcs^.invalid then
+          cntpd:=0
+        else
+          cntpd:=1;
+
+        if assigned(FCandidateProcs^.next) then
+         begin
+           save_validity(FCandidateProcs);
+           restart := false;
+           { keep restarting, until there wasn't a sorted-out besthpstart }
+           repeat
+             besthpstart:=FCandidateProcs;
+             bestpd:=FCandidateProcs^.data;
+             if restart then
+               begin
+                 restore_validity(FCandidateProcs);
+                 restart := false;
+               end;
+             { Setup the first procdef as best, only count it as a result
+               when it is valid }
+             if besthpstart^.invalid then
+               cntpd:=0
+             else
+               cntpd:=1;
+             hp:=FCandidateProcs^.next;
+             while assigned(hp) and not(restart) do
+               begin
+                 restart := decide_restart(hp,besthpstart);
+                 if not restart then
+                   begin
+                   if besthpstart^.invalid then res := 1
+                   else if hp^.invalid then res := -1
+                   else if not singlevariant then
+                     res:=is_better_candidate(hp,besthpstart)
+                   else
+                     res:=is_better_candidate_single_variant(hp,besthpstart);
+                 end;
+                 if restart then
+                   begin
+                     { mark the sorted out invalid globally }
+                     besthpstart^.saved_validity := true;
+                   end
+                 else if (res>0) then
+                   begin
+                     { hp is better, flag all procs to be incompatible }
+                     while (besthpstart<>hp) do
+                       begin
+                         besthpstart^.invalid:=true;
+                         besthpstart:=besthpstart^.next;
+                       end;
+                     { besthpstart is already set to hp }
+                     bestpd:=besthpstart^.data;
+                     if besthpstart^.invalid then
+                       cntpd:=0
+                     else
+                       cntpd:=1;
+                   end
+                 else if (res<0) then
+                   begin
+                    { besthpstart is better, flag current hp to be incompatible }
+                    hp^.invalid:=true;
+                   end
+                 else
+                   begin
+                     { res=0, both are valid }
+                     if not hp^.invalid then
+                       inc(cntpd);
+                   end;
+                 hp:=hp^.next;
+               end;
+           until not(restart);
+         end;
+
+        { check the alternate choices if they would have been sorted out before patch... }
+
+        { note we have procadded the candidates, so order is reversed procadd order here.
+          this was also used above: each sorted-out always has an "outsorter" counterpart
+          deeper down the next chain
+        }
+
+        { for the intial implementation, let's first do some more consistency checking}
+        res := 0;
+        hp := FCandidateProcs;
+        while assigned(hp) do
+          begin
+            if not(hp^.invalid) then
+              inc(res);
+            hp := hp^.next;
+          end;
+        if (res<>cntpd) then
+          internalerror(202002161);
+
+        { check all valid choices for sortout }
+        cntpd := 0;
+        hp := FCandidateProcs;
+        while assigned(hp) do
+          begin
+            if not(hp^.invalid) then
+              begin
+                hp2 := hp^.next;
+                while assigned(hp2) do begin
+                  if compare_by_old_sortout_check(hp2,hp)<>0 then
+                    begin
+                      hp^.invalid := true;
+                      hp2 := nil;
+                    end
+                  else
+                    hp2:=hp2^.next;
+                end;
+                if not(hp^.invalid) then
+                  begin
+                    inc(cntpd);
+                    { check for the impossible event bestpd had become invalid}
+                    if (cntpd=1) and (hp^.data<>bestpd) then
+                      internalerror(202002162);
+                  end;
+              end;
+            hp := hp^.next;
+          end;
+
+
+        { if we've found one, check the procdefs ignored for overload choosing
+          to see whether they contain one from a child class with the same
+          parameters (so the overload choosing was not influenced by their
+          presence, but now that we've decided which overloaded version to call,
+          make sure we call the version closest in terms of visibility }
+        if cntpd=1 then
+          begin
+            for res:=0 to FIgnoredCandidateProcs.count-1 do
+              begin
+                pd:=tprocdef(FIgnoredCandidateProcs[res]);
+                { stop searching when we start comparing methods of parent of
+                  the struct in which the current best method was found }
+                if assigned(pd.struct) and
+                   (pd.struct<>tprocdef(bestpd).struct) and
+                   def_is_related(tprocdef(bestpd).struct,pd.struct) then
+                  break;
+                if (pd.proctypeoption=bestpd.proctypeoption) and
+                   ((pd.procoptions*[po_classmethod,po_methodpointer])=(bestpd.procoptions*[po_classmethod,po_methodpointer])) and
+                   (compare_paras(pd.paras,bestpd.paras,cp_all,[cpo_ignorehidden,cpo_ignoreuniv,cpo_openequalisexact])=te_exact) then
+                  begin
+                    { first one encountered is closest in terms of visibility }
+                    bestpd:=pd;
+                    break;
+                  end;
+              end;
+          end;
+        result:=cntpd;
+      end;
+
+{$endif}
+
+
+
+
+
     procedure tcallcandidates.find_wrong_para;
       var
         currparanr : smallint;

compiler/i386/aoptcpu.pas

@@ -143,8 +143,14 @@ unit aoptcpu;
                   Result:=OptPass1Imul(p);
                 A_CMP:
                   Result:=OptPass1Cmp(p);
+                A_VPXORD,
+                A_VPXORQ,
+                A_VXORPS,
+                A_VXORPD,
                 A_VPXOR:
                   Result:=OptPass1VPXor(p);
+                A_XORPS,
+                A_XORPD,
                 A_PXOR:
                   Result:=OptPass1PXor(p);
                 A_FLD:
@@ -199,9 +205,7 @@ unit aoptcpu;
                 A_VANDPD,
                 A_VANDPS,
                 A_VORPD,
-                A_VORPS,
-                A_VXORPD,
-                A_VXORPS:
+                A_VORPS:
                   Result:=OptPass1VOP(p);
                 A_MULSD,
                 A_MULSS,
@@ -234,6 +238,8 @@ unit aoptcpu;
               if InsContainsSegRef(taicpu(p)) then
                 exit;
               case taicpu(p).opcode Of
+                A_ADD:
+                  Result:=OptPass2ADD(p);
                 A_Jcc:
                   Result:=OptPass2Jcc(p);
                 A_Lea:
@@ -246,6 +252,8 @@ unit aoptcpu;
                   Result:=OptPass2Jmp(p);
                 A_MOV:
                   Result:=OptPass2MOV(p);
+                A_MOVZX:
+                  Result:=OptPass2Movx(p);
                 A_SUB:
                   Result:=OptPass2SUB(p);
                 else
@@ -282,7 +290,9 @@ unit aoptcpu;
                   {   "cmpl $3,%eax; movzbl 8(%ebp),%ebx; je .Lxxx"           }
                   { so we can't safely replace the movzx then with xor/mov,   }
                   { since that would change the flags (JM)                    }
-                  if not(cs_opt_regvar in current_settings.optimizerswitches) then
+                  if PostPeepholeOptMovzx(p) then
+                    Result := True
+                  else if not(cs_opt_regvar in current_settings.optimizerswitches) then
                     begin
                       if (taicpu(p).oper[1]^.typ = top_reg) then
                         if (taicpu(p).oper[0]^.typ = top_reg)
@@ -330,8 +340,12 @@ unit aoptcpu;
                    end;
                 A_TEST, A_OR:
                   Result:=PostPeepholeOptTestOr(p);
+                A_AND:
+                  Result:=PostPeepholeOptAnd(p);
                 A_MOVSX:
                   Result:=PostPeepholeOptMOVSX(p);
+                A_SHR:
+                  Result:=PostPeepholeOptShr(p);
                 else
                   ;
               end;

compiler/i386/cgcpu.pas

@@ -636,7 +636,7 @@ unit cgcpu;
               op2:=A_AND;
             end;
           else
-            internalerror(200203241);
+            internalerror(2002032408);
         end;
       end;
 
@@ -857,7 +857,7 @@ unit cgcpu;
                     list.Concat(taicpu.op_reg_reg(A_SAR,S_L,NR_CL,regdst.reghi));
                   end;
                 else
-                  internalerror(2017041801);
+                  internalerror(2017041802);
               end;
               cg.a_label(list,l2);
 
@@ -980,7 +980,7 @@ unit cgcpu;
                           list.concat(taicpu.op_const_reg(A_SHL,S_L,value,reg.reglo));
                         end;
                       else
-                        internalerror(2017041201);
+                        internalerror(2017041202);
                     end;
                 end;
             end;
@@ -1049,7 +1049,7 @@ unit cgcpu;
                           cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
                         end;
                       else
-                        internalerror(2019050901);
+                        internalerror(2019050903);
                     end
                   else if value>31 then
                     case op of
@@ -1086,7 +1086,7 @@ unit cgcpu;
                           cg.a_load_const_ref(list,OS_32,0,tempref);
                         end;
                       else
-                        internalerror(2017041801);
+                        internalerror(2017041803);
                     end
                   else
                     case op of
@@ -1130,7 +1130,7 @@ unit cgcpu;
                             end;
                         end;
                       else
-                        internalerror(2017041201);
+                        internalerror(2017041203);
                     end;
                 end;
             end;

compiler/i386/cpuelf.pas

@@ -473,7 +473,7 @@ implementation
               else
                 begin
                   writeln(reltyp);
-                  internalerror(200604014);
+                  internalerror(2006040108);
                 end;
             end
           else           { not relocsec.Used }

compiler/i386/cpuinfo.pas

@@ -67,7 +67,8 @@ Type
       fpu_sse41,
       fpu_sse42,
       fpu_avx,
-      fpu_avx2
+      fpu_avx2,
+      fpu_avx512f
      );
 
    tcontrollertype =
@@ -122,7 +123,7 @@ Const
      'COREAVX2'
    );
 
-   fputypestr : array[tfputype] of string[6] = (
+   fputypestr : array[tfputype] of string[7] = (
      'NONE',
 //     'SOFT',
      'X87',
@@ -133,13 +134,14 @@ Const
      'SSE41',
      'SSE42',
      'AVX',
-     'AVX2'
+     'AVX2',
+     'AVX512F'
    );
 
-   sse_singlescalar = [fpu_sse..fpu_avx2];
-   sse_doublescalar = [fpu_sse2..fpu_avx2];
+   sse_singlescalar = [fpu_sse..fpu_avx512f];
+   sse_doublescalar = [fpu_sse2..fpu_avx512f];
 
-   fpu_avx_instructionsets = [fpu_avx,fpu_avx2];
+   fpu_avx_instructionsets = [fpu_avx,fpu_avx2,fpu_avx512f];
 
    { Supported optimizations, only used for information }
    supported_optimizerswitches = genericlevel1optimizerswitches+
@@ -174,7 +176,9 @@ type
 
    tfpuflags =
       (FPUX86_HAS_AVXUNIT,
-       FPUX86_HAS_32MMREGS
+       FPUX86_HAS_AVX512F,
+       FPUX86_HAS_AVX512VL,
+       FPUX86_HAS_AVX512DQ
       );
 
  const
@@ -202,7 +206,8 @@ type
       { fpu_sse41    } [],
       { fpu_sse42    } [],
       { fpu_avx      } [FPUX86_HAS_AVXUNIT],
-      { fpu_avx2     } [FPUX86_HAS_AVXUNIT]
+      { fpu_avx2     } [FPUX86_HAS_AVXUNIT],
+      { fpu_avx512   } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_AVX512F,FPUX86_HAS_AVX512VL,FPUX86_HAS_AVX512DQ]
    );
 
 Implementation

compiler/i386/cpupara.pas

@@ -522,7 +522,7 @@ unit cpupara;
             else
               begin
                 if paralen=0 then
-                  internalerror(200501163);
+                  internalerror(2005011606);
                 firstparaloc:=true;
                 while (paralen>0) do
                   begin
@@ -688,7 +688,7 @@ unit cpupara;
                           else
                             begin
                               if paralen=0 then
-                                internalerror(200501163);
+                                internalerror(2005011607);
                               firstparaloc:=true;
                               while (paralen>0) do
                                 begin

compiler/i386/hlcgcpu.pas

@@ -352,7 +352,7 @@ implementation
         href : treference;
       begin
         if (procdef.extnumber=$ffff) then
-          Internalerror(200006139);
+          Internalerror(2000061312);
         { call/jmp  vmtoffs(%reg) ; method offs }
         reference_reset_base(href,voidpointertype,reg,tobjectdef(procdef.struct).vmtmethodoffset(procdef.extnumber),ctempposinvalid,4,[]);
         list.concat(taicpu.op_ref(op,S_L,href));
@@ -364,7 +364,7 @@ implementation
         href : treference;
       begin
         if (procdef.extnumber=$ffff) then
-          Internalerror(200006139);
+          Internalerror(2000061313);
         { mov vmtoffs(%eax),%eax ; method offs }
         reference_reset_base(href,voidpointertype,NR_EAX,tobjectdef(procdef.struct).vmtmethodoffset(procdef.extnumber),ctempposinvalid,4,[]);
         cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_EAX);

compiler/i386/i386att.inc

@@ -1125,6 +1125,13 @@
 'rdrand',
 'rdseed',
 'xgetbv',
+'xsetbv',
+'xsave',
+'xsave64',
+'xrstor',
+'xrstor64',
+'xsaveopt',
+'xsaveopt64',
 'prefetchwt1',
 'kaddb',
 'kaddd',

compiler/i386/i386atts.inc

@@ -1125,6 +1125,13 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufINT,
 attsufNONE,
 attsufNONE,

compiler/i386/i386int.inc

@@ -1125,6 +1125,13 @@
 'rdrand',
 'rdseed',
 'xgetbv',
+'xsetbv',
+'xsave',
+'xsave64',
+'xrstor',
+'xrstor64',
+'xsaveopt',
+'xsaveopt64',
 'prefetchwt1',
 'kaddb',
 'kaddd',

compiler/i386/i386nop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from x86ins.dat }
-4157;
+4164;

compiler/i386/i386op.inc

@@ -1125,6 +1125,13 @@ A_XTEST,
 A_RDRAND,
 A_RDSEED,
 A_XGETBV,
+A_XSETBV,
+A_XSAVE,
+A_XSAVE64,
+A_XRSTOR,
+A_XRSTOR64,
+A_XSAVEOPT,
+A_XSAVEOPT64,
 A_PREFETCHWT1,
 A_KADDB,
 A_KADDD,

compiler/i386/i386prop.inc

@@ -431,10 +431,10 @@
 (Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_ROp1, Ch_WOp2]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -549,10 +549,10 @@
 (Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_Mop2, Ch_Rop1]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_ROp1, Ch_WOp2]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -805,6 +805,8 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -814,16 +816,14 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
 (Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_Wop2, Ch_Rop1]),
@@ -988,8 +988,8 @@
 (Ch: [Ch_Rop1, Ch_Rop2, Ch_Rop3, Ch_Wop4]),
 (Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Wop4, Ch_Rop3, Ch_Rop2]),
+(Ch: [Ch_Wop4, Ch_Rop3, Ch_Rop2]),
 (Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
@@ -1003,10 +1003,10 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_Rop1, Ch_Rop2, Ch_WZeroFlag, Ch_WParityFlag, Ch_WCarryFlag, Ch_W0OverflowFlag, Ch_W0SignFlag, Ch_W0AuxiliaryFlag]),
 (Ch: [Ch_Rop1, Ch_Rop2, Ch_WZeroFlag, Ch_WParityFlag, Ch_WCarryFlag, Ch_W0OverflowFlag, Ch_W0SignFlag, Ch_W0AuxiliaryFlag]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
+(Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
 (Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
 (Ch: [Ch_Wop3, Ch_Rop2, Ch_Rop1]),
 (Ch: [Ch_All]),
@@ -1125,6 +1125,7 @@
 (Ch: [Ch_Wop1, Ch_WFlags]),
 (Ch: [Ch_Wop1, Ch_WFlags]),
 (Ch: [Ch_WEAX, Ch_WEDX, Ch_RECX]),
+(Ch: [Ch_REAX, Ch_REDX, Ch_RECX]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -1199,6 +1200,30 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -1236,6 +1261,12 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
+(Ch: [Ch_Wop2, Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -1352,34 +1383,10 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Rop1, Ch_Rop2, Ch_Wop3]),
+(Ch: [Ch_Rop1, Ch_Rop2, Ch_Wop3]),
+(Ch: [Ch_Rop1, Ch_Rop2, Ch_Rop3, Ch_Wop4]),
+(Ch: [Ch_Rop1, Ch_Rop2, Ch_Rop3, Ch_Wop4]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),

compiler/i386/i386tab.inc

@@ -20335,6 +20335,55 @@
     code    : #3#15#1#208;
     flags   : [if_xsave]
   ),
+  (
+    opcode  : A_XSETBV;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none);
+    code    : #3#15#1#209;
+    flags   : [if_xsave]
+  ),
+  (
+    opcode  : A_XSAVE;
+    ops     : 1;
+    optypes : (ot_memory,ot_none,ot_none,ot_none);
+    code    : #2#15#174#132;
+    flags   : [if_xsave]
+  ),
+  (
+    opcode  : A_XSAVE64;
+    ops     : 1;
+    optypes : (ot_memory,ot_none,ot_none,ot_none);
+    code    : #214#2#15#174#132;
+    flags   : [if_xsave]
+  ),
+  (
+    opcode  : A_XRSTOR;
+    ops     : 1;
+    optypes : (ot_memory,ot_none,ot_none,ot_none);
+    code    : #2#15#174#133;
+    flags   : [if_xsave]
+  ),
+  (
+    opcode  : A_XRSTOR64;
+    ops     : 1;
+    optypes : (ot_memory,ot_none,ot_none,ot_none);
+    code    : #214#2#15#174#133;
+    flags   : [if_xsave]
+  ),
+  (
+    opcode  : A_XSAVEOPT;
+    ops     : 1;
+    optypes : (ot_memory,ot_none,ot_none,ot_none);
+    code    : #2#15#174#134;
+    flags   : [if_xsave]
+  ),
+  (
+    opcode  : A_XSAVEOPT64;
+    ops     : 1;
+    optypes : (ot_memory,ot_none,ot_none,ot_none);
+    code    : #214#2#15#174#134;
+    flags   : [if_xsave]
+  ),
   (
     opcode  : A_PREFETCHWT1;
     ops     : 1;