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@@ -1869,7 +1869,7 @@ unit cgcpu;
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{ Allocate SI and load it with source }
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{ Allocate SI and load it with source }
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getcpuregister(list,NR_SI);
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getcpuregister(list,NR_SI);
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- if (ref.segment=NR_NO) or
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+ if ((ref.segment=NR_NO) and (segment_regs_equal(NR_SS,NR_DS) or (ref.base<>NR_BP))) or
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(is_segment_reg(ref.segment) and segment_regs_equal(ref.segment,NR_DS)) then
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(is_segment_reg(ref.segment) and segment_regs_equal(ref.segment,NR_DS)) then
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begin
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begin
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a_loadaddr_ref_reg(list,ref,NR_SI);
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a_loadaddr_ref_reg(list,ref,NR_SI);
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@@ -1880,7 +1880,12 @@ unit cgcpu;
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hlcg.a_loadaddr_ref_reg(list,voidnearpointertype,voidnearpointertype,ref,NR_SI);
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hlcg.a_loadaddr_ref_reg(list,voidnearpointertype,voidnearpointertype,ref,NR_SI);
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list.concat(taicpu.op_reg(A_PUSH,S_W,NR_DS));
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list.concat(taicpu.op_reg(A_PUSH,S_W,NR_DS));
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saved_ds:=true;
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saved_ds:=true;
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- list.concat(taicpu.op_reg(A_PUSH,S_W,ref.segment));
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+ if ref.segment<>NR_NO then
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+ list.concat(taicpu.op_reg(A_PUSH,S_W,ref.segment))
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+ else if ref.base=NR_BP then
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+ list.concat(taicpu.op_reg(A_PUSH,S_W,NR_SS))
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+ else
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+ internalerror(2014040403);
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list.concat(taicpu.op_reg(A_POP,S_W,NR_DS));
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list.concat(taicpu.op_reg(A_POP,S_W,NR_DS));
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end;
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end;
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@@ -1928,6 +1933,8 @@ unit cgcpu;
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{ patch the new address, but don't use a_load_reg_reg, that will add a move instruction
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{ patch the new address, but don't use a_load_reg_reg, that will add a move instruction
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that can confuse the reg allocator }
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that can confuse the reg allocator }
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list.concat(Taicpu.Op_reg_reg(A_MOV,S_W,NR_SP,destreg));
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list.concat(Taicpu.Op_reg_reg(A_MOV,S_W,NR_SP,destreg));
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+ if current_settings.x86memorymodel in x86_far_data_models then
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+ list.concat(Taicpu.Op_reg_reg(A_MOV,S_W,NR_SS,GetNextReg(destreg)));
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end;
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end;
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