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@@ -28,14 +28,16 @@ Interface
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Uses Aasm;
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+Procedure PrePeepHoleOpts(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
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Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
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Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
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+Procedure PostPeepHoleOpts(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
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Implementation
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Uses
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globtype,systems,
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- globals,verbose,hcodegen,
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+ globals,hcodegen,
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{$ifdef finaldestdebug}
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cobjects,
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{$endif finaldestdebug}
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@@ -97,6 +99,308 @@ begin
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end;
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end;
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+Procedure PrePeepHoleOpts(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
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+var
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+ p,hp1: pai;
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+ l: longint;
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+ tmpRef: treference;
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+Begin
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+ P := BlockStart;
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+ While (P <> BlockEnd) Do
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+ Begin
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+ Case P^.Typ Of
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+ Ait_Instruction:
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+ Begin
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+ Case Paicpu(p)^.opcode Of
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+ A_IMUL:
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+ {changes certain "imul const, %reg"'s to lea sequences}
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+ Begin
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+ If (Paicpu(p)^.oper[0].typ = Top_Const) And
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+ (Paicpu(p)^.oper[1].typ = Top_Reg) And
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+ (Paicpu(p)^.opsize = S_L) Then
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+ If (Paicpu(p)^.oper[0].val = 1) Then
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+ If (Paicpu(p)^.oper[2].typ = Top_None) Then
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+ {remove "imul $1, reg"}
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+ Begin
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+ hp1 := Pai(p^.Next);
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+ AsmL^.Remove(p);
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+ Dispose(p, Done);
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+ p := hp1;
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+ Continue;
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+ End
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+ Else
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+ {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
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+ Begin
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+ hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
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+ InsertLLItem(AsmL, p^.previous, p^.next, hp1);
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+ Dispose(p, Done);
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+ p := hp1;
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+ End
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+ Else If
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+ ((Paicpu(p)^.oper[2].typ = Top_Reg) or
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+ (Paicpu(p)^.oper[2].typ = Top_None)) And
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+ (aktoptprocessor < ClassP6) And
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+ (Paicpu(p)^.oper[0].val <= 12) And
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+ Not(CS_LittleSize in aktglobalswitches) And
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+ (Not(GetNextInstruction(p, hp1)) Or
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+ {GetNextInstruction(p, hp1) And}
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+ Not((Pai(hp1)^.typ = ait_instruction) And
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+ ((paicpu(hp1)^.opcode=A_Jcc) and
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+ (paicpu(hp1)^.condition in [C_O,C_NO]))))
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+ Then
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+ Begin
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+ Reset_reference(tmpref);
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+ Case Paicpu(p)^.oper[0].val Of
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+ 3: Begin
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+ {imul 3, reg1, reg2 to
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+ lea (reg1,reg1,2), reg2
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+ imul 3, reg1 to
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+ lea (reg1,reg1,2), reg1}
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+ TmpRef.base := Paicpu(p)^.oper[1].reg;
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ TmpRef.ScaleFactor := 2;
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+ If (Paicpu(p)^.oper[2].typ = Top_None) Then
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
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+ Else
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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+ InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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+ Dispose(p, Done);
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+ p := hp1;
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+ End;
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+ 5: Begin
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+ {imul 5, reg1, reg2 to
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+ lea (reg1,reg1,4), reg2
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+ imul 5, reg1 to
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+ lea (reg1,reg1,4), reg1}
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+ TmpRef.base := Paicpu(p)^.oper[1].reg;
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ TmpRef.ScaleFactor := 4;
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+ If (Paicpu(p)^.oper[2].typ = Top_None) Then
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
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+ Else
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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+ InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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+ Dispose(p, Done);
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+ p := hp1;
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+ End;
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+ 6: Begin
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+ {imul 6, reg1, reg2 to
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+ lea (,reg1,2), reg2
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+ lea (reg2,reg1,4), reg2
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+ imul 6, reg1 to
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+ lea (reg1,reg1,2), reg1
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+ add reg1, reg1}
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+ If (aktoptprocessor <= Class386)
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+ Then
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+ Begin
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ If (Paicpu(p)^.oper[2].typ = Top_Reg)
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+ Then
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+ Begin
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+ TmpRef.base := Paicpu(p)^.oper[2].reg;
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+ TmpRef.ScaleFactor := 4;
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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+ End
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+ Else
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+ Begin
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+ hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
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+ Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
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+ End;
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+ InsertLLItem(AsmL,p, p^.next, hp1);
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+ Reset_reference(tmpref);
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ TmpRef.ScaleFactor := 2;
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+ If (Paicpu(p)^.oper[2].typ = Top_Reg)
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+ Then
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+ Begin
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+ TmpRef.base := R_NO;
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
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+ Paicpu(p)^.oper[2].reg));
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+ End
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+ Else
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+ Begin
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+ TmpRef.base := Paicpu(p)^.oper[1].reg;
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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+ End;
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+ InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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+ Dispose(p, Done);
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+ p := Pai(hp1^.next);
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+ End
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+ End;
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+ 9: Begin
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+ {imul 9, reg1, reg2 to
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+ lea (reg1,reg1,8), reg2
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+ imul 9, reg1 to
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+ lea (reg1,reg1,8), reg1}
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+ TmpRef.base := Paicpu(p)^.oper[1].reg;
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ TmpRef.ScaleFactor := 8;
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+ If (Paicpu(p)^.oper[2].typ = Top_None) Then
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
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+ Else
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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+ InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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+ Dispose(p, Done);
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+ p := hp1;
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+ End;
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+ 10: Begin
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+ {imul 10, reg1, reg2 to
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+ lea (reg1,reg1,4), reg2
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+ add reg2, reg2
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+ imul 10, reg1 to
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+ lea (reg1,reg1,4), reg1
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+ add reg1, reg1}
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+ If (aktoptprocessor <= Class386) Then
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+ Begin
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+ If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
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+ hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
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+ Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
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+ Else
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+ hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
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+ Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
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+ InsertLLItem(AsmL,p, p^.next, hp1);
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+ TmpRef.base := Paicpu(p)^.oper[1].reg;
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ TmpRef.ScaleFactor := 4;
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+ If (Paicpu(p)^.oper[2].typ = Top_Reg)
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+ Then
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
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+ Else
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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+ InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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+ Dispose(p, Done);
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+ p := Pai(hp1^.next);
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+ End
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+ End;
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+ 12: Begin
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+ {imul 12, reg1, reg2 to
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+ lea (,reg1,4), reg2
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+ lea (,reg1,8) reg2
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+ imul 12, reg1 to
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+ lea (reg1,reg1,2), reg1
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+ lea (,reg1,4), reg1}
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+ If (aktoptprocessor <= Class386)
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+ Then
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+ Begin
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
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+ Begin
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+ TmpRef.base := Paicpu(p)^.oper[2].reg;
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+ TmpRef.ScaleFactor := 8;
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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+ End
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+ Else
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+ Begin
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+ TmpRef.base := R_NO;
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+ TmpRef.ScaleFactor := 4;
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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+ End;
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+ InsertLLItem(AsmL,p, p^.next, hp1);
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+ Reset_reference(tmpref);
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+ TmpRef.Index := Paicpu(p)^.oper[1].reg;
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+ If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
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+ Begin
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+ TmpRef.base := R_NO;
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+ TmpRef.ScaleFactor := 4;
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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+ End
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+ Else
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+ Begin
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+ TmpRef.base := Paicpu(p)^.oper[1].reg;
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+ TmpRef.ScaleFactor := 2;
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+ hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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+ End;
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+ InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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+ Dispose(p, Done);
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+ p := Pai(hp1^.next);
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+ End
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+ End
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+ End;
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+ End;
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+ End;
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+ A_SAR, A_SHR:
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+ {changes the code sequence
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+ shr/sar const1, x
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+ shl const2, x
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+ to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
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+ Begin
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+ If GetNextInstruction(p, hp1) And
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+ (pai(hp1)^.typ = ait_instruction) and
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+ (Paicpu(hp1)^.opcode = A_SHL) and
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+ (Paicpu(p)^.oper[0].typ = top_const) and
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+ (Paicpu(hp1)^.oper[0].typ = top_const) and
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+ (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
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+ (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
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+ OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
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+ Then
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+ If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
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+ Not(CS_LittleSize In aktglobalswitches)
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+ Then
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+ { shr/sar const1, %reg
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+ shl const2, %reg
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+ with const1 > const2 }
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+ Begin
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+ Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
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+ Paicpu(hp1)^.opcode := A_AND;
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+ l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
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+ Case Paicpu(p)^.opsize Of
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+ S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
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+ S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
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+ S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
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+ End;
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+ End
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+ Else
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+ If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
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+ Not(CS_LittleSize In aktglobalswitches)
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+ Then
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+ { shr/sar const1, %reg
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+ shl const2, %reg
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+ with const1 < const2 }
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+ Begin
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+ Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
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+ Paicpu(p)^.opcode := A_AND;
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+ l := (1 shl (Paicpu(p)^.oper[0].val))-1;
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+ Case Paicpu(p)^.opsize Of
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+ S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
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+ S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
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+ S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
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+ End;
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+ End
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+ Else
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+ { shr/sar const1, %reg
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+ shl const2, %reg
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+ with const1 = const2 }
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+ if (Paicpu(p)^.oper[0].val = Paicpu(hp1)^.oper[0].val) then
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+ Begin
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+ Paicpu(p)^.opcode := A_AND;
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+ l := (1 shl (Paicpu(p)^.oper[0].val))-1;
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+ Case Paicpu(p)^.opsize Of
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+ S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
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+ S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
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+ S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
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+ End;
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+ AsmL^.remove(hp1);
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+ dispose(hp1, done);
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+ End;
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+ End;
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+ A_XOR:
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+ If (Paicpu(p)^.oper[0].typ = top_reg) And
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+ (Paicpu(p)^.oper[1].typ = top_reg) And
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+ (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
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+ { temporarily change this to 'mov reg,0' to make it easier }
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+ { for the CSE. Will be changed back in pass 2 }
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+ begin
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+ paicpu(p)^.opcode := A_MOV;
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+ paicpu(p)^.loadconst(0,0);
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+ end;
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+ End;
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+ End;
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+ End;
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+ p := Pai(p^.next)
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+ End;
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+End;
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+
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+
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Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
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{First pass of peepholeoptimizations}
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@@ -279,9 +583,7 @@ Begin
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If (paicpu(p)^.opcode = A_JMP) Then
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Begin
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While GetNextInstruction(p, hp1) and
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- ((hp1^.typ <> ait_label) or
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- { skip unused labels, they're not referenced anywhere }
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- labelCanBeSkipped(pai_label(hp1))) Do
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+ (hp1^.typ <> ait_label) do
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If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
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Begin
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AsmL^.Remove(hp1);
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@@ -289,6 +591,7 @@ Begin
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End
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else break;
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End;
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+ { remove jumps to a label coming right after them }
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If GetNextInstruction(p, hp1) then
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Begin
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if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
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@@ -481,259 +784,53 @@ Begin
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{ change to
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fld/fst mem1 (hp1) fld/fst mem1
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fld mem1 (p) fadd/
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- faddp/ fmul st, st
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- fmulp st, st1 (hp2) }
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- Begin
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- AsmL^.Remove(p);
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- Dispose(p, Done);
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- p := hp1;
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- If (Paicpu(hp2)^.opcode = A_FADDP) Then
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- Paicpu(hp2)^.opcode := A_FADD
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- Else
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- Paicpu(hp2)^.opcode := A_FMUL;
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- Paicpu(hp2)^.oper[1].reg := R_ST;
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- End
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- Else
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- { change to
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- fld/fst mem1 (hp1) fld/fst mem1
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- fld mem1 (p) fld st}
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- Begin
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- Paicpu(p)^.changeopsize(S_FL);
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- Paicpu(p)^.loadreg(0,R_ST);
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- End
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- Else
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- Begin
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- Case Paicpu(hp2)^.opcode Of
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- A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
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- { change to
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- fld/fst mem1 (hp1) fld/fst mem1
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- fld mem2 (p) fxxx mem2
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- fxxxp st, st1 (hp2) }
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-
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- Begin
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- Case Paicpu(hp2)^.opcode Of
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- A_FADDP: Paicpu(p)^.opcode := A_FADD;
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- A_FMULP: Paicpu(p)^.opcode := A_FMUL;
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- A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
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- A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
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- A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
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- A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
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- End;
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- AsmL^.Remove(hp2);
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- Dispose(hp2, Done)
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- End
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- End
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- End
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- End;
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- A_FSTP,A_FISTP:
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- if doFpuLoadStoreOpt(asmL,p) then
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- continue;
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- A_IMUL:
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- {changes certain "imul const, %reg"'s to lea sequences}
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- Begin
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- If (Paicpu(p)^.oper[0].typ = Top_Const) And
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- (Paicpu(p)^.oper[1].typ = Top_Reg) And
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- (Paicpu(p)^.opsize = S_L) Then
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- If (Paicpu(p)^.oper[0].val = 1) Then
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- If (Paicpu(p)^.oper[2].typ = Top_None) Then
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- {remove "imul $1, reg"}
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- Begin
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- hp1 := Pai(p^.Next);
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- AsmL^.Remove(p);
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- Dispose(p, Done);
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- p := hp1;
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- Continue;
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- End
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- Else
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- {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
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- Begin
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- hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
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- InsertLLItem(AsmL, p^.previous, p^.next, hp1);
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- Dispose(p, Done);
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- p := hp1;
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- End
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- Else If
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- ((Paicpu(p)^.oper[2].typ = Top_Reg) or
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- (Paicpu(p)^.oper[2].typ = Top_None)) And
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- (aktoptprocessor < ClassP6) And
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- (Paicpu(p)^.oper[0].val <= 12) And
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- Not(CS_LittleSize in aktglobalswitches) And
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- (Not(GetNextInstruction(p, hp1)) Or
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- {GetNextInstruction(p, hp1) And}
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- Not((Pai(hp1)^.typ = ait_instruction) And
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- ((paicpu(hp1)^.opcode=A_Jcc) and
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- (paicpu(hp1)^.condition in [C_O,C_NO]))))
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- Then
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- Begin
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- Reset_reference(tmpref);
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- Case Paicpu(p)^.oper[0].val Of
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- 3: Begin
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- {imul 3, reg1, reg2 to
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- lea (reg1,reg1,2), reg2
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- imul 3, reg1 to
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- lea (reg1,reg1,2), reg1}
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- TmpRef.base := Paicpu(p)^.oper[1].reg;
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- TmpRef.ScaleFactor := 2;
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- If (Paicpu(p)^.oper[2].typ = Top_None) Then
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
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- Else
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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- InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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- Dispose(p, Done);
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- p := hp1;
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- End;
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- 5: Begin
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- {imul 5, reg1, reg2 to
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- lea (reg1,reg1,4), reg2
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- imul 5, reg1 to
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- lea (reg1,reg1,4), reg1}
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- TmpRef.base := Paicpu(p)^.oper[1].reg;
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- TmpRef.ScaleFactor := 4;
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- If (Paicpu(p)^.oper[2].typ = Top_None) Then
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
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- Else
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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- InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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- Dispose(p, Done);
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- p := hp1;
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- End;
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- 6: Begin
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- {imul 6, reg1, reg2 to
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- lea (,reg1,2), reg2
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- lea (reg2,reg1,4), reg2
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- imul 6, reg1 to
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- lea (reg1,reg1,2), reg1
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- add reg1, reg1}
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- If (aktoptprocessor <= Class386)
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- Then
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- Begin
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- If (Paicpu(p)^.oper[2].typ = Top_Reg)
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- Then
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- Begin
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- TmpRef.base := Paicpu(p)^.oper[2].reg;
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- TmpRef.ScaleFactor := 4;
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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- End
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- Else
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- Begin
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- hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
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- Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
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- End;
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- InsertLLItem(AsmL,p, p^.next, hp1);
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- Reset_reference(tmpref);
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- TmpRef.ScaleFactor := 2;
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- If (Paicpu(p)^.oper[2].typ = Top_Reg)
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- Then
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- Begin
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- TmpRef.base := R_NO;
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
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- Paicpu(p)^.oper[2].reg));
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- End
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- Else
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- Begin
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- TmpRef.base := Paicpu(p)^.oper[1].reg;
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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- End;
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- InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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- Dispose(p, Done);
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- p := Pai(hp1^.next);
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- End
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- End;
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- 9: Begin
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- {imul 9, reg1, reg2 to
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- lea (reg1,reg1,8), reg2
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- imul 9, reg1 to
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- lea (reg1,reg1,8), reg1}
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- TmpRef.base := Paicpu(p)^.oper[1].reg;
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- TmpRef.ScaleFactor := 8;
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- If (Paicpu(p)^.oper[2].typ = Top_None) Then
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
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- Else
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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- InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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- Dispose(p, Done);
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- p := hp1;
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- End;
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- 10: Begin
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- {imul 10, reg1, reg2 to
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- lea (reg1,reg1,4), reg2
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- add reg2, reg2
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- imul 10, reg1 to
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- lea (reg1,reg1,4), reg1
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- add reg1, reg1}
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- If (aktoptprocessor <= Class386) Then
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- Begin
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- If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
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- hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
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- Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
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- Else
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- hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
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- Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
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- InsertLLItem(AsmL,p, p^.next, hp1);
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- TmpRef.base := Paicpu(p)^.oper[1].reg;
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- TmpRef.ScaleFactor := 4;
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- If (Paicpu(p)^.oper[2].typ = Top_Reg)
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- Then
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
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- Else
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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- InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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- Dispose(p, Done);
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- p := Pai(hp1^.next);
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- End
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- End;
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- 12: Begin
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- {imul 12, reg1, reg2 to
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- lea (,reg1,4), reg2
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- lea (,reg1,8) reg2
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- imul 12, reg1 to
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- lea (reg1,reg1,2), reg1
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- lea (,reg1,4), reg1}
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- If (aktoptprocessor <= Class386)
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- Then
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- Begin
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
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- Begin
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- TmpRef.base := Paicpu(p)^.oper[2].reg;
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- TmpRef.ScaleFactor := 8;
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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- End
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- Else
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- Begin
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- TmpRef.base := R_NO;
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- TmpRef.ScaleFactor := 4;
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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- End;
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- InsertLLItem(AsmL,p, p^.next, hp1);
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- Reset_reference(tmpref);
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- TmpRef.Index := Paicpu(p)^.oper[1].reg;
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- If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
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- Begin
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- TmpRef.base := R_NO;
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- TmpRef.ScaleFactor := 4;
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
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- End
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- Else
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- Begin
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- TmpRef.base := Paicpu(p)^.oper[1].reg;
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- TmpRef.ScaleFactor := 2;
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- hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
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- End;
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- InsertLLItem(AsmL,p^.previous, p^.next, hp1);
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- Dispose(p, Done);
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- p := Pai(hp1^.next);
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- End
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- End
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- End;
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- End;
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+ faddp/ fmul st, st
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+ fmulp st, st1 (hp2) }
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+ Begin
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+ AsmL^.Remove(p);
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+ Dispose(p, Done);
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+ p := hp1;
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+ If (Paicpu(hp2)^.opcode = A_FADDP) Then
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+ Paicpu(hp2)^.opcode := A_FADD
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+ Else
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+ Paicpu(hp2)^.opcode := A_FMUL;
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+ Paicpu(hp2)^.oper[1].reg := R_ST;
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+ End
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+ Else
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+ { change to
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+ fld/fst mem1 (hp1) fld/fst mem1
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+ fld mem1 (p) fld st}
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+ Begin
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+ Paicpu(p)^.changeopsize(S_FL);
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+ Paicpu(p)^.loadreg(0,R_ST);
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+ End
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+ Else
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+ Begin
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+ Case Paicpu(hp2)^.opcode Of
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+ A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
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+ { change to
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+ fld/fst mem1 (hp1) fld/fst mem1
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+ fld mem2 (p) fxxx mem2
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+ fxxxp st, st1 (hp2) }
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+
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+ Begin
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+ Case Paicpu(hp2)^.opcode Of
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+ A_FADDP: Paicpu(p)^.opcode := A_FADD;
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+ A_FMULP: Paicpu(p)^.opcode := A_FMUL;
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+ A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
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+ A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
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+ A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
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+ A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
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+ End;
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+ AsmL^.Remove(hp2);
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+ Dispose(hp2, Done)
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+ End
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+ End
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+ End
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End;
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+ A_FSTP,A_FISTP:
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+ if doFpuLoadStoreOpt(asmL,p) then
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+ continue;
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A_LEA:
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Begin
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{removes seg register prefixes from LEA operations, as they
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@@ -784,7 +881,6 @@ Begin
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end;
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end;
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end;
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-
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End;
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A_MOV:
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Begin
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@@ -1420,71 +1516,6 @@ Begin
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p := hp1;
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End
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End;
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- A_SAR, A_SHR:
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- {changes the code sequence
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- shr/sar const1, x
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- shl const2, x
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- to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
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- Begin
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- If GetNextInstruction(p, hp1) And
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- (pai(hp1)^.typ = ait_instruction) and
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- (Paicpu(hp1)^.opcode = A_SHL) and
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- (Paicpu(p)^.oper[0].typ = top_const) and
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- (Paicpu(hp1)^.oper[0].typ = top_const) and
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- (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
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- (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
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- OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
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- Then
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- If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
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- Not(CS_LittleSize In aktglobalswitches)
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- Then
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- { shr/sar const1, %reg
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- shl const2, %reg
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- with const1 > const2 }
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- Begin
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- Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
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- Paicpu(hp1)^.opcode := A_AND;
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- l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
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- Case Paicpu(p)^.opsize Of
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- S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
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- S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
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- S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
|
|
|
- End;
|
|
|
- End
|
|
|
- Else
|
|
|
- If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
|
|
|
- Not(CS_LittleSize In aktglobalswitches)
|
|
|
- Then
|
|
|
- { shr/sar const1, %reg
|
|
|
- shl const2, %reg
|
|
|
- with const1 < const2 }
|
|
|
- Begin
|
|
|
- Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
|
|
|
- Paicpu(p)^.opcode := A_AND;
|
|
|
- l := (1 shl (Paicpu(p)^.oper[0].val))-1;
|
|
|
- Case Paicpu(p)^.opsize Of
|
|
|
- S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
|
|
|
- S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
|
|
|
- S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
|
|
|
- End;
|
|
|
- End
|
|
|
- Else
|
|
|
- { shr/sar const1, %reg
|
|
|
- shl const2, %reg
|
|
|
- with const1 = const2 }
|
|
|
- if (Paicpu(p)^.oper[0].val = Paicpu(hp1)^.oper[0].val) then
|
|
|
- Begin
|
|
|
- Paicpu(p)^.opcode := A_AND;
|
|
|
- l := (1 shl (Paicpu(p)^.oper[0].val))-1;
|
|
|
- Case Paicpu(p)^.opsize Of
|
|
|
- S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
|
|
|
- S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
|
|
|
- S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
|
|
|
- End;
|
|
|
- AsmL^.remove(hp1);
|
|
|
- dispose(hp1, done);
|
|
|
- End;
|
|
|
- End;
|
|
|
A_SETcc :
|
|
|
{ changes
|
|
|
setcc (funcres) setcc reg
|
|
|
@@ -1604,6 +1635,7 @@ end;
|
|
|
|
|
|
Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
|
|
|
|
|
|
+{$ifdef USECMOV}
|
|
|
function CanBeCMOV(p : pai) : boolean;
|
|
|
|
|
|
begin
|
|
|
@@ -1613,6 +1645,7 @@ Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
|
|
|
(paicpu(p)^.oper[0].typ in [top_reg,top_ref]) and
|
|
|
(paicpu(p)^.oper[1].typ in [top_reg,top_ref]);
|
|
|
end;
|
|
|
+{$endif USECMOV}
|
|
|
|
|
|
var
|
|
|
p,hp1,hp2: pai;
|
|
|
@@ -1633,20 +1666,6 @@ Begin
|
|
|
Ait_Instruction:
|
|
|
Begin
|
|
|
Case Paicpu(p)^.opcode Of
|
|
|
- A_CALL:
|
|
|
- If (AktOptProcessor < ClassP6) And
|
|
|
- GetNextInstruction(p, hp1) And
|
|
|
- (hp1^.typ = ait_instruction) And
|
|
|
- (paicpu(hp1)^.opcode = A_JMP) Then
|
|
|
- Begin
|
|
|
- Inc(paicpu(hp1)^.oper[0].sym^.refs);
|
|
|
- hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
|
|
|
- InsertLLItem(AsmL, p^.previous, p, hp2);
|
|
|
- Paicpu(p)^.opcode := A_JMP;
|
|
|
- AsmL^.Remove(hp1);
|
|
|
- Dispose(hp1, Done)
|
|
|
- End;
|
|
|
-
|
|
|
{$ifdef USECMOV}
|
|
|
A_Jcc:
|
|
|
if (aktspecificoptprocessor=ClassP6) then
|
|
|
@@ -1833,59 +1852,6 @@ Begin
|
|
|
p := hp1
|
|
|
End;
|
|
|
End
|
|
|
- else if (Paicpu(p)^.oper[0].typ = Top_Const) And
|
|
|
- (Paicpu(p)^.oper[0].val = 0) And
|
|
|
- (Paicpu(p)^.oper[1].typ = Top_Reg) Then
|
|
|
- { change "mov $0, %reg" into "xor %reg, %reg" }
|
|
|
- Begin
|
|
|
- Paicpu(p)^.opcode := A_XOR;
|
|
|
- Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
|
|
|
- End
|
|
|
- End;
|
|
|
- A_MOVZX:
|
|
|
- Begin
|
|
|
- If (Paicpu(p)^.oper[1].typ = top_reg) Then
|
|
|
- If (Paicpu(p)^.oper[0].typ = top_reg)
|
|
|
- Then
|
|
|
- Case Paicpu(p)^.opsize of
|
|
|
- S_BL:
|
|
|
- Begin
|
|
|
- If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
|
|
|
- Not(CS_LittleSize in aktglobalswitches) And
|
|
|
- (aktoptprocessor = ClassP5)
|
|
|
- Then
|
|
|
- {Change "movzbl %reg1, %reg2" to
|
|
|
- "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
|
|
|
- PentiumMMX}
|
|
|
- Begin
|
|
|
- hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
|
|
|
- Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
|
|
|
- InsertLLItem(AsmL,p^.previous, p, hp1);
|
|
|
- Paicpu(p)^.opcode := A_MOV;
|
|
|
- Paicpu(p)^.changeopsize(S_B);
|
|
|
- Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
|
|
|
- End;
|
|
|
- End;
|
|
|
- End
|
|
|
- Else
|
|
|
- If (Paicpu(p)^.oper[0].typ = top_ref) And
|
|
|
- (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
|
|
|
- (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
|
|
|
- Not(CS_LittleSize in aktglobalswitches) And
|
|
|
- IsGP32Reg(Paicpu(p)^.oper[1].reg) And
|
|
|
- (aktoptprocessor = ClassP5) And
|
|
|
- (Paicpu(p)^.opsize = S_BL)
|
|
|
- Then
|
|
|
- {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
|
|
|
- Pentium and PentiumMMX}
|
|
|
- Begin
|
|
|
- hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
|
|
|
- Paicpu(p)^.oper[1].reg));
|
|
|
- Paicpu(p)^.opcode := A_MOV;
|
|
|
- Paicpu(p)^.changeopsize(S_B);
|
|
|
- Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
|
|
|
- InsertLLItem(AsmL,p^.previous, p, hp1);
|
|
|
- End;
|
|
|
End;
|
|
|
A_TEST, A_OR:
|
|
|
{removes the line marked with (x) from the sequence
|
|
|
@@ -1942,11 +1908,111 @@ Begin
|
|
|
End;
|
|
|
End;
|
|
|
|
|
|
+Procedure PostPeepHoleOpts(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
|
|
|
+var
|
|
|
+ p,hp1,hp2: pai;
|
|
|
+Begin
|
|
|
+ P := BlockStart;
|
|
|
+ While (P <> BlockEnd) Do
|
|
|
+ Begin
|
|
|
+ Case P^.Typ Of
|
|
|
+ Ait_Instruction:
|
|
|
+ Begin
|
|
|
+ Case Paicpu(p)^.opcode Of
|
|
|
+ A_CALL:
|
|
|
+ If (AktOptProcessor < ClassP6) And
|
|
|
+ GetNextInstruction(p, hp1) And
|
|
|
+ (hp1^.typ = ait_instruction) And
|
|
|
+ (paicpu(hp1)^.opcode = A_JMP) Then
|
|
|
+ Begin
|
|
|
+ Inc(paicpu(hp1)^.oper[0].sym^.refs);
|
|
|
+ hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
|
|
|
+ InsertLLItem(AsmL, p^.previous, p, hp2);
|
|
|
+ Paicpu(p)^.opcode := A_JMP;
|
|
|
+ AsmL^.Remove(hp1);
|
|
|
+ Dispose(hp1, Done)
|
|
|
+ End;
|
|
|
+ A_MOV:
|
|
|
+ if (Paicpu(p)^.oper[0].typ = Top_Const) And
|
|
|
+ (Paicpu(p)^.oper[0].val = 0) And
|
|
|
+ (Paicpu(p)^.oper[1].typ = Top_Reg) Then
|
|
|
+ { change "mov $0, %reg" into "xor %reg, %reg" }
|
|
|
+ Begin
|
|
|
+ Paicpu(p)^.opcode := A_XOR;
|
|
|
+ Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
|
|
|
+ End;
|
|
|
+ A_MOVZX:
|
|
|
+ Begin
|
|
|
+ If (Paicpu(p)^.oper[1].typ = top_reg) Then
|
|
|
+ If (Paicpu(p)^.oper[0].typ = top_reg)
|
|
|
+ Then
|
|
|
+ Case Paicpu(p)^.opsize of
|
|
|
+ S_BL:
|
|
|
+ Begin
|
|
|
+ If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
|
|
|
+ Not(CS_LittleSize in aktglobalswitches) And
|
|
|
+ (aktoptprocessor = ClassP5)
|
|
|
+ Then
|
|
|
+ {Change "movzbl %reg1, %reg2" to
|
|
|
+ "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
|
|
|
+ PentiumMMX}
|
|
|
+ Begin
|
|
|
+ hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
|
|
|
+ Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
|
|
|
+ InsertLLItem(AsmL,p^.previous, p, hp1);
|
|
|
+ Paicpu(p)^.opcode := A_MOV;
|
|
|
+ Paicpu(p)^.changeopsize(S_B);
|
|
|
+ Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
|
|
|
+ End;
|
|
|
+ End;
|
|
|
+ End
|
|
|
+ Else
|
|
|
+ If (Paicpu(p)^.oper[0].typ = top_ref) And
|
|
|
+ (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
|
|
|
+ (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
|
|
|
+ Not(CS_LittleSize in aktglobalswitches) And
|
|
|
+ IsGP32Reg(Paicpu(p)^.oper[1].reg) And
|
|
|
+ (aktoptprocessor = ClassP5) And
|
|
|
+ (Paicpu(p)^.opsize = S_BL)
|
|
|
+ Then
|
|
|
+ {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
|
|
|
+ Pentium and PentiumMMX}
|
|
|
+ Begin
|
|
|
+ hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
|
|
|
+ Paicpu(p)^.oper[1].reg));
|
|
|
+ Paicpu(p)^.opcode := A_MOV;
|
|
|
+ Paicpu(p)^.changeopsize(S_B);
|
|
|
+ Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
|
|
|
+ InsertLLItem(AsmL,p^.previous, p, hp1);
|
|
|
+ End;
|
|
|
+ End;
|
|
|
+ End;
|
|
|
+ End;
|
|
|
+ End;
|
|
|
+ p := Pai(p^.next)
|
|
|
+ End;
|
|
|
+End;
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
End.
|
|
|
|
|
|
{
|
|
|
$Log$
|
|
|
- Revision 1.1 2000-10-15 09:47:43 peter
|
|
|
+ Revision 1.2 2000-10-24 10:40:54 jonas
|
|
|
+ + register renaming ("fixes" bug1088)
|
|
|
+ * changed command line options meanings for optimizer:
|
|
|
+ O2 now means peepholopts, CSE and register renaming in 1 pass
|
|
|
+ O3 is the same, but repeated until no further optimizations are
|
|
|
+ possible or until 5 passes have been done (to avoid endless loops)
|
|
|
+ * changed aopt386 so it does this looping
|
|
|
+ * added some procedures from csopt386 to the interface because they're
|
|
|
+ used by rropt386 as well
|
|
|
+ * some changes to csopt386 and daopt386 so that newly added instructions
|
|
|
+ by the CSE get optimizer info (they were simply skipped previously),
|
|
|
+ this fixes some bugs
|
|
|
+
|
|
|
+ Revision 1.1 2000/10/15 09:47:43 peter
|
|
|
* moved to i386/
|
|
|
|
|
|
Revision 1.13 2000/10/02 13:01:29 jonas
|
Jonas Maebe