+ implemented 64-bit OP_SHR,OP_SHL and OP_SAR in a_op64_reg_reg for i8086 and

  use it in the shl/shr node for code generation.

git-svn-id: trunk@36018 -

compiler/i8086/cgcpu.pas

@@ -2873,6 +2873,8 @@ unit cgcpu;
     procedure tcg64f8086.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
       var
         op1,op2 : TAsmOp;
+        l2, l3: TAsmLabel;
+        ai: taicpu;
       begin
         case op of
           OP_NEG :
@@ -2897,6 +2899,48 @@ unit cgcpu;
               cg.a_op_reg_reg(list,OP_NOT,OS_32,regdst.reghi,regdst.reghi);
               exit;
             end;
+          OP_SHR,OP_SHL,OP_SAR:
+            begin
+              { load right operators in a register }
+              cg.getcpuregister(list,NR_CX);
+
+              cg.a_load_reg_reg(list,OS_16,OS_16,regsrc.reglo,NR_CX);
+
+              current_asmdata.getjumplabel(l2);
+              current_asmdata.getjumplabel(l3);
+              cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
+              list.concat(taicpu.op_const_reg(A_AND,S_W,63,NR_CX));
+              cg.a_jmp_flags(list,F_E,l3);
+              cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
+              cg.a_label(list,l2);
+              case op of
+                OP_SHL:
+                  begin
+                    cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
+                    list.concat(taicpu.op_const_reg(A_SHL,S_W,1,regdst.reglo));
+                    list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(regdst.reglo)));
+                    list.concat(taicpu.op_const_reg(A_RCL,S_W,1,regdst.reghi));
+                    list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(regdst.reghi)));
+                    cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
+                  end;
+                OP_SHR,OP_SAR:
+                  begin
+                    cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
+                    cg.a_op_const_reg(list,op,OS_16,1,GetNextReg(regdst.reghi));
+                    list.concat(taicpu.op_const_reg(A_RCR,S_W,1,regdst.reghi));
+                    list.concat(taicpu.op_const_reg(A_RCR,S_W,1,GetNextReg(regdst.reglo)));
+                    list.concat(taicpu.op_const_reg(A_RCR,S_W,1,regdst.reglo));
+                    cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
+                  end;
+              end;
+              ai:=Taicpu.Op_Sym(A_LOOP,S_W,l2);
+              ai.is_jmp := True;
+              list.Concat(ai);
+              cg.a_label(list,l3);
+
+              cg.ungetcpuregister(list,NR_CX);
+              exit;
+            end;
         end;
         get_64bit_ops(op,op1,op2);
         if op in [OP_ADD,OP_SUB] then

compiler/i8086/n8086mat.pas

@@ -388,8 +388,7 @@ implementation
       var
         hreg64hi,hreg64lo:Tregister;
         v : TConstExprInt;
-        l2,l3:Tasmlabel;
-        ai: taicpu;
+        tmpreg64: tregister64;
       begin
         location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
 
@@ -413,39 +412,13 @@ implementation
         else
           begin
             { load right operators in a register }
-            cg.getcpuregister(current_asmdata.CurrAsmList,NR_CX);
-
-            hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,u16inttype,right.location,NR_CX);
-
-            { left operator is already in a register }
-            { hence are both in a register }
-            { is it in the case CX ? }
-
-            current_asmdata.getjumplabel(l2);
-            current_asmdata.getjumplabel(l3);
-            emit_const_reg(A_AND,S_W,63,NR_CX);
-            cg.a_jmp_flags(current_asmdata.CurrAsmList,F_E,l3);
-            cg.a_label(current_asmdata.CurrAsmList,l2);
+            tmpreg64.reghi:=NR_NO;
+            tmpreg64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_16);
+            hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,u16inttype,right.location,tmpreg64.reglo);
             if nodetype=shln then
-              begin
-                emit_const_reg(A_SHL,S_W,1,hreg64lo);
-                emit_const_reg(A_RCL,S_W,1,GetNextReg(hreg64lo));
-                emit_const_reg(A_RCL,S_W,1,hreg64hi);
-                emit_const_reg(A_RCL,S_W,1,GetNextReg(hreg64hi));
-              end
+              cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_64,tmpreg64,location.register64)
             else
-              begin
-                emit_const_reg(A_SHR,S_W,1,GetNextReg(hreg64hi));
-                emit_const_reg(A_RCR,S_W,1,hreg64hi);
-                emit_const_reg(A_RCR,S_W,1,GetNextReg(hreg64lo));
-                emit_const_reg(A_RCR,S_W,1,hreg64lo);
-              end;
-            ai:=Taicpu.Op_Sym(A_LOOP,S_W,l2);
-            ai.is_jmp := True;
-            current_asmdata.CurrAsmList.Concat(ai);
-            cg.a_label(current_asmdata.CurrAsmList,l3);
-
-            cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_CX);
+              cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_64,tmpreg64,location.register64);
           end;
       end;