* m68k: initial support for ROL/ROR operations, defining 'cpurox' for CPU target can actually enable them. However it cannot be done outright because these instructions do not exits on Coldfire, and internal processing of RoX,Sar,BsX, etc. can not yet be switched depending on CPU subtype.

git-svn-id: trunk@28101 -

compiler/m68k/aasmcpu.pas

@@ -469,6 +469,7 @@ type
               result:=operand_write;
           A_ADD, A_ADDQ, A_ADDX, A_SUB, A_SUBQ, A_SUBX,
           A_AND, A_LSR, A_LSL, A_ASR, A_ASL, A_EOR, A_EORI, A_OR,
+          A_ROL, A_ROR, A_ROXL, A_ROXR,
           A_MULS, A_MULU, A_DIVS, A_DIVU, A_DIVSL, A_DIVUL:
             if opnr=1 then
               result:=operand_readwrite;

compiler/m68k/cgcpu.pas

@@ -152,8 +152,8 @@ unit cgcpu;
        A_LSR,
        A_SUB,
        A_EOR,
-       A_NONE,
-       A_NONE
+       A_ROL,
+       A_ROR
       );
 
       { opcode with extend bits table lookup, used by 64bit cg }
@@ -1092,6 +1092,8 @@ unit cgcpu;
                         call_rtl_mul_const_reg(list, size, a, reg,'fpc_mul_longint');
                   end;
               end;
+          OP_ROL,
+          OP_ROR,
           OP_SAR,
           OP_SHL,
           OP_SHR :