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@@ -84,6 +84,7 @@ Implementation
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case p.typ of
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case p.typ of
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ait_instruction:
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ait_instruction:
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begin
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begin
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+ (* optimization proved not to be safe, see tw4768.pp
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{
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{
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change
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change
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<op> reg,x,y
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<op> reg,x,y
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@@ -118,6 +119,7 @@ Implementation
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hp1.free;
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hp1.free;
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end
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end
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else
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else
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+ *)
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case taicpu(p).opcode of
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case taicpu(p).opcode of
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A_STR:
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A_STR:
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begin
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begin
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@@ -129,7 +131,7 @@ Implementation
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mov reg2,reg1
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mov reg2,reg1
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}
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}
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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- getnextinstruction(p,hp1) and
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+ GetNextInstruction(p,hp1) and
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(hp1.typ = ait_instruction) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opcode = A_LDR) and
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(taicpu(hp1).opcode = A_LDR) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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@@ -148,7 +150,39 @@ Implementation
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end;
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end;
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result := true;
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result := true;
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end;
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end;
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- end;
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+ end;
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+ A_LDR:
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+ begin
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+ { change
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+ ldr reg1,ref
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+ ldr reg2,ref
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+ into
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+ ldr reg1,ref
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+ mov reg2,reg1
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+ }
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+ if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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+ GetNextInstruction(p,hp1) and
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+ (hp1.typ = ait_instruction) and
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+ (taicpu(hp1).opcode = A_LDR) and
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+ RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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+ (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.index) and
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+ (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.base) and
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+ (taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
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+ begin
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+ if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
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+ begin
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+ asml.remove(hp1);
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+ hp1.free;
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+ end
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+ else
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+ begin
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+ taicpu(hp1).opcode:=A_MOV;
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+ taicpu(hp1).oppostfix:=PF_None;
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+ taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
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+ end;
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+ result := true;
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+ end;
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+ end;
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A_MOV:
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A_MOV:
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begin
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begin
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{ fold
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{ fold
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