* Moved method g_flag2reg from tcgppc (in both powerpc and powerpc64) to tcgppcgen class, since it is identical for both targets.

git-svn-id: trunk@27589 -

compiler/powerpc/cgcpu.pas

@@ -62,8 +62,6 @@ unit cgcpu;
         procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
         procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
 
-        procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
-
         procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
         procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
         procedure g_save_registers(list:TAsmList); override;
@@ -689,47 +687,6 @@ const
          a_jmp(list,A_BC,c.cond,c.cr-RS_CR0,l);
        end;
 
-     procedure tcgppc.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
-
-       var
-         testbit: byte;
-         bitvalue: boolean;
-
-       begin
-         { get the bit to extract from the conditional register + its }
-         { requested value (0 or 1)                                   }
-         testbit := ((f.cr-RS_CR0) * 4);
-         case f.flag of
-           F_EQ,F_NE:
-             begin
-               inc(testbit,2);
-               bitvalue := f.flag = F_EQ;
-             end;
-           F_LT,F_GE:
-             begin
-               bitvalue := f.flag = F_LT;
-             end;
-           F_GT,F_LE:
-             begin
-               inc(testbit);
-               bitvalue := f.flag = F_GT;
-             end;
-           else
-             internalerror(200112261);
-         end;
-         { load the conditional register in the destination reg }
-         list.concat(taicpu.op_reg(A_MFCR,reg));
-         { we will move the bit that has to be tested to bit 0 by rotating }
-         { left                                                            }
-         testbit := (testbit + 1) and 31;
-         { extract bit }
-         list.concat(taicpu.op_reg_reg_const_const_const(
-           A_RLWINM,reg,reg,testbit,31,31));
-         { if we need the inverse, xor with 1 }
-         if not bitvalue then
-           list.concat(taicpu.op_reg_reg_const(A_XORI,reg,reg,1));
-       end;
-
 (*
      procedure tcgppc.g_cond2reg(list: TAsmList; const f: TAsmCond; reg: TRegister);
 

compiler/powerpc64/cgcpu.pas

@@ -71,9 +71,6 @@ type
     procedure a_jmp_flags(list: TAsmList; const f: TResFlags; l: tasmlabel);
       override;
 
-    procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags;
-      reg: TRegister); override;
-
     { need to override this for ppc64 to avoid calling CG methods which allocate
       registers during creation of the interface wrappers to subtract ioffset from
       the self pointer. But register allocation does not take place for them (which
@@ -1088,45 +1085,6 @@ begin
   a_jmp(list, A_BC, c.cond, c.cr - RS_CR0, l);
 end;
 
-procedure tcgppc.g_flags2reg(list: TAsmList; size: TCgSize; const f:
-  TResFlags; reg: TRegister);
-var
-  testbit: byte;
-  bitvalue: boolean;
-begin
-  { get the bit to extract from the conditional register + its requested value (0 or 1) }
-  testbit := ((f.cr - RS_CR0) * 4);
-  case f.flag of
-    F_EQ, F_NE:
-      begin
-        inc(testbit, 2);
-        bitvalue := f.flag = F_EQ;
-      end;
-    F_LT, F_GE:
-      begin
-        bitvalue := f.flag = F_LT;
-      end;
-    F_GT, F_LE:
-      begin
-        inc(testbit);
-        bitvalue := f.flag = F_GT;
-      end;
-  else
-    internalerror(200112261);
-  end;
-  { load the conditional register in the destination reg }
-  list.concat(taicpu.op_reg(A_MFCR, reg));
-  { we will move the bit that has to be tested to bit 0 by rotating left }
-  testbit := (testbit + 1) and 31;
-  { extract bit }
-  list.concat(taicpu.op_reg_reg_const_const_const(
-    A_RLWINM,reg,reg,testbit,31,31));
-
-  { if we need the inverse, xor with 1 }
-  if not bitvalue then
-    list.concat(taicpu.op_reg_reg_const(A_XORI, reg, reg, 1));
-end;
-
 { *********** entry/exit code and address loading ************ }
 
 procedure tcgppc.g_save_registers(list: TAsmList);

compiler/ppcgen/cgppc.pas

@@ -69,6 +69,7 @@ unit cgppc;
         procedure get_aix_toc_sym(list: TAsmList; const symname: string; const flags: tindsymflags; out ref: treference; force_direct_toc: boolean);
         procedure g_load_check_simple(list: TAsmList; const ref: treference; size: aint);
         procedure g_external_wrapper(list: TAsmList; pd: TProcDef; const externalname: string); override;
+        procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
        protected
         function g_indirect_sym_load(list:TAsmList;const symname: string; const flags: tindsymflags): tregister; override;
         function  get_darwin_call_stub(const s: string; weak: boolean): tasmsymbol;
@@ -1002,6 +1003,45 @@ unit cgppc;
       end;
 
 
+    procedure tcgppcgen.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
+      var
+        testbit: byte;
+        bitvalue: boolean;
+      begin
+        { get the bit to extract from the conditional register + its requested value (0 or 1) }
+        testbit := ((f.cr - RS_CR0) * 4);
+        case f.flag of
+          F_EQ, F_NE:
+            begin
+              inc(testbit, 2);
+              bitvalue := f.flag = F_EQ;
+            end;
+          F_LT, F_GE:
+            begin
+              bitvalue := f.flag = F_LT;
+            end;
+          F_GT, F_LE:
+            begin
+              inc(testbit);
+              bitvalue := f.flag = F_GT;
+            end;
+        else
+          internalerror(200112261);
+        end;
+        { load the conditional register in the destination reg }
+        list.concat(taicpu.op_reg(A_MFCR, reg));
+        { we will move the bit that has to be tested to bit 0 by rotating left }
+        testbit := (testbit + 1) and 31;
+        { extract bit }
+        list.concat(taicpu.op_reg_reg_const_const_const(
+          A_RLWINM,reg,reg,testbit,31,31));
+
+        { if we need the inverse, xor with 1 }
+        if not bitvalue then
+          list.concat(taicpu.op_reg_reg_const(A_XORI, reg, reg, 1));
+      end;
+
+
     function tcgppcgen.fixref(list: TAsmList; var ref: treference): boolean;
       var
         tmpreg: tregister;