There is code in the register allocator to restrict register allocation to the

first 16 registers in RISC-V RVE and RVEC modes.  However, there was still
code in tcpuparamanager.create_paraloc_info_intern that allowed the allocation
of up to register X17 in RVE and RVEC modes.  Modified this function to
take the processor mode into account and restrict it to X0..X15 in RVE and RVEC modes.

Also put conditional code in setjump.inc assembler code to only set the first
16 registers in RVE and RVEC modes.

The entire embedded-riscv32 RTL can now compile successfuly in RVEC mode.

compiler/riscv32/cpuinfo.pas

@@ -211,7 +211,6 @@ Const
        { cpu_rv32e     } [CPURV_HAS_16REGISTERS],
        { cpu_rv32imc   } [CPURV_HAS_MUL,CPURV_HAS_COMPACT],
        { cpu_rv32ec    } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT]
-
      );
 
 Implementation

compiler/riscv32/cpupara.pas

@@ -306,6 +306,7 @@ unit cpupara;
          stack_offset: longint;
          paralen: aint;
          nextintreg,nextfloatreg,nextmmreg, maxfpureg : tsuperregister;
+         MaxIntReg : TSuperRegister;
          locdef,
          fdef,
          paradef : tdef;
@@ -328,6 +329,9 @@ unit cpupara;
          nextmmreg := curmmreg;
          stack_offset := cur_stack_offset;
          maxfpureg := RS_F17;
+         if CPURV_HAS_16REGISTERS in cpu_capabilities[current_settings.cputype] then
+          MaxIntReg := RS_X15 else
+          MaxIntReg := RS_X17;
 
           for i:=0 to paras.count-1 do
             begin
@@ -398,7 +402,7 @@ unit cpupara;
                   { In case of po_delphi_nested_cc, the parent frame pointer
                     is always passed on the stack. }
                   if (loc = LOC_REGISTER) and
-                     (nextintreg <= RS_X17) and
+                     (nextintreg <= MaxIntReg) and
                      (not(vo_is_parentfp in hp.varoptions) or
                       not(po_delphi_nested_cc in p.procoptions)) then
                     begin
@@ -424,7 +428,7 @@ unit cpupara;
                       dec(paralen,tcgsize2size[paraloc^.size]);
                     end
                   else if (loc = LOC_FPUREGISTER) and
-                          (nextintreg <= RS_X17) then
+                          (nextintreg <= MaxIntReg) then
                     begin
                       paraloc^.loc:=loc;
                       paraloc^.size := paracgsize;
@@ -475,7 +479,7 @@ unit cpupara;
 
                        inc(stack_offset,align(paralen,4));
                        while (paralen > 0) and
-                             (nextintreg < RS_X18) do
+                             (nextintreg <= MaxIntReg) do
                           begin
                             inc(nextintreg);
                             dec(paralen,sizeof(pint));

rtl/embedded/riscv32/CH32VxBootstrap.pp

@@ -1,3 +1,16 @@
+{
+    Copyright (c) 1998-2023 by the Free Pascal development team
+
+    Bootstrap code specific to WCH CH32Vxxx RISC-V microcontrollers.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
 unit CH32VxBootstrap;
 
 interface

rtl/embedded/riscv32/riscv32_start.inc

@@ -19,7 +19,6 @@ procedure InitMemAndStart; noreturn;
 var
   pdest, psrc, pend: PLongWord;
 begin
-
   pdest:=@_data;
   psrc:=@_etext;
   pend:=@_bss_start;