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+ RiscV: CPU type rv32imafc added

florian 1 week ago
parent
commit
ca1511b83c
2 changed files with 5 additions and 2 deletions
  1. 2 2
      compiler/riscv/agrvgas.pas
  2. 3 0
      compiler/riscv32/cpuinfo.pas

+ 2 - 2
compiler/riscv/agrvgas.pas

@@ -233,8 +233,8 @@ unit agrvgas;
       const
       const
         arch_str: array[boolean,tcputype] of string[18] = (
         arch_str: array[boolean,tcputype] of string[18] = (
 {$ifdef RISCV32}
 {$ifdef RISCV32}
-          ('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32imafdc','rv32imaf','rv32imafd','rv32ec','rv32gc','rv32gc_zba_zbb_zbs'),
-          ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imaf','rv32imafd','rv32ecfd','rv32gc','rv32gc_zba_zbb_zbs')
+          ('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32imafdc','rv32imaf','rv32imafc','rv32imafd','rv32ec','rv32gc','rv32gc_zba_zbb_zbs'),
+          ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imaf','rv32imafc','rv32imafd','rv32ecfd','rv32gc','rv32gc_zba_zbb_zbs')
 {$endif RISCV32}
 {$endif RISCV32}
 {$ifdef RISCV64}
 {$ifdef RISCV64}
           ('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gc_zba_zbb_zbs'),
           ('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gc_zba_zbb_zbs'),

+ 3 - 0
compiler/riscv32/cpuinfo.pas

@@ -43,6 +43,7 @@ Type
        cpu_rv32imc,
        cpu_rv32imc,
        cpu_rv32imafdc,
        cpu_rv32imafdc,
        cpu_rv32imaf,
        cpu_rv32imaf,
+       cpu_rv32imafc,
        cpu_rv32imafd,
        cpu_rv32imafd,
        cpu_rv32ec,
        cpu_rv32ec,
        cpu_rv32gc,
        cpu_rv32gc,
@@ -179,6 +180,7 @@ Const
      'RV32IMC',
      'RV32IMC',
      'RV32IMAFDC',
      'RV32IMAFDC',
      'RV32IMAF',
      'RV32IMAF',
+     'RV32IMAFC',
      'RV32IMAFD',
      'RV32IMAFD',
      'RV32EC',
      'RV32EC',
      'RV32GC',
      'RV32GC',
@@ -247,6 +249,7 @@ Const
        { cpu_rv32imc   } [CPURV_HAS_MUL,CPURV_HAS_COMPACT],
        { cpu_rv32imc   } [CPURV_HAS_MUL,CPURV_HAS_COMPACT],
        { cpu_rv32imafdc} [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv32imafdc} [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv32imaf  } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F],
        { cpu_rv32imaf  } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F],
+       { cpu_rv32imafc } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F,CPURV_HAS_COMPACT],
        { cpu_rv32imafd } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv32imafd } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv32ec    } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT],
        { cpu_rv32ec    } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT],
        { cpu_rv32gc    } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv32gc    } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],